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This commit ports the stm32f20xxf40xx_flash.c driver to the STM32F7 platform and fixes some relevant problems in the header files.

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This commit is contained in:
Evgeniy Bobkov
2018-08-03 11:02:59 -06:00
committed by Gregory Nutt
parent bfc8f9dfdb
commit caa7fa7327
7 changed files with 432 additions and 8 deletions
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arch/arm/Kconfig
+1
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@@ -297,6 +297,7 @@ config ARCH_CHIP_STM32F7
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
arch/arm/src/stm32f7/Make.defs
+1 -1
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@@ -108,7 +108,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
CHIP_CSRCS += stm32_start.c stm32_capture.c
CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_flash.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h
+1 -1
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@@ -162,7 +162,7 @@
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT)) /* Sector n, n=0..7 */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
+1 -1
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@@ -151,7 +151,7 @@
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) ((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */
# define FLASH_CR_SNB(n) (((uint32_t)((n) % 8) << FLASH_CR_SNB_SHIFT) | ((n / 8) << 6)) /* Sector n, n=0..23 */
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h
+4 -4
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@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -106,8 +106,8 @@
# define STM32_FLASH_NPAGES 12
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256))
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
_K(128), _K(256), _K(256), _K(256) \
_K(256), _K(256), _K(256), _K(256)}
_K(128), _K(256), _K(256), _K(256), \
_K(256), _K(256), _K(256), _K(256)}
#endif
/* Register Offsets *****************************************************************/
@@ -165,7 +165,7 @@
#define FLASH_CR_MER_MER1 (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
#define FLASH_CR_SNB_MASK (0x1f << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) ((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
# define FLASH_CR_SNB(n) (((uint32_t)((n) % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
arch/arm/src/stm32f7/stm32_flash.c
+423
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h
+1 -1
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@@ -136,7 +136,7 @@
#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT)) /* Sector n, n=0..7 */
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
/* Bits 11-14: Reserved */
#define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */
#define FLASH_CR_EOPIE (1 << 16) /* Bit 16: End-of-program interrupt enable */