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!arch/stm32h7: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32H7 Kconfig symbols were renamed from CONFIG_STM32H7_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_STM32H7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
2026-06-24 23:14:35 +08:00
committed by Xiang Xiao
parent 4f093cc1dd
commit c926b8af0c
286 changed files with 3865 additions and 9629 deletions
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Documentation/components/drivers/character/timers/capture.rst
+1 -1
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@@ -109,7 +109,7 @@ To enable the capture driver, enable the following configuration options:
* ``CONFIG_CAPTURE`` - Enable the capture driver framework
* ``CONFIG_CAPTURE_NOTIFY`` - Enable signal notification support for edge events
* ``CONFIG_FAKE_CAPTURE`` - Enable fake capture driver for testing (generates 10Hz signal with 50% duty cycle)
* ``CONFIG_STM32H7_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific)
* ``CONFIG_STM32_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific)
The ``CONFIG_CAPTURE`` option enables the lower-half driver and registers
the ``/dev/capture`` device.
Documentation/guides/renode.rst
+1 -1
View File
@@ -119,7 +119,7 @@ nucleo-h743zi
=============
Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable
it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``.
it with ``CONFIG_STM32_PWR_IGNORE_ACTVOSRDY=y``.
Renode script::
Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst
+1 -1
View File
@@ -721,7 +721,7 @@ After that check if your PC recognized the usb driver::
[27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk
[27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c
**OBS:** This example disable the macro CONFIG_STM32_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c
netnsh
------
Documentation/platforms/arm/stm32h7/index.rst
+1 -1
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@@ -114,7 +114,7 @@ The selection of the core for which the image is build is made using options:
- ``CONFIG_ARCH_CHIP_STM32H7_CORTEXM4`` - selects Cortex-M4 core
Support for the CM7 core is always enabled, support for the CM4 core is controlled
with the ``CONFIG_STM32H7_CORTEXM4_ENABLED`` option.
with the ``CONFIG_STM32_CORTEXM4_ENABLED`` option.
Interprocessor communication between cores is realized with the NuttX RPTUN
device based on the OpenAMP framework. ``HSEM`` is used for synchronization and
arch/arm/Kconfig
+1
View File
@@ -553,6 +553,7 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32H7
bool "STMicro STM32 H7"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_PROGMEM
arch/arm/include/stm32h7/chip.h
+6 -6
View File
@@ -91,10 +91,10 @@
/* Size SRAM */
#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || defined(CONFIG_STM32_STM32H7X3XX) || defined(CONFIG_STM32_STM32H7X5XX)
/* Memory */
# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX
# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */
# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */
@@ -152,7 +152,7 @@
# define STM32_NSAI (4) /* (4) SAI1-4*/
# define STM32_NCAN (2) /* (2) CAN1-2 */
# define STM32_NSDIO (2) /* (2) SDIO */
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
/* Memory */
# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */
@@ -206,7 +206,7 @@
# define STM32_NSAI (4) /* (4) SAI1-4*/
# define STM32_NCAN (2) /* (2) CAN1-2 */
# define STM32_NSDIO (2) /* (2) SDIO */
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
/* Memory */
# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
@@ -259,13 +259,13 @@
/* Diversification based on Family and package */
#if defined(CONFIG_STM32H7_HAVE_ETHERNET)
#if defined(CONFIG_STM32_HAVE_ETHERNET)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
#if defined(CONFIG_STM32H7_HAVE_FMC)
#if defined(CONFIG_STM32_HAVE_FMC)
# define STM32_NFMC 1 /* Have FMC memory controller */
#else
# define STM32_NFMC 0 /* No FMC memory controller */
arch/arm/include/stm32h7/irq.h
+5 -5
View File
@@ -69,19 +69,19 @@
* Included Files
****************************************************************************/
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include <arch/stm32h7/stm32h7x3xx_irq.h>
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include <arch/stm32h7/stm32h7x3xx_irq.h>
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include <arch/stm32h7/stm32h7x3xx_irq.h>
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
# include <arch/stm32h7/stm32h7x5xx_irq.h>
# else
# include <arch/stm32h7/stm32h7x5xx_cpu2_irq.h>
# endif
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include <arch/stm32h7/stm32h7x7xx_irq.h>
#else
# error "Unsupported STM32 H7 chip"
arch/arm/src/stm32h7/CMakeLists.txt
+36 -24
View File
@@ -35,7 +35,7 @@ list(
stm32_serial.c
stm32_uid.c)
if(CONFIG_STM32H7_PROGMEM)
if(CONFIG_STM32_PROGMEM)
list(APPEND SRCS stm32_flash.c)
endif()
@@ -43,7 +43,7 @@ if(CONFIG_ARCH_STM32H7_DUALCORE)
list(APPEND SRCS stm32_dualcore.c)
endif()
if(CONFIG_STM32H7_HSEM)
if(CONFIG_STM32_HSEM)
list(APPEND SRCS stm32_hsem.c)
endif()
@@ -57,7 +57,7 @@ else()
list(APPEND SRCS stm32_timerisr.c)
endif()
if(CONFIG_STM32H7_ONESHOT)
if(CONFIG_STM32_ONESHOT)
list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c)
endif()
@@ -73,47 +73,51 @@ if(CONFIG_ARMV7M_DTCM)
list(APPEND SRCS stm32_dtcm.c)
endif()
if(CONFIG_STM32H7_ADC)
if(CONFIG_STM32_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32H7_FDCAN)
if(CONFIG_STM32_FDCAN)
list(APPEND SRCS stm32_fdcan_sock.c)
endif()
if(CONFIG_STM32H7_BBSRAM)
if(CONFIG_STM32_BBSRAM)
list(APPEND SRCS stm32_bbsram.c)
endif()
if(CONFIG_STM32H7_DMA)
if(CONFIG_STM32_DMA)
list(APPEND SRCS stm32_dma.c)
endif()
if(CONFIG_STM32H7_FMC)
if(CONFIG_STM32_FMC)
list(APPEND SRCS stm32_fmc.c)
endif()
if(CONFIG_STM32H7_IWDG OR CONFIG_STM32H7_RTC_LSICLOCK)
if(CONFIG_STM32_RNG)
list(APPEND SRCS stm32_rng.c)
endif()
if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK)
list(APPEND SRCS stm32_lsi.c)
endif()
if(CONFIG_STM32H7_RTC_LSECLOCK)
if(CONFIG_STM32_RTC_LSECLOCK)
list(APPEND SRCS stm32_lse.c)
endif()
if(CONFIG_STM32H7_I2C)
if(CONFIG_STM32_I2C)
list(APPEND SRCS stm32_i2c.c)
endif()
if(CONFIG_STM32H7_PWR)
if(CONFIG_STM32_PWR)
list(APPEND SRCS stm32_pwr.c)
endif()
if(CONFIG_STM32H7_QSPI)
if(CONFIG_STM32_QSPI)
list(APPEND SRCS stm32_qspi.c)
endif()
if(CONFIG_STM32H7_RTC)
if(CONFIG_STM32_RTC)
list(APPEND SRCS stm32_rtc.c)
if(CONFIG_RTC_ALARM)
list(APPEND SRCS stm32_exti_alarm.c)
@@ -126,7 +130,7 @@ if(CONFIG_STM32H7_RTC)
endif()
endif()
if(CONFIG_STM32H7_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
@@ -134,7 +138,7 @@ if(CONFIG_SPI_SLAVE)
list(APPEND SRCS stm32_spi_slave.c)
endif()
if(CONFIG_STM32H7_SDMMC)
if(CONFIG_STM32_SDMMC)
list(APPEND SRCS stm32_sdmmc.c)
endif()
@@ -142,7 +146,7 @@ if(CONFIG_TIMER)
list(APPEND SRCS stm32_tim_lowerhalf.c)
endif()
if(CONFIG_STM32H7_TIMX_CAP)
if(CONFIG_STM32_TIMX_CAP)
list(APPEND SRCS stm32_capture.c)
endif()
@@ -150,7 +154,7 @@ if(CONFIG_CAPTURE)
list(APPEND SRCS stm32_capture_lowerhalf.c)
endif()
if(CONFIG_STM32H7_LTDC)
if(CONFIG_STM32_LTDC)
list(APPEND SRCS stm32_ltdc.c)
endif()
@@ -169,15 +173,15 @@ if(CONFIG_USBHOST)
endif()
endif()
if(CONFIG_STM32H7_TIM)
if(CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim.c)
endif()
if(CONFIG_STM32H7_LPTIM)
if(CONFIG_STM32_LPTIM)
list(APPEND SRCS stm32_lptim.c)
endif()
if(CONFIG_STM32H7_PWM)
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
@@ -185,7 +189,7 @@ if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32H7_ETHMAC)
if(CONFIG_STM32_ETHMAC)
list(APPEND SRCS stm32_ethernet.c)
endif()
@@ -204,12 +208,20 @@ if(CONFIG_PM)
endif()
endif()
if(CONFIG_STM32H7_IWDG)
if(CONFIG_STM32_IWDG)
list(APPEND SRCS stm32_iwdg.c)
endif()
if(CONFIG_STM32H7_WWDG)
if(CONFIG_STM32_WWDG)
list(APPEND SRCS stm32_wwdg.c)
endif()
if(CONFIG_STM32_CRYP AND CONFIG_STM32_HAVE_IP_CRYPTO_H7)
list(APPEND SRCS stm32_aes.c)
endif()
if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7)
list(APPEND SRCS stm32_crypto.c)
endif()
target_sources(arch PRIVATE ${SRCS})
arch/arm/src/stm32h7/Kconfig
+316 -6169
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h7/Make.defs
+31 -31
View File
@@ -27,7 +27,7 @@
include armv7-m/Make.defs
ifeq ($(CONFIG_STM32H7_PROGMEM),y)
ifeq ($(CONFIG_STM32_PROGMEM),y)
CHIP_CSRCS += stm32_flash.c
endif
@@ -35,7 +35,7 @@ ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y)
CHIP_CSRCS += stm32_dualcore.c
endif
ifeq ($(CONFIG_STM32H7_HSEM),y)
ifeq ($(CONFIG_STM32_HSEM),y)
CHIP_CSRCS += stm32_hsem.c
endif
@@ -55,7 +55,7 @@ else
CHIP_CSRCS += stm32_timerisr.c
endif
ifeq ($(CONFIG_STM32H7_ONESHOT),y)
ifeq ($(CONFIG_STM32_ONESHOT),y)
CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c
endif
@@ -71,51 +71,51 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y)
CHIP_CSRCS += stm32_dtcm.c
endif
ifeq ($(CONFIG_STM32H7_ADC),y)
ifeq ($(CONFIG_STM32_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32H7_FDCAN),y)
ifeq ($(CONFIG_STM32_FDCAN),y)
CHIP_CSRCS += stm32_fdcan_sock.c
endif
ifeq ($(CONFIG_STM32H7_RNG),y)
ifeq ($(CONFIG_STM32_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif
ifeq ($(CONFIG_STM32H7_BBSRAM),y)
ifeq ($(CONFIG_STM32_BBSRAM),y)
CHIP_CSRCS += stm32_bbsram.c
endif
ifeq ($(CONFIG_STM32H7_DMA),y)
ifeq ($(CONFIG_STM32_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32H7_FMC),y)
ifeq ($(CONFIG_STM32_FMC),y)
CHIP_CSRCS += stm32_fmc.c
endif
ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y)
ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y)
CHIP_CSRCS += stm32_lsi.c
endif
ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y)
ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y)
CHIP_CSRCS += stm32_lse.c
endif
ifeq ($(CONFIG_STM32H7_I2C),y)
ifeq ($(CONFIG_STM32_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32H7_PWR),y)
ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_pwr.c
endif
ifeq ($(CONFIG_STM32H7_QSPI),y)
ifeq ($(CONFIG_STM32_QSPI),y)
CHIP_CSRCS += stm32_qspi.c
endif
ifeq ($(CONFIG_STM32H7_RTC),y)
ifeq ($(CONFIG_STM32_RTC),y)
CHIP_CSRCS += stm32_rtc.c
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
@@ -128,7 +128,7 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_STM32H7_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
@@ -136,7 +136,7 @@ ifeq ($(CONFIG_SPI_SLAVE),y)
CHIP_CSRCS += stm32_spi_slave.c
endif
ifeq ($(CONFIG_STM32H7_SDMMC),y)
ifeq ($(CONFIG_STM32_SDMMC),y)
CHIP_CSRCS += stm32_sdmmc.c
endif
@@ -144,7 +144,7 @@ ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_STM32H7_TIMX_CAP),y)
ifeq ($(CONFIG_STM32_TIMX_CAP),y)
CHIP_CSRCS += stm32_capture.c
endif
@@ -152,7 +152,7 @@ ifeq ($(CONFIG_CAPTURE),y)
CHIP_CSRCS += stm32_capture_lowerhalf.c
endif
ifeq ($(CONFIG_STM32H7_LTDC),y)
ifeq ($(CONFIG_STM32_LTDC),y)
CHIP_CSRCS += stm32_ltdc.c
endif
@@ -171,23 +171,23 @@ endif
endif
endif
ifeq ($(CONFIG_STM32H7_TIM),y)
ifeq ($(CONFIG_STM32_TIM),y)
CHIP_CSRCS += stm32_tim.c
endif
ifeq ($(CONFIG_STM32H7_LPTIM),y)
ifeq ($(CONFIG_STM32_LPTIM),y)
CHIP_CSRCS += stm32_lptim.c
endif
ifeq ($(CONFIG_STM32H7_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32H7_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
ifeq ($(CONFIG_STM32H7_ETHMAC),y)
ifeq ($(CONFIG_STM32_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif
@@ -206,22 +206,22 @@ CHIP_CSRCS += stm32_pminitialize.c
endif
endif
ifeq ($(CONFIG_STM32H7_IWDG),y)
ifeq ($(CONFIG_STM32_IWDG),y)
CHIP_CSRCS += stm32_iwdg.c
endif
ifeq ($(CONFIG_STM32H7_WWDG),y)
ifeq ($(CONFIG_STM32_WWDG),y)
CHIP_CSRCS += stm32_wwdg.c
endif
#ifeq ($(CONFIG_STM32H7_HASH),y)
#CHIP_CSRCS += stm32_hash.c
#endif
ifeq ($(CONFIG_STM32H7_CRYP),y)
ifeq ($(CONFIG_STM32_CRYP),y)
ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y)
CHIP_CSRCS += stm32_aes.c
endif
endif
ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y)
ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y)
CHIP_CSRCS += stm32_crypto.c
endif
endif
arch/arm/src/stm32h7/hardware/stm32_dmamux.h
+5 -5
View File
@@ -203,15 +203,15 @@
/* Import DMAMUX map */
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_dmamux.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_dmamux.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_dmamux.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_dmamux.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_dmamux.h"
#else
# error "Unsupported STM32 H7 sub family"
arch/arm/src/stm32h7/hardware/stm32_ethernet.h
+6 -6
View File
@@ -33,11 +33,11 @@
* families
*/
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -680,5 +680,5 @@ struct eth_desc_s
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */
arch/arm/src/stm32h7/hardware/stm32_exti.h
+6 -6
View File
@@ -35,11 +35,11 @@
* families
*/
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -243,5 +243,5 @@
#define EXTI_EVENT_ETHWKUP 86 /* Ethernet wakeup */
#define EXTI_EVENT_HSECSS 87 /* HSECSS interrupt */
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */
arch/arm/src/stm32h7/hardware/stm32_flash.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_flash.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_flash.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7b3xx_flash.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_flash.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_flash.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_gpio.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_gpio.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_gpio.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_gpio.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_gpio.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_gpio.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_i2c.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_i2c.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_i2c.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_i2c.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_i2c.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_i2c.h"
#else
# error "Unsupported STM32 H7 sub family"
arch/arm/src/stm32h7/hardware/stm32_memorymap.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_memorymap.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_memorymap.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_memorymap.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_memorymap.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_memorymap.h"
#else
# error "Unsupported STM32 H7 memory map"
arch/arm/src/stm32h7/hardware/stm32_pinmap.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_pinmap.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_pinmap.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_pinmap.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_pinmap.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_pinmap.h"
#else
# error "Unsupported STM32 H7 Pin map"
arch/arm/src/stm32h7/hardware/stm32_pwr.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_pwr.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_pwr.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_pwr.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_pwr.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_pwr.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_rcc.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_rcc.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_rcc.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_rcc.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_rcc.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_rcc.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_sdmmc.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "stm32h7x3xx_sdmmc.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "stm32h7x3xx_sdmmc.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "stm32h7x3xx_sdmmc.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "stm32h7x3xx_sdmmc.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "stm32h7x3xx_sdmmc.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_spi.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_spi.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_spi.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_spi.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_spi.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_spi.h"
#else
# error "Unsupported STM32 H7 sub family"
arch/arm/src/stm32h7/hardware/stm32_syscfg.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_syscfg.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_syscfg.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_syscfg.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_syscfg.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_syscfg.h"
#else
# error "Unsupported STM32 H7 part"
arch/arm/src/stm32h7/hardware/stm32_uart.h
+5 -5
View File
@@ -30,15 +30,15 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX)
#if defined(CONFIG_STM32_STM32H7X0XX)
# include "hardware/stm32h7x3xx_uart.h"
#elif defined(CONFIG_STM32H7_STM32H7X3XX)
#elif defined(CONFIG_STM32_STM32H7X3XX)
# include "hardware/stm32h7x3xx_uart.h"
#elif defined(CONFIG_STM32H7_STM32H7B3XX)
#elif defined(CONFIG_STM32_STM32H7B3XX)
# include "hardware/stm32h7x3xx_uart.h"
#elif defined(CONFIG_STM32H7_STM32H7X5XX)
#elif defined(CONFIG_STM32_STM32H7X5XX)
# include "hardware/stm32h7x3xx_uart.h"
#elif defined(CONFIG_STM32H7_STM32H7X7XX)
#elif defined(CONFIG_STM32_STM32H7X7XX)
# include "hardware/stm32h7x3xx_uart.h"
#else
# error "Unsupported STM32 H7 memory map"
arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h
+8 -8
View File
@@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include <arch/stm32h7/chip.h>
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -120,7 +120,7 @@
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
#endif
#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF))
#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF))
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
@@ -133,7 +133,7 @@
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
#endif
#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG))
#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG))
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
@@ -390,5 +390,5 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */
arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
+1 -1
View File
@@ -65,7 +65,7 @@
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
# define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */
# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX
# define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */
# else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */
# define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
+6 -6
View File
@@ -31,11 +31,11 @@
#include "stm32_gpio.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -1538,5 +1538,5 @@
#define GPIO_UART8_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN1)
#define GPIO_UART8_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8)
#endif /* CONFIG_STM32H7_STM32H7X0XX CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X0XX CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
+2 -2
View File
@@ -131,10 +131,10 @@
#define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */
#define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */
#ifndef CONFIG_STM32H7_HAVE_SMPS
#ifndef CONFIG_STM32_HAVE_SMPS
# define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */
#endif
#ifdef CONFIG_STM32H7_HAVE_SMPS
#ifdef CONFIG_STM32_HAVE_SMPS
# define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */
# define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */
# define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */
arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
+2 -2
View File
@@ -827,10 +827,10 @@
/* RCC Global Control register */
#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */
#ifdef CONFIG_STM32H7_HAVE_CM4
#ifdef CONFIG_STM32_HAVE_CM4
# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */
#endif
#ifdef CONFIG_STM32H7_HAVE_CM4
#ifdef CONFIG_STM32_HAVE_CM4
# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */
# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */
#endif
arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
+6 -6
View File
@@ -29,11 +29,11 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -466,5 +466,5 @@
/* TODO: SPI/I2S configuration register */
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */
arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
+3 -3
View File
@@ -56,7 +56,7 @@
#define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2))
#define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */
#ifdef CONFIG_STM32H7_HAVE_CM4
#ifdef CONFIG_STM32_HAVE_CM4
# define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */
#endif
#define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */
@@ -92,7 +92,7 @@
#define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET)
#define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET)
#ifdef CONFIG_STM32H7_HAVE_CM4
#ifdef CONFIG_STM32_HAVE_CM4
# define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET)
#endif
#define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET)
@@ -220,7 +220,7 @@
/* User register 1 */
#ifdef CONFIG_STM32H7_HAVE_CM4
#ifdef CONFIG_STM32_HAVE_CM4
# define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */
# define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */
#endif
arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
+6 -6
View File
@@ -31,11 +31,11 @@
#include "chip.h"
#include "hardware/stm32_memorymap.h"
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Pre-processor Definitions
@@ -415,5 +415,5 @@
# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */
arch/arm/src/stm32h7/stm32_adc.c
+38 -38
View File
@@ -77,8 +77,8 @@
/* Some ADC peripheral must be enabled */
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \
defined(CONFIG_STM32H7_ADC3)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
defined(CONFIG_STM32_ADC3)
/****************************************************************************
* Pre-processor Definitions
@@ -92,9 +92,9 @@
/* ADC Channels/DMA *********************************************************/
#ifdef ADC_HAVE_DMA
# if !defined(CONFIG_STM32H7_DMA1) && !defined(CONFIG_STM32H7_DMA2)
# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2)
# /* REVISIT: check accordingly to which one is configured in board.h */
# error "STM32H7 ADC DMA support requires CONFIG_STM32H7_DMA1 or CONFIG_STM32H7_DMA2"
# error "STM32H7 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2"
# endif
#endif
@@ -191,7 +191,7 @@ struct stm32_dev_s
/* List of selected ADC channels to sample */
uint8_t chanlist[CONFIG_STM32H7_ADC_MAX_SAMPLES];
uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES];
};
/****************************************************************************
@@ -254,10 +254,10 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain,
/* ADC Interrupt Handler */
static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval);
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
static int adc12_interrupt(int irq, void *context, void *arg);
#endif
#if defined(CONFIG_STM32H7_ADC3)
#if defined(CONFIG_STM32_ADC3)
static int adc3_interrupt(int irq, void *context, void *arg);
#endif
@@ -289,11 +289,11 @@ static const struct adc_ops_s g_adcops =
/* ADC1 state */
#ifdef CONFIG_STM32H7_ADC1
#ifdef CONFIG_STM32_ADC1
#ifdef ADC1_HAVE_DMA
static uint16_t g_adc1_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES *
CONFIG_STM32H7_ADC1_DMA_BATCH];
static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC1_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv1 =
@@ -305,19 +305,19 @@ static struct stm32_dev_s g_adcpriv1 =
.mbase = STM32_ADC1_BASE,
.initialized = false,
#ifdef ADC1_HAVE_TIMER
.trigger = CONFIG_STM32H7_ADC1_TIMTRIG,
.trigger = CONFIG_STM32_ADC1_TIMTRIG,
.tbase = ADC1_TIMER_BASE,
.trcc_enr = ADC1_TIMER_RCC_ENR,
.trcc_en = ADC1_TIMER_RCC_EN,
.extsel = ADC1_EXTSEL_VALUE,
.pclck = ADC1_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
#endif
#ifdef ADC1_HAVE_DMA
.dmachan = ADC1_DMA_CHAN,
.hasdma = true,
.r_dmabuffer = g_adc1_dmabuffer,
.dmabatch = CONFIG_STM32H7_ADC1_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC1_DMA_BATCH,
#endif
#ifdef ADC1_HAVE_DFSDM
.hasdfsdm = true,
@@ -339,11 +339,11 @@ static struct adc_dev_s g_adcdev1 =
/* ADC2 state */
#ifdef CONFIG_STM32H7_ADC2
#ifdef CONFIG_STM32_ADC2
#ifdef ADC2_HAVE_DMA
static uint16_t g_adc2_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES *
CONFIG_STM32H7_ADC2_DMA_BATCH];
static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC2_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv2 =
@@ -355,19 +355,19 @@ static struct stm32_dev_s g_adcpriv2 =
.mbase = STM32_ADC1_BASE,
.initialized = false,
#ifdef ADC2_HAVE_TIMER
.trigger = CONFIG_STM32H7_ADC2_TIMTRIG,
.trigger = CONFIG_STM32_ADC2_TIMTRIG,
.tbase = ADC2_TIMER_BASE,
.trcc_enr = ADC2_TIMER_RCC_ENR,
.trcc_en = ADC2_TIMER_RCC_EN,
.extsel = ADC2_EXTSEL_VALUE,
.pclck = ADC2_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
#endif
#ifdef ADC2_HAVE_DMA
.dmachan = ADC2_DMA_CHAN,
.hasdma = true,
.r_dmabuffer = g_adc2_dmabuffer,
.dmabatch = CONFIG_STM32H7_ADC2_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC2_DMA_BATCH,
#endif
#ifdef ADC2_HAVE_DFSDM
.hasdfsdm = true,
@@ -389,11 +389,11 @@ static struct adc_dev_s g_adcdev2 =
/* ADC3 state */
#ifdef CONFIG_STM32H7_ADC3
#ifdef CONFIG_STM32_ADC3
#ifdef ADC3_HAVE_DMA
static uint16_t g_adc3_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES *
CONFIG_STM32H7_ADC3_DMA_BATCH];
static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC3_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv3 =
@@ -405,19 +405,19 @@ static struct stm32_dev_s g_adcpriv3 =
.mbase = STM32_ADC3_BASE,
.initialized = false,
#ifdef ADC3_HAVE_TIMER
.trigger = CONFIG_STM32H7_ADC3_TIMTRIG,
.trigger = CONFIG_STM32_ADC3_TIMTRIG,
.tbase = ADC3_TIMER_BASE,
.trcc_enr = ADC3_TIMER_RCC_ENR,
.trcc_en = ADC3_TIMER_RCC_EN,
.extsel = ADC3_EXTSEL_VALUE,
.pclck = ADC3_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY,
#endif
#ifdef ADC3_HAVE_DMA
.dmachan = ADC3_DMA_CHAN,
.hasdma = true,
.r_dmabuffer = g_adc3_dmabuffer,
.dmabatch = CONFIG_STM32H7_ADC3_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC3_DMA_BATCH,
#endif
#ifdef ADC3_HAVE_DFSDM
.hasdfsdm = true,
@@ -1381,7 +1381,7 @@ static int adc_setup(struct adc_dev_s *dev)
* ADC1 and ADC2 are enabled.)
*/
#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2)
#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)
if ((dev == &g_adcdev1 &&
!((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) ||
(dev == &g_adcdev2 &&
@@ -1880,7 +1880,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch)
priv->rnchannels = 1;
}
DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES);
DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES);
bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST,
ADC_SQR4_SQ_OFFSET);
@@ -2163,13 +2163,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
*
****************************************************************************/
#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
static int adc12_interrupt(int irq, void *context, void *arg)
{
uint32_t regval;
uint32_t pending;
#ifdef CONFIG_STM32H7_ADC1
#ifdef CONFIG_STM32_ADC1
regval = getreg32(STM32_ADC1_ISR);
pending = regval & ADC_INT_MASK;
if (pending != 0)
@@ -2178,7 +2178,7 @@ static int adc12_interrupt(int irq, void *context, void *arg)
}
#endif
#ifdef CONFIG_STM32H7_ADC2
#ifdef CONFIG_STM32_ADC2
regval = getreg32(STM32_ADC2_ISR);
pending = regval & ADC_INT_MASK;
if (pending != 0)
@@ -2203,7 +2203,7 @@ static int adc12_interrupt(int irq, void *context, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32H7_ADC3
#ifdef CONFIG_STM32_ADC3
static int adc3_interrupt(int irq, void *context, void *arg)
{
uint32_t regval;
@@ -2312,19 +2312,19 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
switch (intf)
{
#ifdef CONFIG_STM32H7_ADC1
#ifdef CONFIG_STM32_ADC1
case 1:
ainfo("ADC1 selected\n");
dev = &g_adcdev1;
break;
#endif
#ifdef CONFIG_STM32H7_ADC2
#ifdef CONFIG_STM32_ADC2
case 2:
ainfo("ADC2 selected\n");
dev = &g_adcdev2;
break;
#endif
#ifdef CONFIG_STM32H7_ADC3
#ifdef CONFIG_STM32_ADC3
case 3:
ainfo("ADC3 selected\n");
dev = &g_adcdev3;
@@ -2340,10 +2340,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
priv = (struct stm32_dev_s *)dev->ad_priv;
priv->cb = NULL;
DEBUGASSERT(cchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES);
if (cchannels > CONFIG_STM32H7_ADC_MAX_SAMPLES)
DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES);
if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES)
{
cchannels = CONFIG_STM32H7_ADC_MAX_SAMPLES;
cchannels = CONFIG_STM32_ADC_MAX_SAMPLES;
}
priv->cchannels = cchannels;
@@ -2360,5 +2360,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
return dev;
}
#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
#endif /* CONFIG_ADC */
arch/arm/src/stm32h7/stm32_adc.h
+238 -238
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h7/stm32_aes.h
+1 -1
View File
@@ -37,7 +37,7 @@
* variants include CRYP
*/
#ifdef CONFIG_STM32H7_HAVE_CRYP
#ifdef CONFIG_STM32_HAVE_CRYP
# include "hardware/stm32h7xxxx_cryp.h"
#else
# error "Unknown chip for AES"
arch/arm/src/stm32h7/stm32_allocateheap.c
+6 -6
View File
@@ -57,7 +57,7 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
!defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
!defined(CONFIG_STM32_CORTEXM4_ENABLED)
/* Configuration for M7 core when M4 core support disabled */
@@ -84,7 +84,7 @@
* - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system
* heap. Note that DTCM has a number of limitations, for example DMA
* transfers to/from DTCM are limited.
* Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap.
* Define CONFIG_STM32_DTCMEXCLUDE to exclude the DTCM from heap.
* +1 to CONFIG_MM_REGIONS if you want to use DTCM.
*
* - External SDRAM can be connected to the FMC peripheral. Initialization
@@ -117,7 +117,7 @@
# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE)
#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
defined(CONFIG_STM32_CORTEXM4_ENABLED)
/* Configuration for M7 core when M4 core support enabled */
@@ -139,7 +139,7 @@
#endif
#undef HAVE_SRAM4
#if !defined(CONFIG_STM32H7_SRAM4EXCLUDE)
#if !defined(CONFIG_STM32_SRAM4EXCLUDE)
# define HAVE_SRAM4 1
# define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE))
@@ -158,7 +158,7 @@
/* DTCM to be excluded from the main heap. */
#ifdef CONFIG_STM32H7_DTCMEXCLUDE
#ifdef CONFIG_STM32_DTCMEXCLUDE
# undef HAVE_DTCM
#endif
@@ -410,7 +410,7 @@ void arm_addregion(void)
}
#endif
#ifdef CONFIG_STM32H7_FMC
#ifdef CONFIG_STM32_FMC
stm32_fmc_init();
#endif
arch/arm/src/stm32h7/stm32_bbsram.c
+7 -7
View File
@@ -50,14 +50,14 @@
#include "mpu.h"
#include "stm32_pwr.h"
#ifdef CONFIG_STM32H7_BBSRAM
#ifdef CONFIG_STM32_BBSRAM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32H7_BKPSRAM)
#error Driver Requires CONFIG_STM32H7_BKPSRAM to be enabled
#if !defined(CONFIG_STM32_BKPSRAM)
#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled
#endif
#define MAX_OPENCNT (255) /* Limit of uint8_t */
@@ -168,7 +168,7 @@ static const struct file_operations g_stm32_bbsram_fops =
#endif
};
static struct stm32_bbsram_s g_bbsram[CONFIG_STM32H7_BBSRAM_FILES];
static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES];
/****************************************************************************
* Private Functions
@@ -690,7 +690,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
avail = STM32_BBSRAM_SIZE;
for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0);
for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0);
i++)
{
/* Validate the actual allocations against what is in the BBSRAM */
@@ -855,7 +855,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
*
****************************************************************************/
#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP)
#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)
{
struct bbsramfh_s *bbf;
@@ -873,7 +873,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)
{
once = true;
DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32H7_BBSRAM_FILES);
DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES);
bbf = g_bbsram[fileno].bbf;
arch/arm/src/stm32h7/stm32_bbsram.h
+5 -5
View File
@@ -48,8 +48,8 @@
#define STM32_BBSRAM_SIZE 4096
#if !defined(CONFIG_STM32H7_BBSRAM_FILES)
# define CONFIG_STM32H7_BBSRAM_FILES 4
#if !defined(CONFIG_STM32_BBSRAM_FILES)
# define CONFIG_STM32_BBSRAM_FILES 4
#endif
/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique
@@ -107,8 +107,8 @@ extern "C"
* the last entry should be 0
* A size of -1 will use all the remaining spaces
*
* If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES
* CONFIG_STM32H7_BBSRAM_FILES will be returned.
* If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES
* CONFIG_STM32_BBSRAM_FILES will be returned.
*
* Returned Value:
* Number of files created on success; Negated errno on failure.
@@ -137,7 +137,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes);
*
*****************************************************************************/
#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP)
#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);
#endif
arch/arm/src/stm32h7/stm32_capture.c
+80 -80
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h7/stm32_capture_lowerhalf.c
+48 -48
View File
@@ -125,123 +125,123 @@ static const struct cap_ops_s g_cap_ops =
.getfreq = stm32_getfreq,
};
#ifdef CONFIG_STM32H7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
static struct stm32_lowerhalf_s g_cap1_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM1_RES,
.channel = CONFIG_STM32H7_TIM1_CHANNEL,
.clock = CONFIG_STM32H7_TIM1_CLOCK,
.channel = CONFIG_STM32_TIM1_CHANNEL,
.clock = CONFIG_STM32_TIM1_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
static struct stm32_lowerhalf_s g_cap2_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM2_RES,
.channel = CONFIG_STM32H7_TIM2_CHANNEL,
.clock = CONFIG_STM32H7_TIM2_CLOCK,
.channel = CONFIG_STM32_TIM2_CHANNEL,
.clock = CONFIG_STM32_TIM2_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
static struct stm32_lowerhalf_s g_cap3_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM3_RES,
.channel = CONFIG_STM32H7_TIM3_CHANNEL,
.clock = CONFIG_STM32H7_TIM3_CLOCK,
.channel = CONFIG_STM32_TIM3_CHANNEL,
.clock = CONFIG_STM32_TIM3_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
static struct stm32_lowerhalf_s g_cap4_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM4_RES,
.channel = CONFIG_STM32H7_TIM4_CHANNEL,
.clock = CONFIG_STM32H7_TIM4_CLOCK,
.channel = CONFIG_STM32_TIM4_CHANNEL,
.clock = CONFIG_STM32_TIM4_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
static struct stm32_lowerhalf_s g_cap5_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM5_RES,
.channel = CONFIG_STM32H7_TIM5_CHANNEL,
.clock = CONFIG_STM32H7_TIM5_CLOCK,
.channel = CONFIG_STM32_TIM5_CHANNEL,
.clock = CONFIG_STM32_TIM5_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
static struct stm32_lowerhalf_s g_cap8_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM8_RES,
.channel = CONFIG_STM32H7_TIM8_CHANNEL,
.clock = CONFIG_STM32H7_TIM8_CLOCK,
.channel = CONFIG_STM32_TIM8_CHANNEL,
.clock = CONFIG_STM32_TIM8_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
static struct stm32_lowerhalf_s g_cap12_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM12_RES,
.channel = CONFIG_STM32H7_TIM12_CHANNEL,
.clock = CONFIG_STM32H7_TIM12_CLOCK,
.channel = CONFIG_STM32_TIM12_CHANNEL,
.clock = CONFIG_STM32_TIM12_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
static struct stm32_lowerhalf_s g_cap13_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM13_RES,
.channel = CONFIG_STM32H7_TIM13_CHANNEL,
.clock = CONFIG_STM32H7_TIM13_CLOCK,
.channel = CONFIG_STM32_TIM13_CHANNEL,
.clock = CONFIG_STM32_TIM13_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
static struct stm32_lowerhalf_s g_cap14_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM14_RES,
.channel = CONFIG_STM32H7_TIM14_CHANNEL,
.clock = CONFIG_STM32H7_TIM14_CLOCK,
.channel = CONFIG_STM32_TIM14_CHANNEL,
.clock = CONFIG_STM32_TIM14_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM15_CAP
#ifdef CONFIG_STM32_TIM15_CAP
static struct stm32_lowerhalf_s g_cap15_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM15_RES,
.channel = CONFIG_STM32H7_TIM15_CHANNEL,
.clock = CONFIG_STM32H7_TIM15_CLOCK,
.channel = CONFIG_STM32_TIM15_CHANNEL,
.clock = CONFIG_STM32_TIM15_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM16_CAP
#ifdef CONFIG_STM32_TIM16_CAP
static struct stm32_lowerhalf_s g_cap16_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM16_RES,
.channel = CONFIG_STM32H7_TIM16_CHANNEL,
.clock = CONFIG_STM32H7_TIM16_CLOCK,
.channel = CONFIG_STM32_TIM16_CHANNEL,
.clock = CONFIG_STM32_TIM16_CLOCK,
};
#endif
#ifdef CONFIG_STM32H7_TIM17_CAP
#ifdef CONFIG_STM32_TIM17_CAP
static struct stm32_lowerhalf_s g_cap17_lowerhalf =
{
.ops = &g_cap_ops,
.resolution = STM32_TIM17_RES,
.channel = CONFIG_STM32H7_TIM17_CHANNEL,
.clock = CONFIG_STM32H7_TIM17_CLOCK,
.channel = CONFIG_STM32_TIM17_CHANNEL,
.clock = CONFIG_STM32_TIM17_CLOCK,
};
#endif
@@ -504,62 +504,62 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer)
switch (timer)
{
#ifdef CONFIG_STM32H7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
case 1:
lower = &g_cap1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
case 2:
lower = &g_cap2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
case 3:
lower = &g_cap3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
case 4:
lower = &g_cap4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
case 5:
lower = &g_cap5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
case 8:
lower = &g_cap8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
case 12:
lower = &g_cap12_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
case 13:
lower = &g_cap13_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
case 14:
lower = &g_cap14_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM15_CAP
#ifdef CONFIG_STM32_TIM15_CAP
case 15:
lower = &g_cap15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM16_CAP
#ifdef CONFIG_STM32_TIM16_CAP
case 16:
lower = &g_cap16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H7_TIM17_CAP
#ifdef CONFIG_STM32_TIM17_CAP
case 17:
lower = &g_cap17_lowerhalf;
break;
arch/arm/src/stm32h7/stm32_dma.c
+44 -44
View File
@@ -51,22 +51,22 @@
#define DMAMUX_NUM 2
#define DMA_CONTROLLERS 4
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
# define MDMA_NCHAN 16
#else
# define MDMA_NCHAN 0
#endif
#ifdef CONFIG_STM32H7_DMA1
#ifdef CONFIG_STM32_DMA1
# define DMA1_NSTREAMS 8
#else
# define DMA1_NSTREAMS 0
#endif
#ifdef CONFIG_STM32H7_DMA2
#ifdef CONFIG_STM32_DMA2
# define DMA2_NSTREAMS 8
#else
# define DMA2_NSTREAMS 0
#endif
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
# define BDMA_NCHAN 8
#else
# define BDMA_NCHAN 0
@@ -185,7 +185,7 @@ struct stm32_dma_ops_s
* Private Functions
****************************************************************************/
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
static void stm32_mdma_disable(DMA_CHANNEL dmachan);
static int stm32_mdma_interrupt(int irq, void *context, void *arg);
static void stm32_mdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg);
@@ -193,7 +193,7 @@ static void stm32_mdma_free(DMA_HANDLE handle);
static void stm32_mdma_start(DMA_HANDLE handle, dma_callback_t callback,
void *arg, bool half);
static size_t stm32_mdma_residual(DMA_HANDLE handle);
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_mdma_capable(stm32_dmacfg_t *cfg);
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -201,7 +201,7 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg);
#endif
#endif
#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2)
#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
static void stm32_sdma_disable(DMA_CHANNEL dmachan);
static int stm32_sdma_interrupt(int irq, void *context, void *arg);
static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg);
@@ -209,7 +209,7 @@ static void stm32_sdma_free(DMA_HANDLE handle);
static void stm32_sdma_start(DMA_HANDLE handle, dma_callback_t callback,
void *arg, bool half);
static size_t stm32_sdma_residual(DMA_HANDLE handle);
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_sdma_capable(stm32_dmacfg_t *cfg);
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -217,7 +217,7 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg);
#endif
#endif
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
static void stm32_bdma_disable(DMA_CHANNEL dmachan);
static int stm32_bdma_interrupt(int irq, void *context, void *arg);
static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg);
@@ -225,7 +225,7 @@ static void stm32_bdma_free(DMA_HANDLE handle);
static void stm32_bdma_start(DMA_HANDLE handle, dma_callback_t callback,
void *arg, bool half);
static size_t stm32_bdma_residual(DMA_HANDLE handle);
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_bdma_capable(stm32_dmacfg_t *cfg);
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -265,7 +265,7 @@ static inline void dmachan_modifyreg32(DMA_CHANNEL dmachan,
struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
{
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
/* 0 - MDMA */
{
@@ -275,7 +275,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
.dma_free = stm32_mdma_free,
.dma_start = stm32_mdma_start,
.dma_residual = stm32_mdma_residual,
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
.dma_capable = stm32_mdma_capable,
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -288,7 +288,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
},
#endif
#ifdef CONFIG_STM32H7_DMA1
#ifdef CONFIG_STM32_DMA1
/* 1 - DMA1 */
{
@@ -298,7 +298,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
.dma_free = stm32_sdma_free,
.dma_start = stm32_sdma_start,
.dma_residual = stm32_sdma_residual,
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
.dma_capable = stm32_sdma_capable,
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -311,7 +311,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
},
#endif
#ifdef CONFIG_STM32H7_DMA2
#ifdef CONFIG_STM32_DMA2
/* 2 - DMA2 */
{
@@ -321,7 +321,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
.dma_free = stm32_sdma_free,
.dma_start = stm32_sdma_start,
.dma_residual = stm32_sdma_residual,
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
.dma_capable = stm32_sdma_capable,
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -334,7 +334,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
},
#endif
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
/* 3 - BDMA */
{
@@ -344,7 +344,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
.dma_free = stm32_bdma_free,
.dma_start = stm32_bdma_start,
.dma_residual = stm32_bdma_residual,
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
.dma_capable = stm32_bdma_capable,
#endif
#ifdef CONFIG_DEBUG_DMA_INFO
@@ -427,7 +427,7 @@ struct stm32_dma_s g_dma[DMA_NCHANNELS] =
static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
{
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
/* MDMA */
{
@@ -559,7 +559,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
},
#endif
#ifdef CONFIG_STM32H7_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA1 */
{
@@ -627,7 +627,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
},
#endif
#ifdef CONFIG_STM32H7_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA2 */
{
@@ -695,7 +695,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
},
#endif
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
/* BDMA */
{
@@ -920,7 +920,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first,
* Master DMA functions
****************************************************************************/
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
/****************************************************************************
* Name: stm32_mdma_disable
@@ -1028,7 +1028,7 @@ static size_t stm32_mdma_residual(DMA_HANDLE handle)
* Name: stm32_mdma_capable
****************************************************************************/
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_mdma_capable(stm32_dmacfg_t *cfg)
{
uint32_t transfer_size;
@@ -1084,13 +1084,13 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg)
}
#endif
#endif /* CONFIG_STM32H7_MDMA */
#endif /* CONFIG_STM32_MDMA */
/****************************************************************************
* Standard DMA functions
****************************************************************************/
#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2)
#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
/****************************************************************************
* Name: stm32_sdma_disable
@@ -1158,7 +1158,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg)
/* Get the stream and the controller that generated the interrupt */
#ifdef CONFIG_STM32H7_DMA1
#ifdef CONFIG_STM32_DMA1
if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6)
{
stream = irq - STM32_IRQ_DMA1S0;
@@ -1171,7 +1171,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg)
}
else
#endif
#ifdef CONFIG_STM32H7_DMA2
#ifdef CONFIG_STM32_DMA2
if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4)
{
stream = irq - STM32_IRQ_DMA2S0;
@@ -1258,7 +1258,7 @@ static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg)
"scr: %08" PRIx32 "\n",
cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1);
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
DEBUGASSERT(stm32_sdma_capable(cfg));
#endif
@@ -1530,7 +1530,7 @@ static size_t stm32_sdma_residual(DMA_HANDLE handle)
* Name: stm32_sdma_capable
****************************************************************************/
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_sdma_capable(stm32_dmacfg_t *cfg)
{
uint32_t transfer_size;
@@ -1604,7 +1604,7 @@ static bool stm32_sdma_capable(stm32_dmacfg_t *cfg)
dmainfo("stm32_dmacapable: dcache unaligned "
"maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n",
cfg->maddr, mend);
#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED)
return false;
#endif
}
@@ -1766,13 +1766,13 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg)
}
#endif
#endif /* CONFIG_STM32H7_DMA1 || CONFIG_STM32H7_DMA2 */
#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */
/****************************************************************************
* Basic DMA functions
****************************************************************************/
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
/****************************************************************************
* Name: stm32_bdma_channel_disable
@@ -1898,7 +1898,7 @@ static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg)
"scr: %08" PRIx32 "\n",
cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1);
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
DEBUGASSERT(stm32_bdma_capable(cfg));
#endif
@@ -2106,7 +2106,7 @@ static size_t stm32_bdma_residual(DMA_HANDLE handle)
* Name: stm32_bdma_capable
****************************************************************************/
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
static bool stm32_bdma_capable(stm32_dmacfg_t *cfg)
{
uint32_t transfer_size;
@@ -2177,7 +2177,7 @@ static bool stm32_bdma_capable(stm32_dmacfg_t *cfg)
dmainfo("stm32_dmacapable: dcache unaligned "
"maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n",
cfg->maddr, mend);
#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED)
return false;
#endif
}
@@ -2253,7 +2253,7 @@ static void stm32_bdma_dump(DMA_HANDLE handle, const char *msg)
}
#endif
#endif /* CONFIG_STM32H7_BDMA */
#endif /* CONFIG_STM32_BDMA */
/****************************************************************************
* Name: stm32_dmamux_dump
@@ -2341,30 +2341,30 @@ void weak_function arm_dma_initialize(void)
#ifdef CONFIG_ARCH_IRQPRIO
switch (controller)
{
#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2)
#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
case DMA1:
case DMA2:
{
up_prioritize_irq(dmachan->irq, CONFIG_DMA_PRI);
break;
}
#endif /* CONFIG_STM32H7_DMA1 && CONFIG_STM32H7_DMA2 */
#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_DMA2 */
#ifdef CONFIG_STM32H7_MDMA
#ifdef CONFIG_STM32_MDMA
case MDMA:
{
up_prioritize_irq(dmachan->irq, CONFIG_MDMA_PRI);
break;
}
#endif /* CONFIG_STM32H7_MDMA */
#endif /* CONFIG_STM32_MDMA */
#ifdef CONFIG_STM32H7_BDMA
#ifdef CONFIG_STM32_BDMA
case BDMA:
{
up_prioritize_irq(dmachan->irq, CONFIG_BDMA_PRI);
break;
}
#endif /* CONFIG_STM32H7_BDMA */
#endif /* CONFIG_STM32_BDMA */
default:
{
@@ -2666,7 +2666,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg)
{
DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
arch/arm/src/stm32h7/stm32_dma.h
+1 -1
View File
@@ -194,7 +194,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
* Name: stm32_dmacapable
****************************************************************************/
#ifdef CONFIG_STM32H7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg);
#else
# define stm32_dmacapable(handle, cfg) (true)
arch/arm/src/stm32h7/stm32_dtcm.h
+1 -1
View File
@@ -50,7 +50,7 @@
* heap.
*/
#ifndef CONFIG_STM32H7_DTCMEXCLUDE
#ifndef CONFIG_STM32_DTCMEXCLUDE
# undef HAVE_DTCM_HEAP
#endif
arch/arm/src/stm32h7/stm32_dualcore.c
+4 -4
View File
@@ -52,7 +52,7 @@
****************************************************************************/
#if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \
defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \
defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4)
/****************************************************************************
@@ -105,7 +105,7 @@ static void stm32_cpu2sem_wait(void)
#endif
#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
defined(CONFIG_STM32_CORTEXM4_ENABLED)
/****************************************************************************
* Name: stm32_cm7_take_sem
@@ -134,7 +134,7 @@ static void stm32_cpu2sem_take(void)
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
defined(CONFIG_STM32_CORTEXM4_ENABLED)
/****************************************************************************
* Name: stm32_start_cm4
@@ -162,7 +162,7 @@ void stm32_start_cm4(void)
stm32_cpu2sem_take();
}
#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4
#ifdef CONFIG_STM32_CORTEXM7_BOOTM4
else
{
/* CM4 not started at boot - force CM4 boot */
arch/arm/src/stm32h7/stm32_dualcore.h
+1 -1
View File
@@ -51,7 +51,7 @@ extern "C"
#endif
#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
defined(CONFIG_STM32_CORTEXM4_ENABLED)
/****************************************************************************
* Name: stm32_start_cm4
arch/arm/src/stm32h7/stm32_ethernet.c
+137 -137
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h7/stm32_ethernet.h
+2 -2
View File
@@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf);
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_STM32H7_PHYINIT is defined in the configuration
* the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration
* then the board specific logic must provide stm32_phyinitialize(); The
* STM32 Ethernet driver will call this function one time before it first
* uses the PHY.
@@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf);
*
****************************************************************************/
#ifdef CONFIG_STM32H7_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
int stm32_phy_boardinitialize(int intf);
#endif
arch/arm/src/stm32h7/stm32_exti_gpio.c
+6 -6
View File
@@ -44,11 +44,11 @@
* families
*/
#if defined(CONFIG_STM32H7_STM32H7X0XX) || \
defined(CONFIG_STM32H7_STM32H7X3XX) || \
defined(CONFIG_STM32H7_STM32H7B3XX) || \
defined(CONFIG_STM32H7_STM32H7X5XX) || \
defined(CONFIG_STM32H7_STM32H7X7XX)
#if defined(CONFIG_STM32_STM32H7X0XX) || \
defined(CONFIG_STM32_STM32H7X3XX) || \
defined(CONFIG_STM32_STM32H7B3XX) || \
defined(CONFIG_STM32_STM32H7X5XX) || \
defined(CONFIG_STM32_STM32H7X7XX)
/****************************************************************************
* Private Types
@@ -378,4 +378,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
return OK;
}
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */
arch/arm/src/stm32h7/stm32_fdcan_sock.c
+27 -27
View File
@@ -90,9 +90,9 @@
* critical Rx/Tx transactions on the CAN bus.
*/
# if defined(CONFIG_STM32H7_FDCAN_HPWORK)
# if defined(CONFIG_STM32_FDCAN_HPWORK)
# define CANWORK HPWORK
# elif defined(CONFIG_STM32H7_FDCAN_LPWORK)
# elif defined(CONFIG_STM32_FDCAN_LPWORK)
# define CANWORK LPWORK
# else
# define CANWORK LPWORK
@@ -326,7 +326,7 @@ struct fdcan_message_ram
/* FDCAN device structures **************************************************/
#ifdef CONFIG_STM32H7_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
static const struct fdcan_config_s stm32_fdcan0_config =
{
.tx_pin = GPIO_CAN1_TX,
@@ -339,7 +339,7 @@ static const struct fdcan_config_s stm32_fdcan0_config =
};
#endif
#ifdef CONFIG_STM32H7_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
static const struct fdcan_config_s stm32_fdcan1_config =
{
.tx_pin = GPIO_CAN2_TX,
@@ -352,7 +352,7 @@ static const struct fdcan_config_s stm32_fdcan1_config =
};
#endif
#ifdef CONFIG_STM32H7_FDCAN3
#ifdef CONFIG_STM32_FDCAN3
static const struct fdcan_config_s stm32_fdcan2_config =
{
.tx_pin = GPIO_CAN3_TX,
@@ -411,15 +411,15 @@ struct fdcan_driver_s
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H7_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
static struct fdcan_driver_s g_fdcan0;
#endif
#ifdef CONFIG_STM32H7_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
static struct fdcan_driver_s g_fdcan1;
#endif
#ifdef CONFIG_STM32H7_FDCAN3
#ifdef CONFIG_STM32_FDCAN3
static struct fdcan_driver_s g_fdcan2;
#endif
@@ -437,7 +437,7 @@ static int fdcan_txpoll(struct net_driver_s *dev);
/* Helper functions */
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct fdcan_driver_s *priv);
#endif
@@ -511,7 +511,7 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable);
* Dump common register values to the console for debugging purposes.
****************************************************************************/
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct fdcan_driver_s *priv)
{
printf("-------------- FDCAN Reg Dump ----------------\n");
@@ -685,7 +685,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing)
return 3; /* Solution not found */
}
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d"
", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1,
bs2 - 1);
@@ -1803,7 +1803,7 @@ static int fdcan_ifup(struct net_driver_s *dev)
fdcan_setinit(priv->base, 0);
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
fdcan_dumpregs(priv);
#endif
@@ -2092,7 +2092,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
return -EIO;
}
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
const struct fdcan_bitseg *tim = &priv->arbi_timing;
ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n",
tim->prescaler, tim->sjw, tim->bs1, tim->bs2);
@@ -2116,7 +2116,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
return -EIO;
}
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
tim = &priv->data_timing;
ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n",
tim->prescaler, tim->sjw, tim->bs1, tim->bs2);
@@ -2136,14 +2136,14 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
/* Operation Configuration */
#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK
#ifdef CONFIG_STM32_FDCAN_LOOPBACK
/* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */
modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST);
modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK);
#endif
#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK_INTERNAL
#ifdef CONFIG_STM32_FDCAN_LOOPBACK_INTERNAL
/* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */
modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON);
@@ -2331,7 +2331,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */
putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET);
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
fdcan_dumpregs(priv);
#endif
@@ -2339,7 +2339,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv)
fdcan_setinit(priv->base, 0);
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
fdcan_dumpregs(priv);
#endif
@@ -2395,7 +2395,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv)
{
for (uint32_t i = 0; i < NUM_RX_FIFO0; i++)
{
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]);
#endif
priv->rx[i].header.w1 = 0x0;
@@ -2411,7 +2411,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv)
{
for (uint32_t i = 0; i < NUM_TX_FIFO; i++)
{
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]);
#endif
priv->tx[i].header.w1 = 0x0;
@@ -2458,7 +2458,7 @@ int stm32_fdcansockinitialize(int intf)
switch (intf)
{
#ifdef CONFIG_STM32H7_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
case 0:
priv = &g_fdcan0;
memset(priv, 0, sizeof(struct fdcan_driver_s));
@@ -2477,7 +2477,7 @@ int stm32_fdcansockinitialize(int intf)
break;
#endif
#ifdef CONFIG_STM32H7_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
case 1:
priv = &g_fdcan1;
memset(priv, 0, sizeof(struct fdcan_driver_s));
@@ -2496,7 +2496,7 @@ int stm32_fdcansockinitialize(int intf)
break;
#endif
#ifdef CONFIG_STM32H7_FDCAN3
#ifdef CONFIG_STM32_FDCAN3
case 2:
priv = &g_fdcan2;
memset(priv, 0, sizeof(struct fdcan_driver_s));
@@ -2579,7 +2579,7 @@ int stm32_fdcansockinitialize(int intf)
netdev_register(&priv->dev, NET_LL_CAN);
#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
fdcan_dumpregs(priv);
#endif
@@ -2600,15 +2600,15 @@ int stm32_fdcansockinitialize(int intf)
#if !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)
{
#ifdef CONFIG_STM32H7_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
stm32_fdcansockinitialize(0);
#endif
#ifdef CONFIG_STM32H7_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
stm32_fdcansockinitialize(1);
#endif
#ifdef CONFIG_STM32H7_FDCAN3
#ifdef CONFIG_STM32_FDCAN3
stm32_fdcansockinitialize(2);
#endif
}
arch/arm/src/stm32h7/stm32_fdcan_sock.h
+2 -2
View File
@@ -31,7 +31,7 @@
#include "hardware/stm32_fdcan.h"
#ifdef CONFIG_STM32H7_FDCAN
#ifdef CONFIG_STM32_FDCAN
/****************************************************************************
* Pre-processor Definitions
@@ -105,5 +105,5 @@ int stm32_fdcansockinitialize(int intf);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H7_FDCAN */
#endif /* CONFIG_STM32_FDCAN */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */

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