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USART driver implementation
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2095 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -44,6 +44,9 @@
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_rcc.h"
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#include "stm32_gpio.h"
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#include "stm32_uart.h"
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#include "stm32_internal.h"
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/**************************************************************************
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@@ -77,18 +80,21 @@
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#if defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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@@ -97,7 +103,62 @@
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# error "No CONFIG_USARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Calculate BAUD rate from the SYS clock */
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/* CR1 settings */
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#if CONFIG_USART2_BITS == 9
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# define USART_CR1_M_VALUE USART_CR1_M
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#else
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# define USART_CR1_M_VALUE 0
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#endif
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#if CONFIG_USART2_PARITY == 1
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# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
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#elif CONFIG_USART2_PARITY == 2
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# define USART_CR1_PARITY_VALUE USART_CR1_PCE
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#else
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# define USART_CR1_PARITY_VALUE 0
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#endif
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#define USART_CR1_CLRBITS (USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS)
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#define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
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/* CR2 settings */
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#if CONFIG_USART2_2STOP != 0
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# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
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#else
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# define USART_CR2_STOP2_VALUE 0
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#endif
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#define USART_CR2_CLRBITS (USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE)
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#define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
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/* CR3 settings */
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#define USART_CR3_CLRBITS (USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
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#define USART_CR3_SETBITS 0
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/* Calculate USART BAUD rate divider
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*
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* The baud rate for the receiver and transmitter (Rx and Tx) are both set to
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* the same value as programmed in the Mantissa and Fraction values of USARTDIV.
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*
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* baud = fCK / (16 * usartdiv)
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* usartdiv = fCK / (16 * baud)
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*
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* Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, 5
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* or PCLK2 for USART1)
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*
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* First calculate (NOTE: all stand baud values are even so dividing by two
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* does not lose precision):
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*
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* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
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*/
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#define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
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#define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
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#define STM32_FRACTION ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
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#define STM32_BRR_VALUE ((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | (STM32_FRACTION << USART_BRR_FRAC_SHIFT))
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/**************************************************************************
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* Private Types
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@@ -136,8 +197,11 @@ void up_lowputc(char ch)
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#ifdef HAVE_CONSOLE
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/* Wait until the TX FIFO is not full */
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while ((getreg16(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) != 0);
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/* Then send the character */
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putreg16((uint16)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
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#endif
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}
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@@ -153,24 +217,122 @@ void up_lowputc(char ch)
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void up_lowsetup(void)
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{
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#if !defined(CONFIG_USART1_DISABLE) || !defined(CONFIG_USART2_DISABLE) || !defined(CONFIG_USART3_DISABLE)
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uint32 enr;
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uint32 mapr;
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
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uint32 cr;
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#endif
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/* Enable the selected USARTs and configure GPIO pins need byed the
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* the selected USARTs. NOTE: The serial driver later depends on
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* this pin configuration -- whether or not a serial console is selected.
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*/
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#ifndef CONFIG_USART1_DISABLE
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#endif
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mapr = getreg32(STM32_AFIO_MAPR);
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#ifndef CONFIG_USART1_DISABLE
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#endif
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/* Enable USART1 clocking */
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enr = getreg32(STM32_RCC_APB2ENR_OFFSET);
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enr |= RCC_APB2ENR_USART1EN;
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putreg32(enr, STM32_RCC_APB2ENR_OFFSET);
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/* Assume default pin mapping:
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*
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* Alternate USART1_REMAP USART1_REMAP
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* Function = 0 = 1
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* ---------- ------------ ------------
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* USART1_TX PA9 PB6
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* USART1_RX PA10 PB7
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*/
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mapr &= ~AFIO_MAPR_USART1_REMAP;
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#endif /* !CONFIG_USART1_DISABLE */
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#if !defined(CONFIG_USART2_DISABLE) && !defined(CONFIG_USART3_DISABLE)
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enr = getreg32(STM32_RCC_APB1ENR_OFFSET);
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#ifndef CONFIG_USART2_DISABLE
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#endif
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/* Enable USART2 clocking */
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enr |= RCC_APB1ENR_USART2EN;
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/* Assume default pin mapping:
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*
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* Alternate USART2_REMAP USART2_REMAP
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* Function = 0 = 1
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* ---------- ------------ ------------
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* USART2_TX PA2 PD5
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* USART2_RX PA3 PD6
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*/
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mapr &= ~AFIO_MAPR_USART2_REMAP;
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#endif /* !CONFIG_USART2_DISABLE */
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#ifndef CONFIG_USART3_DISABLE
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/* Enable USART3 clocking */
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enr |= RCC_APB1ENR_USART3EN;
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/* Assume default pin mapping:
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*
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*
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* Alternate USART3_REMAP[1:0] USART3_REMAP[1:0] USART3_REMAP[1:0]
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* Function = “00” (no remap) = “01” (partial remap) = “11” (full remap)
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* --------- ------------------ ---------------------- --------------------
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* USART3_TX PB10 PC10 PD8
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* USART3_RX PB11 PC11 PD9
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*/
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mapr &= ~AFIO_MAPR_USART3_REMAP_MASK;
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#endif /* !CONFIG_USART3_DISABLE */
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/* Save the UART enable settings */
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putreg32(enr, STM32_RCC_APB1ENR_OFFSET);
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#endif /* !CONFIG_USART2_DISABLE && !CONFIG_USART3_DISABLE */
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/* Save the USART pin mappings */
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putreg32(mapr, STM32_AFIO_MAPR);
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/* Enable and configure the selected console device */
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_USART_CONFIG)
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/* Configure CR2 */
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cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
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cr &= ~USART_CR2_CLRBITS;
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cr |= USART_CR2_SETBITS;
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putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
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/* Configure CR1 */
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cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
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cr &= ~USART_CR1_CLRBITS;
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cr |= USART_CR1_SETBITS;
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putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
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/* Configure CR3 */
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cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
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cr &= ~USART_CR3_CLRBITS;
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cr |= USART_CR3_SETBITS;
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putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
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/* Configure the USART Baud Rate */
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putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
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/* Enable Rx, Tx, and the USART */
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cr = getreg16(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
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cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
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putreg16(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
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#endif
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#endif /* !CONFIG_USART1_DISABLE && !CONFIG_USART2_DISABLE && !CONFIG_USART3_DISABLE */
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}
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@@ -117,7 +117,7 @@
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#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
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# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
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# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
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# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
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# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
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# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
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# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
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@@ -230,7 +230,7 @@
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#define RCC_AHBENR_SRAMEN (1 << 2) /* Bit 2: SRAM interface clock enable */
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#define RCC_AHBENR_FLITFEN (1 << 4) /* Bit 4: FLITF clock enable */
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#define RCC_AHBENR_CRCEN (1 << 6) /* Bit 6: CRC clock enable */
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#define RCC_AHBENR_SDIOEN (1 << 8) /* Bit 8: FSMC clock enable */
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#define RCC_AHBENR_FSMCEN (1 << 8) /* Bit 8: FSMC clock enable */
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#define RCC_AHBENR_SDIOEN (1 << 10) /* Bit 10: SDIO clock enable */
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/* APB2 Peripheral Clock enable register */
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+356
-149
File diff suppressed because it is too large
Load Diff
@@ -113,6 +113,9 @@
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#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_SR_ALLBITS (0x03ff)
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#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
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/* Data register */
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#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
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@@ -142,6 +145,8 @@
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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/* Control register 2 */
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#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
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