mirror of
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- imxrt: Add PIT, GPT, and QIMER(TMR) header files
Squashed commit of the following:
imxrt: Add QTIMER(TMR)
imxrt: Add GPT
imxrt: Add PIT
This commit is contained in:
David Sidrane
committed by
Gregory Nutt
Gregory Nutt
parent
9b68efe251
commit
c6db972702
@@ -0,0 +1,182 @@
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/************************************************************************************
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* arch/arm/src/imxrt/chip/imxrt_gpt.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
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#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/imxrt_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define IMXRT_GPT_CR_OFFSET 0xc000 /* GPT Control Register */
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#define IMXRT_GPT_PR_OFFSET 0xc004 /* GPT Prescaler Register */
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#define IMXRT_GPT_SR_OFFSET 0xc008 /* GPT Status Register */
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#define IMXRT_GPT_IR_OFFSET 0xc00c /* GPT Interrupt Register */
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#define IMXRT_GPT_OCR1_OFFSET 0xc010 /* GPT Output Compare Register 1 */
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#define IMXRT_GPT_OCR2_OFFSET 0xc014 /* GPT Output Compare Register 2 */
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#define IMXRT_GPT_OCR3_OFFSET 0xc018 /* GPT Output Compare Register 3 */
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#define IMXRT_GPT_ICR1_OFFSET 0xc01c /* GPT Input Capture Register 1 */
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#define IMXRT_GPT_ICR2_OFFSET 0xc020 /* GPT Input Capture Register 2 */
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#define IMXRT_GPT_CNT_OFFSET 0xc024 /* GPT Counter Register */
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/* Register addresses ***********************************************************************/
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#define IMXRT_GPT1_CR (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET) /* GPT 1 Control Register */
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#define IMXRT_GPT1_PR (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET) /* GPT 1 Prescaler Register */
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#define IMXRT_GPT1_SR (IMXRT_GPT1_BASE + IMXRT_GPT1_SR_OFFSET) /* GPT 1 Status Register */
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#define IMXRT_GPT1_IR (IMXRT_GPT1_BASE + IMXRT_GPT1_IR_OFFSET) /* GPT 1 Interrupt Register */
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#define IMXRT_GPT1_OCR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR1_OFFSET) /* GPT 1 Output Compare Register 1 */
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#define IMXRT_GPT1_OCR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR2_OFFSET) /* GPT 1 Output Compare Register 2 */
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#define IMXRT_GPT1_OCR3 (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR3_OFFSET) /* GPT 1 Output Compare Register 3 */
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#define IMXRT_GPT1_ICR1 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR1_OFFSET) /* GPT 1 Input Capture Register 1 */
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#define IMXRT_GPT1_ICR2 (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR2_OFFSET) /* GPT 1 Input Capture Register 2 */
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#define IMXRT_GPT1_CNT (IMXRT_GPT1_BASE + IMXRT_GPT1_CNT_OFFSET) /* GPT 1 Counter Register */
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#define IMXRT_GPT2_CR (IMXRT_GPT2_BASE + IMXRT_GPT2_CR_OFFSET) /* GPT 2 Control Register */
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#define IMXRT_GPT2_PR (IMXRT_GPT2_BASE + IMXRT_GPT2_PR_OFFSET) /* GPT 2 Prescaler Register */
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#define IMXRT_GPT2_SR (IMXRT_GPT2_BASE + IMXRT_GPT2_SR_OFFSET) /* GPT 2 Status Register */
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#define IMXRT_GPT2_IR (IMXRT_GPT2_BASE + IMXRT_GPT2_IR_OFFSET) /* GPT 2 Interrupt Register */
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#define IMXRT_GPT2_OCR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR1_OFFSET) /* GPT 2 Output Compare Register 1 */
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#define IMXRT_GPT2_OCR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR2_OFFSET) /* GPT 2 Output Compare Register 2 */
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#define IMXRT_GPT2_OCR3 (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR3_OFFSET) /* GPT 2 Output Compare Register 3 */
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#define IMXRT_GPT2_ICR1 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR1_OFFSET) /* GPT 2 Input Capture Register 1 */
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#define IMXRT_GPT2_ICR2 (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR2_OFFSET) /* GPT 2 Input Capture Register 2 */
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#define IMXRT_GPT2_CNT (IMXRT_GPT2_BASE + IMXRT_GPT2_CNT_OFFSET) /* GPT 2 Counter Register */
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/* GPT Control Register */
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/* Register Bit Definitions *********************************************************/
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#define GPT_CR_EN (1 << 0) /* Bit: 0 GPT Enable. */
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#define GPT_CR_ENMOD (1 << 1) /* Bit: 1 GPT Enable mode. */
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#define GPT_CR_DBGEN (1 << 2) /* Bit: 2 GPT debug mode enable. */
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#define GPT_CR_WAITEN (1 << 3) /* Bit: 3 GPT Wait Mode enable. */
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#define GPT_CR_DOZEEN (1 << 4) /* Bit: 4 GPT Doze Mode Enable. */
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#define GPT_CR_STOPEN (1 << 5) /* Bit: 5 GPT Stop Mode enable. */
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#define GPT_CR_CLKSRC_SHIFT (6) /* Bits: 6-8 Clock Source select. */
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#define GPT_CR_CLKSRC_MASK (7 << GPT_CR_CLKSRC_SHIFT)
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# define GPT_CR_CLKSRC(n) ((uint32_t)(n) << GPT_CR_CLKSRC_SHIFT)
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# define GPT_CR_CLKSRC_NONE (0 << GPT_CR_CLKSRC_SHIFT) /* No clock */
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# define GPT_CR_CLKSRC_IPG (1 << GPT_CR_CLKSRC_SHIFT) /* Peripheral Clock (ipg_clk) */
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# define GPT_CR_CLKSRC_IPG_HFR (2 << GPT_CR_CLKSRC_SHIFT) /* High Frequency Reference Clock (ipg_clk_highfreq) */
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# define GPT_CR_CLKSRC_EXT (3 << GPT_CR_CLKSRC_SHIFT) /* External Clock */
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# define GPT_CR_CLKSRC_IPG_LFR (4 << GPT_CR_CLKSRC_SHIFT) /* Low Frequency Reference Clock (ipg_clk_32k) */
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# define GPT_CR_CLKSRC_IPG_24M (5 << GPT_CR_CLKSRC_SHIFT) /* Crystal oscillator as Reference Clock (ipg_clk_24M) */
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#define GPT_CR_FRR (1 << 9) /* Bit: 9 Free-Run or Restart mode. */
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#define GPT_CR_EN_24M (1 << 10) /* Bit: 10 Enable 24 MHz clock input from crystal. */
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/* Bits: 11-14 Reserved */
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#define GPT_CR_SWR (1 << 15) /* Bit: 15 Software reset. */
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#define GPT_CR_IM1_SHIFT (16) /* Bits: 16-17 See IM2 */
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#define GPT_CR_IM1_MASK (3 << GPT_CR_IM1_SHIFT)
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# define GPT_CR_IM1(n) ((uint32_t)(n) << GPT_CR_IM1_SHIFT)
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# define GPT_CR_IM1_DIS (0 << GPT_CR_IM1_SHIFT) /* Capture disabled */
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# define GPT_CR_IM1_RISING (1 << GPT_CR_IM1_SHIFT) /* Capture on rising edge */
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# define GPT_CR_IM1_FALLING (2 << GPT_CR_IM1_SHIFT) /* Capture on falling edge */
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# define GPT_CR_IM1_BOTH (3 << GPT_CR_IM1_SHIFT) /* Capture on both edges */
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#define GPT_CR_IM2_SHIFT (18) /* Bits: 18-19 IM2 (bits 19-18, Input Capture Channel 2 operating mode) */
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#define GPT_CR_IM2_MASK (3 << GPT_CR_IM2_SHIFT)
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# define GPT_CR_IM2(n) ((uint32_t)(n) << GPT_CR_IM2_SHIFT)
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# define GPT_CR_IM2_DIS (0 << GPT_CR_IM2_SHIFT) /* Capture disabled */
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# define GPT_CR_IM2_RISING (1 << GPT_CR_IM2_SHIFT) /* Capture on rising edge */
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# define GPT_CR_IM2_FALLING (2 << GPT_CR_IM2_SHIFT) /* Capture on falling edge */
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# define GPT_CR_IM2_BOTH (3 << GPT_CR_IM2_SHIFT) /* Capture on both edges */
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#define GPT_CR_OM1_SHIFT (20) /* Bits: 20-22 See OM3 */
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#define GPT_CR_OM1_MASK (7 << GPT_CR_OM1_SHIFT)
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# define GPT_CR_OM1(n) ((uint32_t)(n) << GPT_CR_OM1_SHIFT)
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# define GPT_CR_OM1_DIS (0 << GPT_CR_OM1_SHIFT) /* Output disconnected. No response on pin. */
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# define GPT_CR_OM1_TOGGLE (1 << GPT_CR_OM1_SHIFT) /* Toggle output pin */
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# define GPT_CR_OM1_CLEAR (2 << GPT_CR_OM1_SHIFT) /* Clear output pin */
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# define GPT_CR_OM1_SET (3 << GPT_CR_OM1_SHIFT) /* Set output pin */
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# define GPT_CR_OM1_PULSE (4 << GPT_CR_OM1_SHIFT) /* Generate an active low pulse */
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#define GPT_CR_OM2_SHIFT (23) /* Bits: 23-25 See OM3 */
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#define GPT_CR_OM2_MASK (7 << GPT_CR_OM2_SHIFT)
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# define GPT_CR_OM2(n) ((uint32_t)(n) << GPT_CR_OM2_SHIFT)
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# define GPT_CR_OM2_DIS (0 << GPT_CR_OM2_SHIFT) /* Output disconnected. No response on pin. */
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# define GPT_CR_OM2_TOGGLE (1 << GPT_CR_OM2_SHIFT) /* Toggle output pin */
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# define GPT_CR_OM2_CLEAR (2 << GPT_CR_OM2_SHIFT) /* Clear output pin */
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# define GPT_CR_OM2_SET (3 << GPT_CR_OM2_SHIFT) /* Set output pin */
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# define GPT_CR_OM2_PULSE (4 << GPT_CR_OM2_SHIFT) /* Generate an active low pulse */
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#define GPT_CR_OM3_SHIFT (26) /* Bits: 26-28 OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */
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#define GPT_CR_OM3_MASK (7 << GPT_CR_OM3_SHIFT)
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# define GPT_CR_OM3(n) ((uint32_t)(n) << GPT_CR_OM3_SHIFT)
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# define GPT_CR_OM3_DIS (0 << GPT_CR_OM3_SHIFT) /* Output disconnected. No response on pin. */
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# define GPT_CR_OM3_TOGGLE (1 << GPT_CR_OM3_SHIFT) /* Toggle output pin */
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# define GPT_CR_OM3_CLEAR (2 << GPT_CR_OM3_SHIFT) /* Clear output pin */
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# define GPT_CR_OM3_SET (3 << GPT_CR_OM3_SHIFT) /* Set output pin */
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# define GPT_CR_OM3_PULSE (4 << GPT_CR_OM3_SHIFT) /* Generate an active low pulse */
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#define GPT_CR_FO1 (1 << 29) /* Bit: 29 See F03 */
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#define GPT_CR_FO2 (1 << 30) /* Bit: 30 See F03 */
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#define GPT_CR_FO3 (1 << 31) /* Bit: 31 FO3 Force Output Compare Channel 3 */
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/* GPT Prescaler Register */
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#define GPT_PR_PRESCALER_SHIFT (0) /* Bits: 0-11 Prescaler bits. */
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#define GPT_PR_PRESCALER_MASK (0xfff << GPT_PR_PRESCALER_SHIFT)
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# define GPT_PR_PRESCALER(n) ((uint32_t)(n) << GPT_PR_PRESCALER_SHIFT)
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#define GPT_PR_PRESCALER24M_SHIFT (12) /* Bits: 12-15 Prescaler bits. */
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#define GPT_PR_PRESCALER24M_MASK (0xf << GPT_PR_PRESCALER24M_SHIFT)
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# define GPT_PR_PRESCALER24M(n) ((uint32_t)(n) << GPT_PR_PRESCALER24M_SHIFT)
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/* Bits: 16-31 Reserved */
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/* GPT Status Register */
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#define GPT_SR_OF1 (1 << 0) /* Bit: 0 Output Compare 1 Flag*/
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#define GPT_SR_OF2 (1 << 1) /* Bit: 1 Output Compare 2 Flag*/
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#define GPT_SR_OF3 (1 << 2) /* Bit: 2 Output Compare 3 Flag */
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#define GPT_SR_IF1 (1 << 3) /* Bit: 3 Input capture 1 Flag */
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#define GPT_SR_IF2 (1 << 4) /* Bit: 4 Input capture 2 Flag */
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#define GPT_SR_ROV (1 << 5) /* Bit: 5 Rollover Flag. */
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/* Bits: 6-31 Reserved */
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/* GPT Interrupt Register */
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#define GPT_IR_OF1IE (1 << 0) /* Bit: 0 Output Compare 1 Interrupt Enable */
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#define GPT_IR_OF2IE (1 << 1) /* Bit: 1 Output Compare 2 Interrupt Enable */
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#define GPT_IR_OF3IE (1 << 2) /* Bit: 2 Output Compare 3 Interrupt Enable */
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#define GPT_IR_IF1IE (1 << 3) /* Bit: 3 Input capture 1 Interrupt Enable */
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#define GPT_IR_IF2IE (1 << 4) /* Bit: 4 Input capture 2 Interrupt Enable */
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#define GPT_IR_ROVIE (1 << 5) /* Bit: 5 Rollover Interrupt Enable. */
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/* Bits: 6-31 Reserved */
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#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H */
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@@ -0,0 +1,131 @@
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/************************************************************************************
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* arch/arm/src/imxrt/chip/imxrt_pit.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
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#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/imxrt_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define IMXRT_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */
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#define IMXRT_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */
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#define IMXRT_PIT_LTMR64L_OFFSET 0x00e4 /* PIT Lower Lifetime Timer Register */
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#define IMXRT_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */
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#define IMXRT_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */
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#define IMXRT_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */
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#define IMXRT_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */
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#define IMXRT_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */
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#define IMXRT_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */
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#define IMXRT_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */
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#define IMXRT_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */
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#define IMXRT_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */
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#define IMXRT_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */
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#define IMXRT_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */
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#define IMXRT_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */
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#define IMXRT_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */
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#define IMXRT_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */
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#define IMXRT_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */
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#define IMXRT_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */
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/* Register Addresses ***************************************************************/
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#define IMXRT_PIT_MCR (IMXRT_PIT_BASE+IMXRT_PIT_MCR_OFFSET)
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#define IMXRT_PIT_LTMR64H (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64H_OFFSET)
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#define IMXRT_PIT_LTMR64L (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64L_OFFSET)
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#define IMXRT_PIT_LDVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL0_OFFSET)
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#define IMXRT_PIT_CVAL0 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL0_OFFSET)
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#define IMXRT_PIT_TCTRL0 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL0_OFFSET)
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#define IMXRT_PIT_TFLG0 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG0_OFFSET)
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#define IMXRT_PIT_LDVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL1_OFFSET)
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#define IMXRT_PIT_CVAL1 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL1_OFFSET)
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#define IMXRT_PIT_TCTRL1 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL1_OFFSET)
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#define IMXRT_PIT_TFLG1 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG1_OFFSET)
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#define IMXRT_PIT_LDVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL2_OFFSET)
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#define IMXRT_PIT_CVAL2 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL2_OFFSET)
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#define IMXRT_PIT_TCTRL2 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL2_OFFSET)
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#define IMXRT_PIT_TFLG2 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG2_OFFSET)
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#define IMXRT_PIT_LDVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL3_OFFSET)
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#define IMXRT_PIT_CVAL3 (IMXRT_PIT_BASE+IMXRT_PIT_CVAL3_OFFSET)
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#define IMXRT_PIT_TCTRL3 (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL3_OFFSET)
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#define IMXRT_PIT_TFLG3 (IMXRT_PIT_BASE+IMXRT_PIT_TFLG3_OFFSET)
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/* Register Bit Definitions *********************************************************/
|
||||
|
||||
/* PIT Module Control Register */
|
||||
|
||||
#define PIT_MCR_FRZ (1 << 0) /* Bit 0: Freeze */
|
||||
#define PIT_MCR_MDIS (1 << 1) /* Bit 1: Module Disable */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* Timer Load Value Register (32-bit Timer Start Value Bits) */
|
||||
/* Current Timer Value Register (32-bit Current Timer Value) */
|
||||
|
||||
/* Timer Control Register */
|
||||
|
||||
#define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */
|
||||
#define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */
|
||||
/* Bits 2-31: Reserved */
|
||||
#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode */
|
||||
/* Bits 3-31: Reserved */
|
||||
|
||||
/* Timer Flag Register */
|
||||
|
||||
#define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H */
|
||||
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Load Diff
Reference in New Issue
Block a user