arch/risc-v: Add handler for misaligned load/store

Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

arch/risc-v/src/common/riscv_internal.h

@@ -287,6 +287,7 @@ void riscv_netinitialize(void);
 
 uintptr_t *riscv_doirq(int irq, uintptr_t *regs);
 void riscv_exception(uintptr_t mcause, uintptr_t *regs);
+int riscv_misaligned(int irq, void *context, void *arg);
 
 /* Debug ********************************************************************/