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With these changes the S32K146EVB minimal NSH is function. Only verifed while running from SRAM.

Browse Source 
arch/arm/src/s32k1xx/s32k1xx_lowputc.c:  Fix a typo that prevented LPUART1 from working.
    arch/arm/src/s32k1xx/s32k1xx_periphclocks.c and related files:  Fix yet another case of confusion between pre-decremented and non-decremented divider values.  Enforce the rule that dividers are not decremented until the moment they are written into registers.
    arch/arm/src/s32k1xx/s32k1xx_clockconfig.c:  Fix another problem related to whether a divider is pre-decremented or not.  The answer must be the divder values are never pre-decremented.  They are decremented just before being written to hardware.
    arch/arm/src/s32k1xx/s32k1xx_clockconfig.c:  Clean up some bad conditional logic.  Precedence of operators problem.
    boards/arm/s32k1xx/s32k118evb:  Add support for execution out of SRAM.  This is helpful for bringup when you want to avoid putting a lethal image in FLASH.
    arch/arm/src/s32k1xx/s32k1xx_clockconfig.h:  Remove crystal frequency, it is not used.
    arch/arm/src/s32k1xx/s32k1xx_wdog.h:  Fix a typo in a register name.i
    boards/arm/s32k1xx/s32k*evb/configs/nsh/defconfig:  Create Motorola SREC output format.
This commit is contained in:
Gregory Nutt
2019-08-20 14:34:26 -06:00
parent 64fb11c1b8
commit c6026d7500
17 changed files with 318 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/arm/s32k1xx/s32k118evb/README.txt
+22
View File
@@ -9,6 +9,7 @@ Contents
o Status
o Serial Console
o LEDs and Buttons
o OpenSDA Notes
o Configurations
Status
@@ -21,6 +22,12 @@ Status
are interested in assisting with the bring-up.
2019-08-17: The port is code complete. It compiles with no errors or
warnings but is untested. Still waiting for hardware.
2019-08-20: I have the board and started the debug. However, the
very first image that I wrote to FLASH seems to have "bricked" the
board. I believe that the S32K118 resets into a bad state and
cannot interface with the OpenSDA, effectively cutting it off from
the world. I will continuing the bring-up using the S32K146EVB
where I can run from SRAM for the initial bring-up.
Serial Console
==============
@@ -30,6 +37,9 @@ Serial Console
OpenSDA UART TX PTB1(LPUART0_TX)
OpenSDA UART RX PTB0(LPUART0_RX)
USB drivers for the PEMIcro CDC Serial port are available here:
http://www.pemicro.com/opensda/
LEDs and Buttons
================
@@ -74,6 +84,18 @@ LEDs and Buttons
SW2 PTD3
SW3 PTD5
OpenSDA Notes
=============
- USB drivers for the PEMIcro CDC Serial port are available here:
http://www.pemicro.com/opensda/
- The drag'n'drog interface expects files in .srec format.
- Using Segger J-Link: Easy... but remember to use the SWD connector J14
near the touch electrodes and not the OpenSDA connector near the OpenSDA
USB connector J7.
Configurations
==============
boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig
+1 -3
View File
@@ -24,14 +24,13 @@ CONFIG_BOARD_LOOPSPERMSEC=2988
CONFIG_DEFAULT_SMALL=y
CONFIG_DISABLE_MOUNTPOINT=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_HOST_WINDOWS=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LPUART0_RXBUFSIZE=64
CONFIG_LPUART0_SERIAL_CONSOLE=y
CONFIG_LPUART0_TXBUFSIZE=64
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_SMALL=y
CONFIG_MOTOROLA_SREC=y
CONFIG_NFILE_DESCRIPTORS=6
CONFIG_NFILE_STREAMS=6
CONFIG_NPTHREAD_KEYS=0
@@ -50,7 +49,6 @@ CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=1536
CONFIG_RAM_SIZE=23552
CONFIG_RAM_START=0x1ffffc00
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_S32K1XX_LPUART0=y
CONFIG_SCHED_WAITPID=y
boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
-1
View File
@@ -100,7 +100,6 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.sosc =
{
.freq = 40000000, /* Frequency */
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
+10 -10
View File
@@ -84,69 +84,69 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = DMAMUX0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPTMR0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPUART0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPUART1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTA_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTB_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTC_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTD_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTE_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
};
boards/arm/s32k1xx/s32k146evb/README.txt
+21 -2
View File
@@ -9,17 +9,21 @@ Contents
o Status
o Serial Console
o LEDs and Buttons
o OpenSDA Notes
o Configurations
Status
======
2019-08-148 Configuration created but entirely untested. This
2019-08-18: Configuration created but entirely untested. This
configuration is intended, initially, to verify s32k14x architecture
support. The configuration builds and linkes without error but has
support. The configuration builds and links without error but has
not yet been tested. This is VERY much a work in progress and you
should not use this configuration unless you are interested in
assisting with the bring-up.
2019-08-20: Initial testing, I am running out of SRAM to avoid the
brickage problems I had with the S32K118EVB (i.e., with
CONFIG_BOOT_RUNFROMISRAM=y)
Serial Console
==============
@@ -29,6 +33,9 @@ Serial Console
OpenSDA UART TX PTC7 (LPUART1_TX)
OpenSDA UART RX PTC6 (LPUART1_RX)
USB drivers for the PEMIcro CDC Serial port are available here:
http://www.pemicro.com/opensda/
LEDs and Buttons
================
@@ -73,6 +80,18 @@ LEDs and Buttons
SW2 PTC12
SW3 PTC13
OpenSDA Notes
=============
- USB drivers for the PEMIcro CDC Serial port are available here:
http://www.pemicro.com/opensda/
- The drag'n'drog interface expects files in .srec format.
- Using Segger J-Link: Easy... but remember to use the SWD J14 connector
in the center of the board and not the OpenSDA connector closer to the
OpenSDA USB connector J7.
Configurations
==============
boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
+1 -2
View File
@@ -25,13 +25,13 @@ CONFIG_DEFAULT_SMALL=y
CONFIG_DISABLE_MOUNTPOINT=y
CONFIG_DISABLE_MQUEUE=y
CONFIG_HOST_WINDOWS=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LPUART1_RXBUFSIZE=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=64
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_SMALL=y
CONFIG_MOTOROLA_SREC=y
CONFIG_NFILE_DESCRIPTORS=6
CONFIG_NFILE_STREAMS=6
CONFIG_NPTHREAD_KEYS=0
@@ -50,7 +50,6 @@ CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=1536
CONFIG_RAM_SIZE=23552
CONFIG_RAM_START=0x1ffffc00
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
boards/arm/s32k1xx/s32k146evb/scripts/Make.defs
+8 -1
View File
@@ -37,8 +37,13 @@ include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = flash.ld
ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
LDSCRIPT = flash.ld
else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
LDSCRIPT = sram.ld
endif
$(warning, LDSCRIPT is $(LDSCRIPT))
ifeq ($(WINTOOL),y)
# Windows-native toolchains
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
@@ -50,6 +55,8 @@ else
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
endif
$(warning, LDSCRIPT is $(LDSCRIPT))
$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
boards/arm/s32k1xx/s32k146evb/scripts/sram.ld
+131
View File
@@ -0,0 +1,131 @@
/****************************************************************************
* boards/arm/s32k1xx/s32k146evb/scripts/sram.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and
* 124Kb of SRAM beginning at address 0x1fff:fc00 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
* SRAM_L 1fff0000 - 1fffffff 64Kb
* SRAM_U 20000000 - 2000efff 60Kb
*/
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 1M
sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text :
{
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > sram
. = ALIGN(4);
.init_section :
{
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sram
. = ALIGN(4);
.ARM.extab :
{
*(.ARM.extab*)
} >sram
. = ALIGN(4);
__exidx_start = ABSOLUTE(.);
.ARM.exidx :
{
*(.ARM.exidx*)
} >sram
__exidx_end = ABSOLUTE(.);
. = ALIGN(4);
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram
.bss :
{
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
-1
View File
@@ -100,7 +100,6 @@ const struct clock_configuration_s g_initial_clkconfig =
},
.sosc =
{
.freq = 8000000, /* Frequency */
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
.range = SCG_SOSC_RANGE_MID, /* RANGE */
boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c
+12 -12
View File
@@ -84,76 +84,76 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
.clkgate = true,
.clksrc = CLK_SRC_FIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = ADC1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_FIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPTMR0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPUART0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPUART1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = LPUART2_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.frac = 1,
.divider = 1,
},
{
.clkname = PORTA_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTB_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTC_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTD_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
},
{
.clkname = PORTE_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = DIVIDE_BY_ONE,
.divider = 1,
}
};