diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
index c80f16a767d..3c704fa8f63 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
@@ -478,15 +478,16 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src)
  *
  *****************************************************************************/
 
-static int s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
-                                            const struct scg_system_clock_config_s *config)
+static int
+s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
+                                 const struct scg_system_clock_config_s *config)
 {
   uint32_t srcfreq      = 0;
-  uint32_t sysfreq_mul  = ((uint32_t)config->divcore) + 1;
-  uint32_t busfreq_mul  = (((uint32_t)config->divcore) + 1) * (((uint32_t)config->divbus) + 1);
-  uint32_t slowfreq_mul = (((uint32_t)config->divcore) + 1) * (((uint32_t)config->divslow) + 1);
+  uint32_t sysfreq_mul  = (uint32_t)config->divcore;
+  uint32_t busfreq_mul  = (uint32_t)config->divcore * (uint32_t)config->divbus;
+  uint32_t slowfreq_mul = (uint32_t)config->divcore * (uint32_t)config->divslow;
   uint32_t regval;
-  int ret = OK;
+  int ret               = OK;
 
   DEBUGASSERT(mode != SCG_SYSTEM_CLOCK_MODE_CURRENT);
 
@@ -708,14 +709,31 @@ static int s32k1xx_firc_config(bool enable,
 
       /* Step 2. Set FIRC configuration. */
 
-      regval = (firccfg->range == 0 ? 0 : SCG_FIRCCFG_48MHZ);
+      if (firccfg->range == 0)
+        {
+          regval = 0;
+        }
+      else
+        {
+          regval = SCG_FIRCCFG_48MHZ; /* REVISIT: Also zero */
+        }
+
       putreg32(regval, S32K1XX_SCG_FIRCCFG);
 
       /* Step 3. Enable clock, config regulator and locking feature. */
 
-      regval = SCG_FIRCCSR_FIRCEN |
-               firccfg->regulator ? 0 : SCG_FIRCCSR_FIRCREGOFF |
-               firccfg->locked ? SCG_FIRCCSR_LK : 0;
+      regval = SCG_FIRCCSR_FIRCEN;
+
+      if (!firccfg->regulator)
+        {
+          regval |= SCG_FIRCCSR_FIRCREGOFF;
+        }
+
+      if (firccfg->locked)
+        {
+          regval |= SCG_FIRCCSR_LK;
+        }
+
       putreg32(regval, S32K1XX_SCG_FIRCCSR);
 
       /* Wait for FIRC to initialize */
@@ -801,10 +819,6 @@ static int s32k11_firc_clocksource(void)
  *
  *****************************************************************************/
 
-/*FUNCTION**********************************************************************
- * Function Name : 
- * Description   : 
- * END**************************************************************************/
 static int s32k1xx_sirc_config(bool enable,
                                const struct scg_sirc_config_s *sirccfg)
 {
@@ -850,18 +864,38 @@ static int s32k1xx_sirc_config(bool enable,
 
       /* Step 2. Set SIRC configuration: frequency range. */
 
-      regval = (sirccfg->range == 0) ? SCG_SIRCCFG_LOWRANGE :
-               SCG_SIRCCFG_HIGHRANGE; 
+      if (sirccfg->range == SCG_SIRC_RANGE_HIGH)
+        {
+          regval = SCG_SIRCCFG_HIGHRANGE;
+        }
+      else
+        {
+          regval = SCG_SIRCCFG_LOWRANGE;
+        }
+
       putreg32(regval, S32K1XX_SCG_SIRCCFG);
 
       /* Step 3. Set SIRC control: enable clock, configure source in STOP
        * and VLP modes, configure lock feature.
        */
 
-      regval = SCG_SIRCCSR_SIRCEN |
-               (sirccfg->stopmode == 0) ? 0 : SCG_SIRCCSR_SIRCSTEN |
-               (sirccfg->lowpower == 0) ? 0 : SCG_SIRCCSR_SIRCLPEN |
-               (sirccfg->locked == 0) ? 0 : SCG_SIRCCSR_LK;
+      regval = SCG_SIRCCSR_SIRCEN;
+
+      if (sirccfg->stopmode)
+        {
+          regval |= SCG_SIRCCSR_SIRCSTEN;
+        }
+
+      if (sirccfg->lowpower)
+        {
+          regval |= SCG_SIRCCSR_SIRCLPEN;
+        }
+
+      if (sirccfg->locked)
+        {
+          regval |= SCG_SIRCCSR_LK;
+        }
+
       putreg32(regval, S32K1XX_SCG_SIRCCSR);
 
       /* Wait for SIRC to initialize */
@@ -941,14 +975,28 @@ static int s32k1xx_sosc_config(bool enable,
 
       /* Step 2. Set OSC configuration. */
 
-      regval = SCG_SOSCCFG_RANGE(sosccfg->range) |
-               (sosccfg->gain == 0) ? 0 : SCG_SOSCCFG_HGO |
-               (sosccfg->extref == 0) ? 0 : SCG_SOSCCFG_EREFS;
+      regval = SCG_SOSCCFG_RANGE(sosccfg->range);
+
+      if (sosccfg->gain == SCG_SOSC_GAIN_HIGH)
+        {
+          regval |= SCG_SOSCCFG_HGO;
+        }
+
+      if (sosccfg->extref == SCG_SOSC_REF_OSC)
+        {
+          regval |= SCG_SOSCCFG_EREFS;
+        }
+
       putreg32(regval, S32K1XX_SCG_SOSCCFG);
 
       /* Step 3. Enable clock, configure monitor, lock register. */
 
-      regval = SCG_SOSCCSR_SOSCEN | sosccfg->locked ? SCG_SOSCCSR_LK : 0;
+      regval = SCG_SOSCCSR_SOSCEN;
+
+      if (sosccfg->locked)
+        {
+          regval |= SCG_SOSCCSR_LK;
+        }
 
       switch (sosccfg->mode)
         {
@@ -1046,7 +1094,7 @@ static int s32k1xx_spll_config(bool enable,
     }
 
   /* Configure SPLL */
- 
+
   if (enable && (ret == OK))
     {
       /* Get clock source frequency. */
@@ -1056,7 +1104,7 @@ static int s32k1xx_spll_config(bool enable,
 
       /* Pre-divider checking. */
 
-      srcfreq /= (((uint32_t)spllcfg->prediv) + 1);
+      srcfreq /= spllcfg->prediv;
       DEBUGASSERT(srcfreq >= SCG_SPLL_REF_MIN && srcfreq <= SCG_SPLL_REF_MAX);
 
       /* Now start to set up PLL clock. */
@@ -1073,7 +1121,12 @@ static int s32k1xx_spll_config(bool enable,
 
       /* Step 3. Enable clock, configure monitor, lock register. */
 
-      regval = SCG_SPLLCSR_SPLLEN | spllcfg->locked ? SCG_SPLLCSR_LK : 0;
+      regval = SCG_SPLLCSR_SPLLEN;
+
+      if (spllcfg->locked)
+        {
+          regval |= SCG_SPLLCSR_LK;
+        }
 
       switch (spllcfg->mode)
         {
diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
index 6464d708828..6cc2b81fa75 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
@@ -183,11 +183,10 @@ enum scg_sosc_range_e
 
 struct scg_sosc_config_s
 {
-  uint32_t freq;                       /* System OSC frequency */
   enum scg_sosc_monitor_mode_e mode;   /* System OSC Clock monitor mode */
   enum scg_sosc_ext_ref_e extref;      /* System OSC External Reference Select */
   enum scg_sosc_gain_e gain;           /* System OSC high-gain operation */
-  enum scg_sosc_gain_e range;          /* System OSC frequency range */
+  enum scg_sosc_range_e range;         /* System OSC frequency range */
   enum scg_async_clock_div_e div1;     /* Asynchronous peripheral source */
   enum scg_async_clock_div_e div2;     /* Asynchronous peripheral source */
   bool initialize;                     /* true: Initialize the System OSC module */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c
index 039e3e60223..b65bd5075e5 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c
@@ -226,7 +226,7 @@ int s32k1xx_lpuart_configure(uint32_t base,
 #ifdef CONFIG_S32K1XX_LPUART1
   if (base == S32K1XX_LPUART1_BASE)
     {
-      clkname = LPUART2_CLK;
+      clkname = LPUART1_CLK;
     }
   else
 #endif
diff --git a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c
index 9170fb9ef5c..86f536cb77d 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c
@@ -153,7 +153,7 @@ s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk)
     * and the clock gate.
     */
 
-   regval =  PCC_PCS(pclk->clksrc) | PCC_PCD( pclk->divider);
+   regval =  PCC_PCS(pclk->clksrc) | PCC_PCD(pclk->divider);
 
    if (pclk->frac == MULTIPLY_BY_TWO)
      {
@@ -360,7 +360,7 @@ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency)
                   freq = s32k1xx_get_pclkfreq_divided(clkname, SCG_ASYNC_CLOCK_DIV1);
                 }
 
-              if ((g_periph_features[clkname] & HAS_PROTOCOL_CLOCK_FROM_ASYNC2) != 0U)
+              if ((g_periph_features[clkname] & HAS_PROTOCOL_CLOCK_FROM_ASYNC2) != 0)
                 {
                   /* Check whether the functional clock is clocked */
 
diff --git a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h
index 642281592ad..bd9324ac0df 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h
@@ -91,10 +91,12 @@
 #define CLK_SRC_SIRC                   2  /* SCGIRCLK - Slow IRC Clock */
 #define CLK_SRC_FIRC                   3  /* SCGFIRCLK - Fast IRC Clock */
 #define CLK_SRC_SPLL                   6  /* SCGPCLK System PLL clock */
+
 #define CLK_SRC_SOSC_DIV1              1  /* OSCCLK - System Oscillator Bus Clock */
 #define CLK_SRC_SIRC_DIV1              2  /* SCGIRCLK - Slow IRC Clock */
 #define CLK_SRC_FIRC_DIV1              3  /* SCGFIRCLK - Fast IRC Clock */
 #define CLK_SRC_SPLL_DIV1              6  /* SCGPCLK System PLL clock */
+
 #define CLK_SRC_SOSC_DIV2              1  /* OSCCLK - System Oscillator Bus Clock */
 #define CLK_SRC_SIRC_DIV2              2  /* SCGIRCLK - Slow IRC Clock */
 #define CLK_SRC_FIRC_DIV2              3  /* SCGFIRCLK - Fast IRC Clock */
@@ -175,29 +177,17 @@ enum peripheral_clock_frac_e
   MULTIPLY_BY_TWO          = 1         /* Fractional value is one */
 };
 
-enum peripheral_clock_divider_e
-{
-  DIVIDE_BY_ONE            = 0,        /* Divide by 1 (pass-through, no clock divide) */
-  DIVIDE_BY_TWO            = 1,        /* Divide by 2 */
-  DIVIDE_BY_THREE          = 2,        /* Divide by 3 */
-  DIVIDE_BY_FOUR           = 3,        /* Divide by 4 */
-  DIVIDE_BY_FIVE           = 4,        /* Divide by 5 */
-  DIVIDE_BY_SIX            = 5,        /* Divide by 6 */
-  DIVIDE_BY_SEVEN          = 6,        /* Divide by 7 */
-  DIVIDE_BY_EIGTH          = 7         /* Divide by 8 */
-};
-
 struct peripheral_clock_config_s
 {
   /* clkname is the name of the peripheral clock.  It must be one of the values
    * defined in the chip specific xxxxxx_configname.h header file.
    */
 
-  enum clock_names_e clkname;              /* Peripheral clock name */
-  bool clkgate;                            /* Peripheral clock gate */
-  peripheral_clock_source_t clksrc;        /* Peripheral clock source */
-  enum peripheral_clock_frac_e frac;       /* Peripheral clock fractional value */
-  enum peripheral_clock_divider_e divider; /* Peripheral clock divider value */
+  enum clock_names_e clkname;          /* Peripheral clock name */
+  bool clkgate;                        /* Peripheral clock gate */
+  peripheral_clock_source_t clksrc;    /* Peripheral clock source */
+  enum peripheral_clock_frac_e frac;   /* Peripheral clock fractional value */
+  uint8_t divider;                     /* Peripheral clock divider, range 1..8 */
 };
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c
index 6ba9d9f1b1f..709b7b3864f 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.c
@@ -102,7 +102,7 @@
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_FEATURES
-#  define showprogress(c) up_lowputc(c)
+#  define showprogress(c) s32k1xx_lowputc(c)
 #else
 #  define showprogress(c)
 #endif
@@ -272,34 +272,25 @@ static inline void s32k1xx_mpu_config(void)
 
 void __start(void)
 {
+#ifdef CONFIG_BOOT_RUNFROMFLASH
   const uint32_t *src;
+#endif
   uint32_t *dest;
 
   /* Make sure that interrupts are disabled */
 
   __asm__ __volatile__ ("\tcpsid  i\n");
 
-  /* Configure the clocking and the console uart so that we can get debug
-   * output as soon as possible.  NOTE: That this logic must not assume that
-   * .bss or .data have been initialized.
-   */
-
-  DEBUGVERIFY(s32k1xx_clockconfig(&g_initial_clkconfig));
-  s32k1xx_lowsetup();
-  showprogress('A');
-
 #ifdef CONFIG_S32K1XX_WDT_DISABLE
   /* Disable the watchdog timer */
 
   s32k1xx_wdog_disable();
-  showprogress('B');
 #endif
 
 #ifdef CONFIG_S32K1XX_HAVE_LMEM
   /* Initialize the cache (if supported) */
 
   s32k1xx_cache_config();
-  showprogress('C');
 #endif
 
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
@@ -311,8 +302,7 @@ void __start(void)
       *dest++ = 0;
     }
 
-  showprogress('D');
-
+#ifdef CONFIG_BOOT_RUNFROMFLASH
   /* Move the initialized data section from his temporary holding spot in
    * FLASH into the correct place in SRAM.  The correct place in SRAM is
    * give by _sdata and _edata.  The temporary location is in FLASH at the
@@ -323,19 +313,27 @@ void __start(void)
     {
       *dest++ = *src++;
     }
+#endif
 
-  showprogress('E');
+  /* Configure the clocking and the console uart so that we can get debug
+   * output as soon as possible.  NOTE: That this logic must not assume that
+   * .bss or .data have been initialized.
+   */
+
+  DEBUGVERIFY(s32k1xx_clockconfig(&g_initial_clkconfig));
+  s32k1xx_lowsetup();
+  showprogress('B');
 
   /* Initialize the FPU (if configured) */
 
   s32k1xx_fpu_config();
-  showprogress('F');
+  showprogress('C');
 
 #if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
   /* Enable all MPU bus masters */
 
   s32k1xx_mpu_config();
-  showprogress('G');
+  showprogress('D');
 }
 #endif
 
@@ -344,7 +342,7 @@ void __start(void)
 #ifdef USE_EARLYSERIALINIT
   s32k1xx_earlyserialinit();
 #endif
-  showprogress('H');
+  showprogress('E');
 
   /* For the case of the separate user-/kernel-space build, perform whatever
    * platform specific initialization of the user memory is required.
@@ -354,13 +352,13 @@ void __start(void)
 
 #ifdef CONFIG_BUILD_PROTECTED
   s32k1xx_userspace();
-  showprogress('I');
+  showprogress('F');
 #endif
 
-  /* Initialize onboard resources */
+  /* Initialize on-board resources */
 
   s32k1xx_board_initialize();
-  showprogress('J');
+  showprogress('G');
 
   /* Then start NuttX */
 
diff --git a/arch/arm/src/s32k1xx/s32k1xx_wdog.h b/arch/arm/src/s32k1xx/s32k1xx_wdog.h
index 63c58137b44..f4e4b41938b 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_wdog.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_wdog.h
@@ -93,8 +93,8 @@ static inline void s32k1xx_wdog_disable(void)
    * update enable, watchdog disabled.
    */
 
-  regval = (WDOG_CS_CMD32EN | WDOG_CS_CLK_LPOCLK |WDOG_CS_UPDATE);
-  putreg32(regval, S32K1XX_WDOG_CNT);
+  regval = (WDOG_CS_CMD32EN | WDOG_CS_CLK_LPOCLK | WDOG_CS_UPDATE);
+  putreg32(regval, S32K1XX_WDOG_CS);
 
   /* Configure timeout to the maximum: */
 
diff --git a/boards/arm/s32k1xx/s32k118evb/README.txt b/boards/arm/s32k1xx/s32k118evb/README.txt
index 66940933a71..022b8e46870 100644
--- a/boards/arm/s32k1xx/s32k118evb/README.txt
+++ b/boards/arm/s32k1xx/s32k118evb/README.txt
@@ -9,6 +9,7 @@ Contents
   o Status
   o Serial Console
   o LEDs and Buttons
+  o OpenSDA Notes
   o Configurations
 
 Status
@@ -21,6 +22,12 @@ Status
     are interested in assisting with the bring-up.
   2019-08-17:  The port is code complete.  It compiles with no errors or
     warnings but is untested.  Still waiting for hardware.
+  2019-08-20:  I have the board and started the debug.  However, the
+    very first image that I wrote to FLASH seems to have "bricked" the
+    board.  I believe that the S32K118 resets into a bad state and
+    cannot interface with the OpenSDA, effectively cutting it off from
+    the world.  I will continuing the bring-up using the S32K146EVB
+    where I can run from SRAM for the initial bring-up.
 
 Serial Console
 ==============
@@ -30,6 +37,9 @@ Serial Console
     OpenSDA UART TX  PTB1(LPUART0_TX)
     OpenSDA UART RX  PTB0(LPUART0_RX)
 
+  USB drivers for the PEMIcro CDC Serial port are available here:
+  http://www.pemicro.com/opensda/
+
 LEDs and Buttons
 ================
 
@@ -74,6 +84,18 @@ LEDs and Buttons
     SW2  PTD3
     SW3  PTD5
 
+OpenSDA Notes
+=============
+
+  - USB drivers for the PEMIcro CDC Serial port are available here:
+    http://www.pemicro.com/opensda/
+
+  - The drag'n'drog interface expects files in .srec format.
+
+  - Using Segger J-Link:  Easy... but remember to use the SWD connector J14
+    near the touch electrodes and not the OpenSDA connector near the OpenSDA
+    USB connector J7.
+
 Configurations
 ==============
 
diff --git a/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig
index 3cfecc83c4b..6a55b85bd2b 100644
--- a/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/s32k118evb/configs/nsh/defconfig
@@ -24,14 +24,13 @@ CONFIG_BOARD_LOOPSPERMSEC=2988
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_HOST_WINDOWS=y
-CONFIG_INTELHEX_BINARY=y
 CONFIG_LPUART0_RXBUFSIZE=64
 CONFIG_LPUART0_SERIAL_CONSOLE=y
 CONFIG_LPUART0_TXBUFSIZE=64
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_SMALL=y
+CONFIG_MOTOROLA_SREC=y
 CONFIG_NFILE_DESCRIPTORS=6
 CONFIG_NFILE_STREAMS=6
 CONFIG_NPTHREAD_KEYS=0
@@ -50,7 +49,6 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PTHREAD_STACK_DEFAULT=1536
 CONFIG_RAM_SIZE=23552
 CONFIG_RAM_START=0x1ffffc00
-CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_S32K1XX_LPUART0=y
 CONFIG_SCHED_WAITPID=y
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c b/boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
index a8f78ae35ea..0a77b8612d5 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
@@ -100,7 +100,6 @@ const struct clock_configuration_s g_initial_clkconfig =
     },
     .sosc               =
     {
-      .freq             = 40000000,                  /* Frequency */
       .mode             = SCG_SOSC_MONITOR_DISABLE,  /* SOSCCM */
       .gain             = SCG_SOSC_GAIN_LOW,         /* HGO */
       .range            = SCG_SOSC_RANGE_HIGH,       /* RANGE */
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c b/boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
index 1e576c01d0e..f8ba47acace 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
@@ -84,69 +84,69 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC_DIV2,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = DMAMUX0_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPTMR0_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC_DIV2,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPUART0_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC_DIV2,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPUART1_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC_DIV2,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTA_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTB_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTC_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTD_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTE_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
 };
diff --git a/boards/arm/s32k1xx/s32k146evb/README.txt b/boards/arm/s32k1xx/s32k146evb/README.txt
index 9e66993668d..fd674ba8f1d 100644
--- a/boards/arm/s32k1xx/s32k146evb/README.txt
+++ b/boards/arm/s32k1xx/s32k146evb/README.txt
@@ -9,17 +9,21 @@ Contents
   o Status
   o Serial Console
   o LEDs and Buttons
+  o OpenSDA Notes
   o Configurations
 
 Status
 ======
 
-  2019-08-148  Configuration created but entirely untested.  This
+  2019-08-18:  Configuration created but entirely untested.  This
     configuration is intended, initially, to verify s32k14x architecture
-    support.  The configuration builds and linkes without error but has
+    support.  The configuration builds and links without error but has
     not yet been tested.  This is VERY much a work in progress and you
     should not use this configuration unless you are interested in
     assisting with the bring-up.
+  2019-08-20:  Initial testing, I am running out of SRAM to avoid the
+    brickage problems I had with the S32K118EVB (i.e., with
+    CONFIG_BOOT_RUNFROMISRAM=y)
 
 Serial Console
 ==============
@@ -29,6 +33,9 @@ Serial Console
     OpenSDA UART TX  PTC7 (LPUART1_TX)
     OpenSDA UART RX  PTC6 (LPUART1_RX)
 
+  USB drivers for the PEMIcro CDC Serial port are available here:
+  http://www.pemicro.com/opensda/
+
 LEDs and Buttons
 ================
 
@@ -73,6 +80,18 @@ LEDs and Buttons
     SW2  PTC12
     SW3  PTC13
 
+OpenSDA Notes
+=============
+
+  - USB drivers for the PEMIcro CDC Serial port are available here:
+    http://www.pemicro.com/opensda/
+
+  - The drag'n'drog interface expects files in .srec format.
+
+  - Using Segger J-Link:  Easy... but remember to use the SWD J14 connector
+    in the center of the board and not the OpenSDA connector closer to the
+    OpenSDA USB connector J7.
+
 Configurations
 ==============
 
diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
index caa2e72b411..e887ae4d23e 100644
--- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
@@ -25,13 +25,13 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
 CONFIG_HOST_WINDOWS=y
-CONFIG_INTELHEX_BINARY=y
 CONFIG_LPUART1_RXBUFSIZE=64
 CONFIG_LPUART1_SERIAL_CONSOLE=y
 CONFIG_LPUART1_TXBUFSIZE=64
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_SMALL=y
+CONFIG_MOTOROLA_SREC=y
 CONFIG_NFILE_DESCRIPTORS=6
 CONFIG_NFILE_STREAMS=6
 CONFIG_NPTHREAD_KEYS=0
@@ -50,7 +50,6 @@ CONFIG_PREALLOC_WDOGS=4
 CONFIG_PTHREAD_STACK_DEFAULT=1536
 CONFIG_RAM_SIZE=23552
 CONFIG_RAM_START=0x1ffffc00
-CONFIG_RAW_BINARY=y
 CONFIG_RR_INTERVAL=200
 CONFIG_S32K1XX_LPUART1=y
 CONFIG_SCHED_WAITPID=y
diff --git a/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs
index 7ba2273f761..5216391216f 100644
--- a/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs
+++ b/boards/arm/s32k1xx/s32k146evb/scripts/Make.defs
@@ -37,8 +37,13 @@ include ${TOPDIR}/.config
 include ${TOPDIR}/tools/Config.mk
 include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
 
-LDSCRIPT = flash.ld
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
 
+$(warning, LDSCRIPT is $(LDSCRIPT))
 ifeq ($(WINTOOL),y)
   # Windows-native toolchains
   ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
@@ -50,6 +55,8 @@ else
   ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
   ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
 endif
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
 
 CC = $(CROSSDEV)gcc
 CXX = $(CROSSDEV)g++
diff --git a/boards/arm/s32k1xx/s32k146evb/scripts/sram.ld b/boards/arm/s32k1xx/s32k146evb/scripts/sram.ld
new file mode 100644
index 00000000000..c8703553d44
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k146evb/scripts/sram.ld
@@ -0,0 +1,131 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k146evb/scripts/sram.ld
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and
+ * 124Kb of SRAM beginning at address 0x1fff:fc00 (plus 4Kb of FlexRAM)
+ *
+ * The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
+ * implemented such that the SRAM_L and SRAM_U ranges form a contiguous
+ * block in the memory map
+ *
+ *   SRAM_L 1fff0000 - 1fffffff 64Kb
+ *   SRAM_U 20000000 - 2000efff 60Kb
+ */
+
+MEMORY
+{
+  flash (rx)  : ORIGIN = 0x00000000, LENGTH = 1M
+  sram  (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+
+SECTIONS
+{
+  .text :
+  {
+    _stext = ABSOLUTE(.);
+    *(.vectors)
+    *(.text .text.*)
+    *(.fixup)
+    *(.gnu.warning)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.t.*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.got)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.r.*)
+    _etext = ABSOLUTE(.);
+  } > sram
+
+  . = ALIGN(4);
+  .init_section :
+  {
+    _sinit = ABSOLUTE(.);
+    *(.init_array .init_array.*)
+    _einit = ABSOLUTE(.);
+  } > sram
+
+  . = ALIGN(4);
+  .ARM.extab :
+  {
+    *(.ARM.extab*)
+  } >sram
+
+  . = ALIGN(4);
+  __exidx_start = ABSOLUTE(.);
+  .ARM.exidx :
+  {
+    *(.ARM.exidx*)
+  } >sram
+  __exidx_end = ABSOLUTE(.);
+
+  . = ALIGN(4);
+  .data :
+  {
+    _sdata = ABSOLUTE(.);
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    CONSTRUCTORS
+    _edata = ABSOLUTE(.);
+  } > sram
+
+  .bss :
+  {
+    _sbss = ABSOLUTE(.);
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    _ebss = ABSOLUTE(.);
+  } > sram
+
+  /* Stabs debugging sections. */
+
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  .debug_abbrev 0 : { *(.debug_abbrev) }
+  .debug_info 0 : { *(.debug_info) }
+  .debug_line 0 : { *(.debug_line) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c b/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
index 7d41552f606..d9dc500af8f 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
+++ b/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
@@ -100,7 +100,6 @@ const struct clock_configuration_s g_initial_clkconfig =
     },
     .sosc               =
     {
-      .freq             = 8000000,                   /* Frequency */
       .mode             = SCG_SOSC_MONITOR_DISABLE,  /* SOSCCM */
       .gain             = SCG_SOSC_GAIN_LOW,         /* HGO */
       .range            = SCG_SOSC_RANGE_MID,        /* RANGE */
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c b/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c
index 450454a8fce..bfb8da43a58 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c
+++ b/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c
@@ -84,76 +84,76 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
     .clkgate    = true,
     .clksrc     = CLK_SRC_FIRC,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = ADC1_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_FIRC,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPTMR0_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPUART0_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPUART1_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = LPUART2_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_SIRC,
-    .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .frac       = 1,
+    .divider    = 1,
   },
   {
     .clkname    = PORTA_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTB_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTC_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTD_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   },
   {
     .clkname    = PORTE_CLK,
     .clkgate    = true,
     .clksrc     = CLK_SRC_OFF,
     .frac       = MULTIPLY_BY_ONE,
-    .divider    = DIVIDE_BY_ONE,
+    .divider    = 1,
   }
 };