mirror of
https://github.com/apache/nuttx.git
synced 2026-05-23 23:05:39 +08:00
Remove nr5m100(risc-v) arch and board source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
committed by
Brennan Ashton
Brennan Ashton
parent
f71c5e5324
commit
c54d617f2c
@@ -3020,13 +3020,6 @@ RISC-V
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RISC-V Architectural Support. Basic support for the RISC-V architecture
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was contributed by Ken Pettit in NuttX-7.19.
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NEXT RISC-V NR5Mxx
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------------------
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This support is for a custom NEXT RISC-V NR5Mxx (RV32IM). The initial release
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is *thin* but a great starting point for anyone interested in RISC-V development with
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NuttX.
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GreenWaves GAP8
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---------------
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@@ -68,7 +68,6 @@ from board-to-board. Follow the links for the details:
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-
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- :ref:`introduction/detailed_support:RISC-V` (2)
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- :ref:`introduction/detailed_support:NEXT RISC-V NR5Mxx` (1)
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- :ref:`introduction/detailed_support:GreenWaves GAP8` (1)
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- :ref:`introduction/detailed_support:LiteX on Arty A7` (1)
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@@ -225,8 +225,6 @@ Current architecture/chip directories are summarized below:
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- ``arch/renesas``: This directory is the home for various
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Renesas architectures, currently only the M16C and vererable
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SuperH-1 architectures.
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- ``arch/risc-v``: This directory supports the RISC-V NR5
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architecture.
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- ``arch/xtensa``: This directory supports the Xtensa LX6
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architecture as used by the ESP32.
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- ``arch/z16f``: Zilog z16f Microcontroller.
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@@ -2302,11 +2302,8 @@ Below is a guide to the available README files in the NuttX source tree:
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| | `- us7032evb1/
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| | `- README.txt
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| |- risc-v/
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| | |- gap8/
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| | | `- gapuino/
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| | | `- README.txt
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| | `-nr5m100/
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| | `- nr5m100-nexys4/
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| | `- gap8/
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| | `- gapuino/
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| | `- README.txt
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| |- sim/
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| | `- sim/
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@@ -258,7 +258,6 @@ arch/risc-v
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arch/risc-v/include/gap8 and arch/risc-v/src/gap8
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arch/risc-v/include/k210 and arch/risc-v/src/k210
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arch/risc-v/include/litex and arch/risc-v/src/litex
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arch/risc-v/include/nr5m100 and arch/risc-v/src/nr5m100
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arch/risc-v/include/rv32im and arch/risc-v/src/rv32im
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arch/risc-v/include/rv64gc and arch/risc-v/src/rv64gc
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+1
-21
@@ -8,7 +8,7 @@ comment "RISC-V Options"
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choice
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prompt "RISC-V chip selection"
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default ARCH_CHIP_NR5
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default ARCH_CHIP_RISCV_CUSTOM
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config ARCH_CHIP_FE310
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bool "SiFive FE310"
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@@ -31,12 +31,6 @@ config ARCH_CHIP_LITEX
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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config ARCH_CHIP_NR5
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bool "NEXT NanoRisc5"
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select ARCH_RV32IM
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---help---
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NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores).
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config ARCH_CHIP_GAP8
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bool "GreenwavesTechnologies GAP8"
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select ARCH_RV32IM
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@@ -101,22 +95,11 @@ config ARCH_CHIP
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default "fe310" if ARCH_CHIP_FE310
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default "k210" if ARCH_CHIP_K210
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default "litex" if ARCH_CHIP_LITEX
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default "nr5m100" if ARCH_CHIP_NR5
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default "gap8" if ARCH_CHIP_GAP8
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default "bl602" if ARCH_CHIP_BL602
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default "esp32c3" if ARCH_CHIP_ESP32C3
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default "c906" if ARCH_CHIP_C906
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config NR5_MPU
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bool "MPU support"
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default n
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depends on ARCH_HAVE_MPU
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select ARCH_USE_MPU
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---help---
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Build in support for the RISC-V Memory Protection Unit (MPU).
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Check your chip specifications first; not all RISC-V architectures
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support the MPU.
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if ARCH_RV32IM
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source arch/risc-v/src/rv32im/Kconfig
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endif
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@@ -132,9 +115,6 @@ endif
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if ARCH_CHIP_LITEX
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source arch/risc-v/src/litex/Kconfig
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endif
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if ARCH_CHIP_NR5
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source arch/risc-v/src/nr5m100/Kconfig
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endif
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if ARCH_CHIP_GAP8
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source arch/risc-v/src/gap8/Kconfig
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endif
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@@ -1,56 +0,0 @@
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/****************************************************************************
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* arch/risc-v/include/nr5m100/chip.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H
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#define __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H */
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@@ -1,55 +0,0 @@
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/****************************************************************************
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* arch/risc-v/include/nr5m100/irq.h
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* include/arch/nr5m100/irq.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
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#define __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#if defined(CONFIG_NR5_NR5M1XX)
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# include <arch/chip/nr5m1xx_irq.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NR5_IRQ_TRAP 0
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#define EPIC_STATUS_PRI_MASK 0x001C
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#define EPIC_STATUS_INT_PRI_MASK 0x01C0
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#define EPIC_STATUS_INT_PRI1 0x0040
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#endif /* __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H */
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@@ -1,66 +0,0 @@
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/****************************************************************************
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* arch/risc-v/include/nr5m100/nr5m1xx_irq.h
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* include/arch/nr5m100/nr5m1xx_irq.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H
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#define __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NR5_IRQ_SYSTICK 1
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#define NR5_IRQ_TIMER 2
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#define NR5_IRQ_SOFTWARE 3
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#define NR5_IRQ_DEBUG 4
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#define NR5_IRQ_UART1_RX 5
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#define NR5_IRQ_UART1_TX 6
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#define NR5_IRQ_TIMER1_A 7
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#define NR5_IRQ_TIMER1_B 8
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#define NR5_IRQ_TIMER2_A 9
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#define NR5_IRQ_TIMER2_B 10
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#define NR_IRQS 11
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H */
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@@ -49,7 +49,7 @@
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/nr5m100/irq.h>
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#include <arch/gap8/irq.h>
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#include "sched/sched.h"
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#include "riscv_internal.h"
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@@ -1,120 +0,0 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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comment "NanoRisc5 Configuration Options"
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choice
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prompt "NR5 Chip Selection"
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default ARCH_CHIP_NR5M100
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depends on ARCH_CHIP_NR5
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config ARCH_CHIP_NR5M100
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bool "NR5M100"
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select NR5_HAVE_UART1
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select NR5_HAVE_GPIOA
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select NR5_HAVE_GPIOB
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select NR5_HAVE_GPIOC
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---help---
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NanoRisc5, RV32IM 128K PROGRAM SRAM, 128K DATA SRAM
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endchoice
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config NR5_NR5M100
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bool
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default y
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select NR5_NR5M1XX
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select NR5_HAVE_UART1
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select NR5_HAVE_TIMER1
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config NR5_NR5M1XX
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bool
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default n
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config NR5_EPIC
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bool "Has Embedded Priority Interrupt Controller (EPIC)"
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---help---
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NanoRisc5 core can have either single vector interrupts or priority
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encoded interrupts. Selects if the core was compiled with EPIC.
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menu "NR5 Peripheral Support"
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# These "hidden" settings determine whether a peripheral option is available
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# for the selected MCU
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config NR5_HAVE_UART1
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bool
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default n
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config NR5_HAVE_TIMER1
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bool
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default n
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config NR5_HAVE_TIM2
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bool
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default n
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config NR5_HAVE_I2C1
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bool
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default n
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config NR5_HAVE_SPI1
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bool
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default n
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# These are the peripheral selections proper
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config NR5_I2C1
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bool "I2C1"
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default n
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select NR5_I2C
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config NR5_SPI1
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bool "SPI1"
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default n
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select SPI
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select NR5_SPI
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config NR5_TIMER1
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bool "TIMER1"
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default n
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depends on NR5_HAVE_TIMER1
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config NR5_TIMER2
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bool "TIMER2"
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default n
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config NR5_UART1
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bool "UART1"
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default n
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select ARCH_HAVE_UART1
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select ARCH_HAVE_SERIAL_TERMIOS
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select NR5_UART
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endmenu
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||||
|
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config NR5_SPI
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bool
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config NR5_I2C
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bool
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|
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config NR5_UART
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bool
|
||||
|
||||
config NR5_UART_RX_BUF_SIZE
|
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int "UART RX Buffer size"
|
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default 64
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||||
depends on NR5_UART
|
||||
---help---
|
||||
Size of RX buffers for NR5 UARTs
|
||||
|
||||
config NR5_UART_TX_BUF_SIZE
|
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int "UART TX Buffer size"
|
||||
default 64
|
||||
depends on NR5_UART
|
||||
---help---
|
||||
Size of TX buffers for NR5 UARTs
|
||||
@@ -1,77 +0,0 @@
|
||||
############################################################################
|
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# arch/risc-v/src/nr5m100/Make.defs
|
||||
#
|
||||
# Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
# Author: Ken Pettit <pettitkd@gmail.com>
|
||||
#
|
||||
# # Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
# Specify our HEAD assembly file. This will be linked as
|
||||
# the first object file, so it will appear at address 0
|
||||
HEAD_ASRC = nr5_vectors.S
|
||||
|
||||
# Specify our general Assembly files
|
||||
CHIP_ASRCS = nr5_head.S nr5_csr.S riscv_syscall.S
|
||||
|
||||
ifeq ($(CONFIG_ARCH_SETJMP_H),y)
|
||||
CMN_ASRCS += riscv_setjmp.S
|
||||
endif
|
||||
|
||||
# If we are compiling the NELIB library, then specify it
|
||||
# in AFLAGS so we can change up our startup behavior
|
||||
ifeq ($(CONFIG_LIB_NEWLIB),y)
|
||||
AFLAGS += -DCONFIG_LIB_NEWLIB
|
||||
endif
|
||||
|
||||
# Override the arch to enable hardware MUL during assembly.
|
||||
# This is to support our hardware mul test. For that test,
|
||||
# we have to disable hardware mul for C code so the soft
|
||||
# math libs will be used to compare software mul vs hw mul.
|
||||
# But hw mul must be enabled to compile the .S file, or we
|
||||
# will get an illegal instruction error.
|
||||
ASARCHCPUFLAGS += -march=RV32IMXcustom
|
||||
|
||||
# Specify C code within the common directory to be included
|
||||
CMN_CSRCS += riscv_initialize.c riscv_swint.c
|
||||
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_idle.c
|
||||
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
|
||||
CMN_CSRCS += riscv_interruptcontext.c riscv_releasepending.c riscv_reprioritizertr.c
|
||||
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c nr5_schedulesigaction.c riscv_sigdeliver.c
|
||||
CMN_CSRCS += riscv_unblocktask.c riscv_usestack.c riscv_copyfullstate.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
|
||||
CMN_CSRCS += riscv_vfork.c
|
||||
endif
|
||||
|
||||
# Specify our C code within this directory to be included
|
||||
CHIP_CSRCS = nr5_init.c nr5_arch.c
|
||||
CHIP_CSRCS += nr5_lowputc.c nr5_allocateheap.c nr5_serial.c
|
||||
CHIP_CSRCS += nr5_timerisr.c nr5_irq.c nr5_irq_dispatch.c
|
||||
|
||||
ifeq ($(CONFIG_TIMER),y)
|
||||
CHIP_CSRCS += nr5_tim_lowerhalf.c
|
||||
endif
|
||||
@@ -1,54 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/chip.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the chip memory map. */
|
||||
|
||||
#include "nr5_memorymap.h"
|
||||
|
||||
/* Include our custom access routines for ISR masking, priority */
|
||||
|
||||
#include "nr5_csr.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_H */
|
||||
@@ -1,41 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/hardware/nr5m1xx_epic.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H
|
||||
#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H
|
||||
|
||||
#define NR5_EPIC_PRI1_REG 0x7E1
|
||||
#define NR5_EPIC_PRI2_REG 0x7E2
|
||||
#define NR5_EPIC_PRI3_REG 0x7E3
|
||||
#define NR5_EPIC_STAT_REG 0x7E4
|
||||
|
||||
#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H */
|
||||
@@ -1,56 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/hardware/nr5m1xx_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* BOOT ROM, SRAM, PERIPHERALS ******************************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 384Kb SRAM */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x4fffffff: Peripheral block */
|
||||
|
||||
/* Register Base Address ************************************************************/
|
||||
|
||||
#define NR5_UART1_BASE 0x40000000 /* 0x40000000 - 0x40000fff: UART0 */
|
||||
#define NR5_GPIO1_BASE 0x40001000 /* 0x40001000 - 0x40001fff: GPIO1 */
|
||||
#define NR5_GPIO2_BASE 0x40002000 /* 0x40002000 - 0x40002fff: GPIO2 */
|
||||
#define NR5_GPIO3_BASE 0x40003000 /* 0x40003000 - 0x40003fff: GPIO3 */
|
||||
#define NR5_TIMER1_BASE 0x40004000 /* 0x40004000 - 0x40004fff: TIMER0 timer */
|
||||
#define NR5_TIMER2_BASE 0x40005000 /* 0x40005000 - 0x40005fff: TIMER1 timer */
|
||||
#define NR5_EXTMEM_BASE 0x40006000 /* 0x40006000 - 0x40006fff: EXTMEM Controller*/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H */
|
||||
@@ -1,193 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/hardware/nr5m1xx_timer.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
|
||||
#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "nr5m1xx_memorymap.h"
|
||||
|
||||
/* The timers used in the NR5M100 are functionally equivalent to
|
||||
* Timer A in the MSP430. The hardware peripheral in the FPGA uses the BSD
|
||||
* licensed RTL code from the OpenMSP430 project on opencores.org.
|
||||
*/
|
||||
|
||||
/* TimerA offset definitions */
|
||||
|
||||
#define NR5_TIMERA_TACTL_OFFSET 0x00
|
||||
#define NR5_TIMERA_TAR_OFFSET 0x04
|
||||
#define NR5_TIMERA_TACCTL0_OFFSET 0x08
|
||||
#define NR5_TIMERA_TACCR0_OFFSET 0x0C
|
||||
#define NR5_TIMERA_TACCTL1_OFFSET 0x10
|
||||
#define NR5_TIMERA_TACCR1_OFFSET 0x14
|
||||
#define NR5_TIMERA_TACCTL2_OFFSET 0x18
|
||||
#define NR5_TIMERA_TACCR2_OFFSET 0x1C
|
||||
#define NR5_TIMERA_TAIV_OFFSET 0x20
|
||||
|
||||
/* Timer 1 address definitions */
|
||||
|
||||
#ifdef CONFIG_NR5_TIMER1
|
||||
#define NR5_TIMER1_TACTL_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACTL_OFFSET)
|
||||
#define NR5_TIMER1_TAR_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAR_OFFSET)
|
||||
#define NR5_TIMER1_TACCTL0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL0_OFFSET)
|
||||
#define NR5_TIMER1_TACCR0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR0_OFFSET)
|
||||
#define NR5_TIMER1_TACCTL1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL1_OFFSET)
|
||||
#define NR5_TIMER1_TACCR1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR1_OFFSET)
|
||||
#define NR5_TIMER1_TACCTL2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL2_OFFSET)
|
||||
#define NR5_TIMER1_TACCR2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR2_OFFSET)
|
||||
#define NR5_TIMER1_TAIV_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Timer 2 address definitions */
|
||||
|
||||
#ifdef CONFIG_NR5_TIMER2
|
||||
#define NR5_TIMER2_TACTL_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACTL_OFFSET)
|
||||
#define NR5_TIMER2_TAR_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAR_OFFSET)
|
||||
#define NR5_TIMER2_TACCTL0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL0_OFFSET)
|
||||
#define NR5_TIMER2_TACCR0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR0_OFFSET)
|
||||
#define NR5_TIMER2_TACCTL1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL1_OFFSET)
|
||||
#define NR5_TIMER2_TACCR1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR1_OFFSET)
|
||||
#define NR5_TIMER2_TACCTL2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL2_OFFSET)
|
||||
#define NR5_TIMER2_TACCR2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR2_OFFSET)
|
||||
#define NR5_TIMER2_TAIV_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Timer 3 address definitions */
|
||||
|
||||
#ifdef CONFIG_NR5_TIMER3
|
||||
#define NR5_TIMER3_TACTL_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACTL_OFFSET)
|
||||
#define NR5_TIMER3_TAR_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAR_OFFSET)
|
||||
#define NR5_TIMER3_TACCTL0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL0_OFFSET)
|
||||
#define NR5_TIMER3_TACCR0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR0_OFFSET)
|
||||
#define NR5_TIMER3_TACCTL1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL1_OFFSET)
|
||||
#define NR5_TIMER3_TACCR1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR1_OFFSET)
|
||||
#define NR5_TIMER3_TACCTL2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL2_OFFSET)
|
||||
#define NR5_TIMER3_TACCR2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR2_OFFSET)
|
||||
#define NR5_TIMER3_TAIV_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Timer 4 address definitions */
|
||||
|
||||
#ifdef CONFIG_NR5_TIMER4
|
||||
#define NR5_TIMER4_TACTL_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACTL_OFFSET)
|
||||
#define NR5_TIMER4_TAR_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAR_OFFSET)
|
||||
#define NR5_TIMER4_TACCTL0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL0_OFFSET)
|
||||
#define NR5_TIMER4_TACCR0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR0_OFFSET)
|
||||
#define NR5_TIMER4_TACCTL1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL1_OFFSET)
|
||||
#define NR5_TIMER4_TACCR1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR1_OFFSET)
|
||||
#define NR5_TIMER4_TACCTL2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL2_OFFSET)
|
||||
#define NR5_TIMER4_TACCR2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR2_OFFSET)
|
||||
#define NR5_TIMER4_TAIV_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Timer 5 address definitions */
|
||||
|
||||
#ifdef CONFIG_NR5_TIMER5
|
||||
#define NR5_TIMER5_TACTL_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACTL_OFFSET)
|
||||
#define NR5_TIMER5_TAR_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAR_OFFSET)
|
||||
#define NR5_TIMER5_TACCTL0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL0_OFFSET)
|
||||
#define NR5_TIMER5_TACCR0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR0_OFFSET)
|
||||
#define NR5_TIMER5_TACCTL1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL1_OFFSET)
|
||||
#define NR5_TIMER5_TACCR1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR1_OFFSET)
|
||||
#define NR5_TIMER5_TACCTL2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL2_OFFSET)
|
||||
#define NR5_TIMER5_TACCR2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR2_OFFSET)
|
||||
#define NR5_TIMER5_TAIV_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* Control register TACTL Bit definitions */
|
||||
|
||||
#define TIMERA_TACTL_TAIFG (1 << 0) /* Bit 0: Interrupt Pending Flag */
|
||||
#define TIMERA_TACTL_TAIE (1 << 1) /* Bit 1: Interrupt Enable */
|
||||
#define TIMERA_TACTL_TACLR (1 << 2) /* Bit 2: TAR counter clear */
|
||||
#define TIMERA_TACTL_MC_SHIFT 4 /* Bits 4-5: Mode Control */
|
||||
# define TIMERA_TACTL_MC_MASK (3 << TIMERA_TACTL_MC_SHIFT)
|
||||
# define TIMERA_TACTL_STOP (0 << TIMERA_TACTL_MC_SHIFT)
|
||||
# define TIMERA_TACTL_UP (1 << TIMERA_TACTL_MC_SHIFT)
|
||||
# define TIMERA_TACTL_CONTINUOUS (2 << TIMERA_TACTL_MC_SHIFT)
|
||||
# define TIMERA_TACTL_UPDOWN (3 << TIMERA_TACTL_MC_SHIFT)
|
||||
#define TIMERA_TACTL_ID_SHIFT 6 /* Bits 6-7: Input Divider */
|
||||
# define TIMERA_TACTL_DIV_1 (0 << TIMERA_TACTL_ID_SHIFT)
|
||||
# define TIMERA_TACTL_DIV_2 (1 << TIMERA_TACTL_ID_SHIFT)
|
||||
# define TIMERA_TACTL_DIV_4 (2 << TIMERA_TACTL_ID_SHIFT)
|
||||
# define TIMERA_TACTL_DIV_8 (3 << TIMERA_TACTL_ID_SHIFT)
|
||||
#define TIMERA_TACTL_TASSEL_SHIFT 8 /* Bits 8-9: Clock Source Select */
|
||||
# define TIMERA_TACTL_MED_CLOCK (0 << TIMERA_TACTL_TASSEL_SHIFT)
|
||||
# define TIMERA_TACTL_SLOW_CLOCK (1 << TIMERA_TACTL_TASSEL_SHIFT)
|
||||
# define TIMERA_TACTL_SYS_CLOCK (2 << TIMERA_TACTL_TASSEL_SHIFT)
|
||||
# define TIMERA_TACTL_EXT_CLOCK (3 << TIMERA_TACTL_TASSEL_SHIFT)
|
||||
#define TIMERA_TACTL_TAPRE_SHIFT 10 /* Bits 10-15: Clock Prescaler */
|
||||
#define TIMERA_TACTL_TAPRE_MASK 0x3F
|
||||
# define TIMERA_TACTL_TAPRE(x) (((x) & TIMERA_TACTL_TAPRE_MASK) << TIMERA_TACTL_TAPRE_SHIFT)
|
||||
|
||||
/* Capture / Compare register bit definitions */
|
||||
|
||||
#define TIMERA_TACCTL_CCIFG (1 << 0) /* Bit 0: Capture/compare interrupt Flag */
|
||||
#define TIMERA_TACCTL_COV (1 << 1) /* Bit 1: Capture overflow */
|
||||
#define TIMERA_TACCTL_OUTVAL (1 << 2) /* Bit 2: Output value */
|
||||
#define TIMERA_TACCTL_CCI (1 << 3) /* Bit 3: Capture/compare input value */
|
||||
#define TIMERA_TACCTL_CCIE (1 << 4) /* Bit 4: Capture/Compare interrupt Enable */
|
||||
#define TIMERA_TACCTL_OUTMOD_SHIFT 5 /* Bits 5-7: Output Mode */
|
||||
# define TIMERA_TACCTL_OUT (0 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_SET (1 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_TOGGLE_RESET (2 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_SET_RESET (3 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_TOGGLE (4 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_RESET (5 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_TOGGLE_SET (6 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
# define TIMERA_TACCTL_RESET_SET (7 << TIMERA_TACCTL_OUTMOD_SHIFT)
|
||||
#define TIMERA_TACCTL_CAP (1 << 8) /* Bit 8: Capture mode select */
|
||||
#define TIMERA_TACCTL_SCCI (1 << 10) /* Bit 10: Synchronized capture input */
|
||||
#define TIMERA_TACCTL_SCS (1 << 11) /* Bit 11: Synchronize capture source */
|
||||
#define TIMERA_TACCTL_CCIS_SHIFT 12 /* Bits 12-13: Capture Input Select */
|
||||
# define TIMERA_TACCTL_CCIS_CCIA (0 << TIMERA_TACCTL_CCIS_SHIFT)
|
||||
# define TIMERA_TACCTL_CCIS_CCIB (1 << TIMERA_TACCTL_CCIS_SHIFT)
|
||||
# define TIMERA_TACCTL_CCIS_GND (2 << TIMERA_TACCTL_CCIS_SHIFT)
|
||||
# define TIMERA_TACCTL_CCIS_VCC (3 << TIMERA_TACCTL_CCIS_SHIFT)
|
||||
#define TIMERA_TACCTL_CM_SHIFT 14 /* Bits 14-15: Capture Mode */
|
||||
# define TIMERA_TACCTL_CM_NO_CAPTURE (0 << TIMERA_TACCTL_SM_SHIFT)
|
||||
# define TIMERA_TACCTL_CM_RISING (1 << TIMERA_TACCTL_SM_SHIFT)
|
||||
# define TIMERA_TACCTL_CM_FALLING (2 << TIMERA_TACCTL_SM_SHIFT)
|
||||
# define TIMERA_TACCTL_CM_BOTH (3 << TIMERA_TACCTL_SM_SHIFT)
|
||||
|
||||
/* Interrupt Vector Register */
|
||||
|
||||
#define TIMERA_TAIV_TAIV_SHIFT 1 /* Bits 1-3: Interrupt Source */
|
||||
# define TIMERA_TAIV_TACCR1 (1 << TIMERA_TAIV_TAIV_SHIFT)
|
||||
# define TIMERA_TAIV_TACCR2 (2 << TIMERA_TAIV_TAIV_SHIFT)
|
||||
# define TIMERA_TAIV_TAIFG (5 << TIMERA_TAIV_TAIV_SHIFT)
|
||||
|
||||
#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H */
|
||||
@@ -1,75 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/hardware/nr5m1xx_uart.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H
|
||||
#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H
|
||||
|
||||
/* The UART in NR5M100 is a very small (i.e. dumb) peripheral. It
|
||||
* only supports the most common mode ever used:
|
||||
*
|
||||
* 8 Data bits
|
||||
* 1 Stop bit
|
||||
* No parity.
|
||||
*
|
||||
* It has a programmable baud rate and RX / TX interrupt capability
|
||||
* and that's about it. The primary goal for the UART is to provide a
|
||||
* debug console to the part.
|
||||
*/
|
||||
|
||||
#define NR5_UART_BAUD_RATE_OFFSET 0x000
|
||||
#define NR5_UART_TX_REG_OFFSET 0x004
|
||||
#define NR5_UART_RX_REG_OFFSET 0x008
|
||||
#define NR5_UART_STATUS_REG_OFFSET 0x00C
|
||||
#define NR5_UART_CTRL_REG_OFFSET 0x010
|
||||
|
||||
#ifdef CONFIG_NR5_UART1
|
||||
# define NR5_UART1_BAUD_RATE_REG (NR5_UART1_BASE+NR5_UART_BAUD_RATE_OFFSET)
|
||||
# define NR5_UART1_TX_REG (NR5_UART1_BASE+NR5_UART_TX_REG_OFFSET)
|
||||
# define NR5_UART1_RX_REG (NR5_UART1_BASE+NR5_UART_RX_REG_OFFSET)
|
||||
# define NR5_UART1_STATUS_REG (NR5_UART1_BASE+NR5_UART_STATUS_REG_OFFSET)
|
||||
# define NR5_UART1_CTRL_REG (NR5_UART1_BASE+NR5_UART_CTRL_REG_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Status Register Bit definitions */
|
||||
|
||||
#define NR5_UART_STATUS_TX_EMPTY 0x01
|
||||
#define NR5_UART_STATUS_RX_AVAIL 0x02
|
||||
#define NR5_UART_STATUS_RX_OVERRUN 0x04
|
||||
#define NR5_UART_RX_IRQ_PENDING 0x08
|
||||
#define NR5_UART_TX_IRQ_PENDING 0x10
|
||||
|
||||
/* Control Register Bit definitions */
|
||||
|
||||
#define NR5_UART_CTRL_ENABLE_RX_IRQ 0x01
|
||||
#define NR5_UART_CTRL_ENABLE_TX_IRQ 0x02
|
||||
|
||||
#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5.h
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Authors: Uros Platise <uros.platise@isotel.eu>
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
* Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_NR5_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include "riscv_internal.h"
|
||||
|
||||
/* Peripherals **********************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
#include "nr5_csr.h"
|
||||
#include "nr5_lowputc.h"
|
||||
#include "nr5_timer.h"
|
||||
#include "nr5_uart.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5_NR5_H */
|
||||
@@ -1,65 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_allocateheap.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: riscv_addregion
|
||||
*
|
||||
* Description:
|
||||
* RAM may be added in non-contiguous chunks. This routine adds all chunks
|
||||
* that may be used for heap.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_MM_REGIONS > 1
|
||||
void riscv_addregion(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_arch.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <string.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include "nr5.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void up_puts(const char *p)
|
||||
{
|
||||
while (*p != 0)
|
||||
up_lowputc(*(p++));
|
||||
up_lowputc('\n');
|
||||
}
|
||||
@@ -1,98 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_config.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/chip/chip.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* UARTs ****************************************************************************/
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART_DEVICE
|
||||
#if defined(CONFIG_NR5_UART1) || defined(CONFIG_NR5_UART2)
|
||||
# define HAVE_UART_DEVICE 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? There should be no more than one defined. It
|
||||
* could be on any UARTn, n=1,.. CHIP_NUARTS
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART1)
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART2)
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# define HAVE_SERIAL_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
# undef HAVE_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */
|
||||
@@ -1,288 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_csr.S
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/*
|
||||
* Provide C level access function to asm only CSR registers
|
||||
*/
|
||||
|
||||
#define ENABLE_QREGS
|
||||
#include "nr5_custom_ops.h"
|
||||
#include "nr5_csr.h"
|
||||
|
||||
.global up_getmisa
|
||||
.global up_getarchid
|
||||
.global up_getimpid
|
||||
.global up_getvendorid
|
||||
.global up_gethartid
|
||||
.global up_getepicprimask
|
||||
.global up_setepicprimask
|
||||
.global up_setepicstat
|
||||
.global up_setsystick
|
||||
.global up_setpri1bit
|
||||
.global up_clearpri1bit
|
||||
.global up_setpri2bit
|
||||
.global up_clearpri2bit
|
||||
.global up_setpri3bit
|
||||
.global up_clearpri3bit
|
||||
.global up_setirqmaskbit
|
||||
.global up_clearirqmaskbit
|
||||
.global up_disableints
|
||||
.global up_enableints
|
||||
.global up_getq0
|
||||
.global up_getq1
|
||||
.global up_getq2
|
||||
.global up_setq0
|
||||
.global up_setq1
|
||||
.global up_setq2
|
||||
.global up_lsbenc
|
||||
|
||||
.section .text
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the Read Only RV32IM Machine ISA (capabilities)
|
||||
****************************************************************************/
|
||||
|
||||
up_getmisa:
|
||||
csrr a0, CSR_MISA
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the Read Only RV32IM Vendor ID
|
||||
****************************************************************************/
|
||||
|
||||
up_getvendorid:
|
||||
csrr a0, CSR_MVENDORID
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the Read Only RV32IM ARCH ID
|
||||
****************************************************************************/
|
||||
|
||||
up_getarchid:
|
||||
csrr a0, CSR_MARCHID
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the Read Only RV32IM IMP ID
|
||||
****************************************************************************/
|
||||
|
||||
up_getimpid:
|
||||
csrr a0, CSR_MIMPID
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the Read Only RV32IM HART ID
|
||||
****************************************************************************/
|
||||
|
||||
up_gethartid:
|
||||
csrr a0, CSR_MHARTID
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the NR5M100 specific Embedded Priority Interrupt Controller (EPIC)
|
||||
* IRQ MASK register
|
||||
****************************************************************************/
|
||||
|
||||
up_getepicmask:
|
||||
csrr a0, NR5_EPIC_IRQ_MASK
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Returns the NR5M100 specific EPIC IRQ Priority register
|
||||
****************************************************************************/
|
||||
|
||||
up_getepicpri:
|
||||
csrr a0, NR5_EPIC_PRIMASK
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets the NR5M100 specific EPIC IRQ Priority register
|
||||
****************************************************************************/
|
||||
|
||||
up_setepicpri:
|
||||
csrrw a0, NR5_EPIC_PRIMASK, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets the NR5M100 specific SYSTICK control register
|
||||
****************************************************************************/
|
||||
|
||||
up_setsystick:
|
||||
csrw NR5_MSYSTICK_REG, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets bits in the NR5M100 specific PRI1 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_setpri1bit:
|
||||
csrrs a0, NR5_EPIC_PRI1, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Clears bits in the NR5M100 specific PRI1 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_clearpri1bit:
|
||||
csrrc a0, NR5_EPIC_PRI1, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets bits in the NR5M100 specific PRI2 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_setpri2bit:
|
||||
csrrs a0, NR5_EPIC_PRI2, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Clears bits in the NR5M100 specific PRI2 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_clearpri2bit:
|
||||
csrrc a0, NR5_EPIC_PRI2, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets bits in the NR5M100 specific PRI3 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_setpri3bit:
|
||||
csrrs a0, NR5_EPIC_PRI3, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Clears bits in the NR5M100 specific PRI3 mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_clearpri3bit:
|
||||
csrrc a0, NR5_EPIC_PRI3, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets bits in the NR5M100 specific IRQ mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_setirqmaskbit:
|
||||
csrrs a0, NR5_EPIC_IRQ_MASK, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Clears bits in the NR5M100 specific IRQ mask control register
|
||||
****************************************************************************/
|
||||
|
||||
up_clearirqmaskbit:
|
||||
csrrc a0, NR5_EPIC_IRQ_MASK, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Disables global interrupts in NR5M100 specific IRQ PRI control register
|
||||
****************************************************************************/
|
||||
|
||||
up_disableints:
|
||||
csrrc a0, NR5_EPIC_PRIMASK, 1
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Enables global interrupts in NR5M100 specific IRQ PRI control register
|
||||
****************************************************************************/
|
||||
|
||||
up_enableints:
|
||||
csrrs a0, NR5_EPIC_PRIMASK, 1
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Reads NR5M100 specific Q0 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_getq0:
|
||||
getq a0, q0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Reads NR5M100 specific Q1 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_getq1:
|
||||
getq a0, q1
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Reads NR5M100 specific Q2 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_getq2:
|
||||
getq a0, q2
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets NR5M100 specific Q0 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_setq0:
|
||||
setq q0, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets NR5M100 specific Q1 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_setq1:
|
||||
setq q1, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Sets NR5M100 specific Q2 register (used for interrupt processing)
|
||||
****************************************************************************/
|
||||
|
||||
up_setq2:
|
||||
setq q2, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Calls the NR5M100 specific LSBENC opcode. This opcode will find the
|
||||
* first least significant non-zero bit in a0 and return it's ordinal value.
|
||||
****************************************************************************/
|
||||
|
||||
up_lsbenc:
|
||||
lsbenc a0, a0
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Modeline to set vim formatting options for ASM file. For this to work,
|
||||
* you must enable moeline processing in your ~/.vimrc file with:
|
||||
*
|
||||
* ~/.vimrc:
|
||||
* set modeline
|
||||
*
|
||||
* vim: noet:ts=4:sw=4
|
||||
****************************************************************************/
|
||||
@@ -1,93 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_csr.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/* CSR Definitions */
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5_NR5_CSR_H
|
||||
#define __ARCH_RISCV_SRC_NR5_NR5_CSR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <arch/arch.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NR5_NR5M1XX)
|
||||
# include "hardware/nr5m1xx_epic.h"
|
||||
#endif
|
||||
|
||||
#include <arch/rv32im/csr.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define NR5_EPIC_IRQ_MASK 0x7E0
|
||||
#define NR5_EPIC_PRI1 0x7E1
|
||||
#define NR5_EPIC_PRI2 0x7E2
|
||||
#define NR5_EPIC_PRI3 0x7E3
|
||||
#define NR5_EPIC_PRIMASK 0x7E4
|
||||
#define NR5_MSYSTICK_REG 0x7E5
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void up_setsystick(uint32_t);
|
||||
|
||||
void up_setpri1bit(uint32_t);
|
||||
void up_setpri2bit(uint32_t);
|
||||
void up_setpri3bit(uint32_t);
|
||||
|
||||
void up_clearpri1bit(uint32_t);
|
||||
void up_clearpri2bit(uint32_t);
|
||||
void up_clearpri3bit(uint32_t);
|
||||
|
||||
void up_setirqmaskbit(uint32_t);
|
||||
void up_clearirqmaskbit(uint32_t);
|
||||
|
||||
void up_disableints(void);
|
||||
void up_enableints(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5_NR5_CSR_H */
|
||||
@@ -1,60 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_custom_ops.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define q0 0
|
||||
#define q1 1
|
||||
#define q2 2
|
||||
#define q3 3
|
||||
|
||||
/****************************************************************************
|
||||
* Assmebler Macros
|
||||
****************************************************************************/
|
||||
|
||||
.macro getq rd qs
|
||||
custom0 \rd, \qs, 0, 0
|
||||
.endm
|
||||
|
||||
.macro setq qd rs
|
||||
custom0 \qd, \rs, 0, 1
|
||||
.endm
|
||||
|
||||
.macro lsbenc rd rs
|
||||
custom0 \rd, \rs, 0, 2
|
||||
.endm
|
||||
|
||||
.macro timer rd rs
|
||||
custom0 \rd, \rs, 0, 5
|
||||
.endm
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,74 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_init.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function - Initialization
|
||||
*
|
||||
* Performs low level board initialization tasks.
|
||||
************************************************************************************/
|
||||
|
||||
void __nr5_init(void)
|
||||
{
|
||||
/* Configure the UART so we can get debug output */
|
||||
|
||||
nr5_lowsetup();
|
||||
|
||||
/* Do board initialization */
|
||||
|
||||
nr5_boardinitialize();
|
||||
|
||||
/* Call nx_start() */
|
||||
|
||||
nx_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
@@ -1,342 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_irq.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
volatile uint32_t *g_current_regs;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: epic_dump
|
||||
*
|
||||
* Description:
|
||||
* Dump the EPIC priority register settings
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void epic_dump(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
char str[40];
|
||||
|
||||
__asm__ volatile("csrr %0, 0x7e0" : "=r"(reg));
|
||||
sprintf(str, "IRQMASK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e4" : "=r"(reg));
|
||||
sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e1" : "=r"(reg));
|
||||
sprintf(str, "PRI1 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e2" : "=r"(reg));
|
||||
sprintf(str, "PRI2 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e3" : "=r"(reg));
|
||||
sprintf(str, "PRI3 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e5" : "=r"(reg));
|
||||
sprintf(str, "SYSTICK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nr5_trap
|
||||
*
|
||||
* Description:
|
||||
* Handler for exceptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provided over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#define CONFIG_DEBUG
|
||||
|
||||
int nr5_trap_handler(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
uint32_t sp;
|
||||
|
||||
/* Print a PANIC message */
|
||||
|
||||
up_puts("PANIC!!! TRAP received\r\n");
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
|
||||
/* restore the SP to that of the bad code */
|
||||
|
||||
sp = g_current_regs[2];
|
||||
__asm__ volatile ("addi x2, %0, 0" ::"r"(sp));
|
||||
|
||||
__asm__ volatile ("ebreak");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t mask;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
mask = ~0;
|
||||
__asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_IRQ_MASK), "r"(mask));
|
||||
|
||||
/* Colorize the interrupt stack for debug purposes */
|
||||
|
||||
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
{
|
||||
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
|
||||
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase -
|
||||
intstack_size), intstack_size);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the location of the vector table */
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
#ifdef NR5_EPIC_PRI_REG
|
||||
__asm__ volatile (" \
|
||||
csrw %0, 0(zero) \
|
||||
csrw %1, 0(zero) \
|
||||
csrw %2, 0(zero) " ::
|
||||
"i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG),
|
||||
"i"(NR5_EPIC_PRI3_REG));
|
||||
#endif
|
||||
|
||||
/* Initialize the IRQ stack to Pri level 5 with interrupts disabled */
|
||||
|
||||
mask = 0x05 << 2;
|
||||
__asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(mask));
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
g_current_regs = NULL;
|
||||
|
||||
/* Attach the Trap exception handler. */
|
||||
|
||||
irq_attach(NR5_IRQ_TRAP, nr5_trap_handler, NULL);
|
||||
|
||||
/* Attach software interrupt handler */
|
||||
|
||||
irq_attach(NR5_IRQ_SOFTWARE, up_swint, NULL);
|
||||
up_enable_irq(NR5_IRQ_SOFTWARE);
|
||||
|
||||
/* Set the software interrupt priority higher */
|
||||
|
||||
up_setpri2bit(1 << NR5_IRQ_SOFTWARE);
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
up_enable_irq(NR5_IRQ_TRAP);
|
||||
|
||||
#endif
|
||||
|
||||
/* Now enable Global Interrupts */
|
||||
|
||||
__asm__ volatile("csrrs a0, %0, 3" :: "i"(NR5_EPIC_PRIMASK));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
up_setirqmaskbit(1 << irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
up_clearirqmaskbit(1 << irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
{
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_get_newintctx
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t up_get_newintctx(void)
|
||||
{
|
||||
int32_t regval;
|
||||
|
||||
/* Set priority level 5, enabled upon return from interrupt */
|
||||
|
||||
regval = ((5 << 2) | 2) << 4;
|
||||
|
||||
return regval;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
* Since this API is not supported on all architectures, it should be
|
||||
* avoided in common implementations where possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irq_save
|
||||
*
|
||||
* Description:
|
||||
* Return the current interrupt state and disable interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
irqstate_t up_irq_save(void)
|
||||
{
|
||||
irqstate_t newpri = (2 << 2) | 3;
|
||||
irqstate_t oldpri;
|
||||
|
||||
/* Set the new IRQ Priority level to level 2, enabled.
|
||||
* This will allow SW and DEBUG / TRAP interrupts to
|
||||
* continue to fire, but no general purpose ints.
|
||||
*/
|
||||
|
||||
__asm__ volatile("csrrw %0, %1, %2" : "=r"(oldpri) :
|
||||
"i"(NR5_EPIC_PRIMASK), "r"(newpri));
|
||||
|
||||
return oldpri;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irq_restore
|
||||
*
|
||||
* Description:
|
||||
* Restore previous IRQ mask state
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_irq_restore(irqstate_t pri)
|
||||
{
|
||||
__asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(pri));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irq_enable
|
||||
*
|
||||
* Description:
|
||||
* Return the current interrupt state and enable interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
irqstate_t up_irq_enable(void)
|
||||
{
|
||||
irqstate_t newpri = up_get_newintctx();
|
||||
irqstate_t oldpri;
|
||||
|
||||
/* Set the new IRQ Priority level to level 5, enabled. This will allow
|
||||
* all interrupt.
|
||||
*/
|
||||
|
||||
__asm__ volatile("csrrw %0, %1, %2" : "=r"(oldpri) :
|
||||
"i"(NR5_EPIC_PRIMASK), "r"(newpri));
|
||||
|
||||
return oldpri;
|
||||
}
|
||||
@@ -1,156 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_irq_dispatch.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "riscv_arch.h"
|
||||
#include "riscv_internal.h"
|
||||
|
||||
#include "group/group.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Extern Functions
|
||||
****************************************************************************/
|
||||
|
||||
int up_lsbenc(int);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
volatile uint32_t * g_current_regs;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* irq_dispatch_all
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t * irq_dispatch_all(uint32_t *regs, uint32_t irqmask)
|
||||
{
|
||||
int next;
|
||||
int mask;
|
||||
mask = irqmask & 0xffff;
|
||||
|
||||
board_autoled_on(LED_INIRQ);
|
||||
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
PANIC();
|
||||
#else
|
||||
/* Current regs non-zero indicates that we are processing an interrupt;
|
||||
* g_current_regs is also used to manage interrupt level context switches.
|
||||
*
|
||||
* Nested interrupts are not supported
|
||||
*/
|
||||
|
||||
DEBUGASSERT(g_current_regs == NULL);
|
||||
g_current_regs = regs;
|
||||
|
||||
/* Get ordinal index of interrupt number from mask */
|
||||
|
||||
next = up_lsbenc(mask);
|
||||
while (next != -1)
|
||||
{
|
||||
/* Deliver the IRQ */
|
||||
|
||||
irq_dispatch(next, regs);
|
||||
|
||||
/* Clear the IRQ from the mask */
|
||||
|
||||
mask &= !(1 << next);
|
||||
next = up_lsbenc(mask);
|
||||
|
||||
#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
|
||||
/* Check for a context switch. If a context switch occurred, then
|
||||
* g_current_regs will have a different value than it did on entry.
|
||||
* If an interrupt level context switch has occurred, then restore the
|
||||
* floating point state and the establish the correct address
|
||||
* environment before returning from the interrupt.
|
||||
*/
|
||||
|
||||
if (regs != g_current_regs)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Restore floating point registers */
|
||||
|
||||
up_restorefpu((uint32_t *)g_current_regs);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_ADDRENV
|
||||
/* Make sure that the address environment for the previously
|
||||
* running task is closed down gracefully (data caches dump,
|
||||
* MMU flushed) and set up the address environment for the new
|
||||
* thread at the head of the ready-to-run list.
|
||||
*/
|
||||
|
||||
group_addrenv(NULL);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* If a context switch occurred while processing the interrupt then
|
||||
* g_current_regs may have change value. If we return any value different
|
||||
* from the input regs, then the lower level will know that a context
|
||||
* switch occurred during interrupt processing.
|
||||
*/
|
||||
|
||||
regs = (uint32_t *) g_current_regs;
|
||||
g_current_regs = NULL;
|
||||
|
||||
board_autoled_off(LED_INIRQ);
|
||||
|
||||
/* Return the stack pointer */
|
||||
|
||||
return regs;
|
||||
}
|
||||
@@ -1,183 +0,0 @@
|
||||
/**************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_lowputc.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "riscv_internal.h"
|
||||
#include "riscv_arch.h"
|
||||
|
||||
#include "nr5_config.h"
|
||||
#include "nr5.h"
|
||||
|
||||
/**************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
# if defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define NR5_CONSOLE_BASE NR5_UART1_BASE
|
||||
# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define NR5_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
# define NR5_CONSOLE_TX GPIO_UART1_TX
|
||||
# define NR5_CONSOLE_RX GPIO_UART1_RX
|
||||
# define HAVE_UART
|
||||
# elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define NR5_CONSOLE_BASE NR5_UART1_BASE
|
||||
# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define NR5_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
# define NR5_CONSOLE_TX GPIO_UART1_TX
|
||||
# define NR5_CONSOLE_RX GPIO_UART1_RX
|
||||
# define HAVE_UART
|
||||
# endif
|
||||
|
||||
/* Calculate UART BAUD rate divider */
|
||||
|
||||
# if defined(CONFIG_NR5_NR5M1XX)
|
||||
|
||||
/* Baud rate for standard UART:
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* UARTDIV = fCK / 32 / baud
|
||||
*/
|
||||
|
||||
# define NR5_UARTDIV \
|
||||
((NR5_HCLK_FREQUENCY >> 5) / NR5_CONSOLE_BAUD)
|
||||
|
||||
# endif /* CONFIG_NR5_NR5M1XX */
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Function Prototypes
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Global Variables
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Variables
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#ifdef HAVE_SERIAL_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(NR5_CONSOLE_BASE + NR5_UART_STATUS_REG_OFFSET) &
|
||||
NR5_UART_STATUS_TX_EMPTY) == 0)
|
||||
;
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, NR5_CONSOLE_BASE + NR5_UART_TX_REG_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* Name: nr5_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output available as soon
|
||||
* as possible.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NR5_NR5M1XX)
|
||||
|
||||
void nr5_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART)
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
||||
#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
|
||||
/* Configure the UART Baud Rate */
|
||||
|
||||
putreg32(NR5_UARTDIV, NR5_CONSOLE_BASE + NR5_UART_BAUD_RATE_OFFSET);
|
||||
|
||||
/* Configure the RX interrupt */
|
||||
|
||||
putreg32(NR5_UART_CTRL_ENABLE_RX_IRQ,
|
||||
NR5_CONSOLE_BASE + NR5_UART_CTRL_REG_OFFSET);
|
||||
|
||||
#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
#else
|
||||
# error "Unsupported NR5 chip"
|
||||
#endif
|
||||
@@ -1,79 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_lowputc.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: nr5_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of __nr5_init. Performs low level initialization
|
||||
* of serial console.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void nr5_lowsetup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H */
|
||||
@@ -1,46 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
|
||||
#define _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/* #include <stdint.h> */
|
||||
|
||||
#ifdef CONFIG_NR5_NR5MXXX
|
||||
#include "hardware/nr5m1xx_memorymap.h"
|
||||
#endif
|
||||
|
||||
#endif /* _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H */
|
||||
@@ -1,205 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_schedulesigaction.c
|
||||
*
|
||||
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sched.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/nr5m100/irq.h>
|
||||
|
||||
#include "sched/sched.h"
|
||||
#include "riscv_internal.h"
|
||||
#include "riscv_arch.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_schedule_sigaction
|
||||
*
|
||||
* Description:
|
||||
* This function is called by the OS when one or more
|
||||
* signal handling actions have been queued for execution.
|
||||
* The architecture specific code must configure things so
|
||||
* that the 'sigdeliver' callback is executed on the thread
|
||||
* specified by 'tcb' as soon as possible.
|
||||
*
|
||||
* This function may be called from interrupt handling logic.
|
||||
*
|
||||
* This operation should not cause the task to be unblocked
|
||||
* nor should it cause any immediate execution of sigdeliver.
|
||||
* Typically, a few cases need to be considered:
|
||||
*
|
||||
* (1) This function may be called from an interrupt handler
|
||||
* During interrupt processing, all xcptcontext structures
|
||||
* should be valid for all tasks. That structure should
|
||||
* be modified to invoke sigdeliver() either on return
|
||||
* from (this) interrupt or on some subsequent context
|
||||
* switch to the recipient task.
|
||||
* (2) If not in an interrupt handler and the tcb is NOT
|
||||
* the currently executing task, then again just modify
|
||||
* the saved xcptcontext structure for the recipient
|
||||
* task so it will invoke sigdeliver when that task is
|
||||
* later resumed.
|
||||
* (3) If not in an interrupt handler and the tcb IS the
|
||||
* currently executing task -- just call the signal
|
||||
* handler now.
|
||||
*
|
||||
* Assumptions:
|
||||
* Called from critical section
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
uint32_t int_ctx;
|
||||
|
||||
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
|
||||
|
||||
/* Refuse to handle nested signal actions */
|
||||
|
||||
if (!tcb->xcp.sigdeliver)
|
||||
{
|
||||
/* First, handle some special cases when the signal is
|
||||
* being delivered to the currently executing task.
|
||||
*/
|
||||
|
||||
sinfo("rtcb=0x%p g_current_regs=0x%p\n",
|
||||
this_task(), g_current_regs);
|
||||
|
||||
if (tcb == this_task())
|
||||
{
|
||||
/* CASE 1: We are not in an interrupt handler and
|
||||
* a task is signalling itself for some reason.
|
||||
*/
|
||||
|
||||
if (!g_current_regs)
|
||||
{
|
||||
/* In this case just deliver the signal now. */
|
||||
|
||||
sigdeliver(tcb);
|
||||
}
|
||||
|
||||
/* CASE 2: We are in an interrupt handler AND the
|
||||
* interrupted task is the same as the one that
|
||||
* must receive the signal, then we will have to modify
|
||||
* the return state as well as the state in the TCB.
|
||||
*
|
||||
* Hmmm... there looks like a latent bug here: The following
|
||||
* logic would fail in the strange case where we are in an
|
||||
* interrupt handler, the thread is signalling itself, but
|
||||
* a context switch to another task has occurred so that
|
||||
* g_current_regs does not refer to the thread of this_task()!
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return EPC and STATUS registers. These will be
|
||||
* restored by the signal trampoline after the signals have
|
||||
* been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_epc = g_current_regs[REG_EPC];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver;
|
||||
int_ctx = g_current_regs[REG_INT_CTX];
|
||||
int_ctx &= ~EPIC_STATUS_INT_PRI_MASK;
|
||||
int_ctx |= EPIC_STATUS_INT_PRI1;
|
||||
g_current_regs[REG_INT_CTX] = int_ctx;
|
||||
|
||||
/* And make sure that the saved context in the TCB
|
||||
* is the same as the interrupt return context.
|
||||
*/
|
||||
|
||||
up_savestate(tcb->xcp.regs);
|
||||
|
||||
sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
|
||||
tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx,
|
||||
g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Otherwise, we are (1) signaling a task is not running
|
||||
* from an interrupt handler or (2) we are not in an
|
||||
* interrupt handler and the running task is signalling
|
||||
* some non-running task.
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return EPC and STATUS registers. These will be
|
||||
* restored by the signal trampoline after the signals have
|
||||
* been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC];
|
||||
tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver;
|
||||
int_ctx = tcb->xcp.regs[REG_INT_CTX];
|
||||
int_ctx &= ~EPIC_STATUS_INT_PRI_MASK;
|
||||
int_ctx |= EPIC_STATUS_INT_PRI1;
|
||||
tcb->xcp.regs[REG_INT_CTX] = int_ctx;
|
||||
|
||||
sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
|
||||
tcb->xcp.saved_epc, tcb->xcp.saved_int_ctx,
|
||||
tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]);
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,169 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_timer.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/nr5m1xx_timer.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Helpers ******************************************************************/
|
||||
|
||||
#define NR5_TIMER_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define NR5_TIMER_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define NR5_TIMER_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
|
||||
#define NR5_TIMER_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
|
||||
#define NR5_TIMER_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
|
||||
#define NR5_TIMER_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
|
||||
#define NR5_TIMER_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define NR5_TIMER_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Timer Modes of Operation */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NR5_TIMER_MODE_UNUSED = -1,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
NR5_TIMER_MODE_DISABLED = 0x0000,
|
||||
NR5_TIMER_MODE_UP = 0x0001,
|
||||
NR5_TIMER_MODE_CONTINUOUS = 0x0002,
|
||||
NR5_TIMER_MODE_UPDOWN = 0x0003,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
NR5_TIM_MODE_CK_SLOW = 0x0000,
|
||||
NR5_TIM_MODE_CK_MED = 0x0010,
|
||||
NR5_TIM_MODE_CK_SYS = 0x0020,
|
||||
NR5_TIM_MODE_CK_EXT = 0x0030,
|
||||
} nr5_timer_mode_t;
|
||||
|
||||
/* Timer Operations */
|
||||
|
||||
struct nr5_timer_dev_s;
|
||||
|
||||
struct nr5_timer_ops_s
|
||||
{
|
||||
/* Basic Timer Operations */
|
||||
|
||||
int (*setmode)(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t mode);
|
||||
int (*setclock)(FAR struct nr5_timer_dev_s *dev, uint32_t freq);
|
||||
void (*setperiod)(FAR struct nr5_timer_dev_s *dev, uint32_t period);
|
||||
|
||||
/* Timer Interrupt Operations */
|
||||
|
||||
int (*setisr)(FAR struct nr5_timer_dev_s *dev, xcpt_t handler, void *arg,
|
||||
int source);
|
||||
void (*enableint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
void (*disableint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
void (*ackint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
};
|
||||
|
||||
/* Timer Device Structure */
|
||||
|
||||
struct nr5_timer_dev_s
|
||||
{
|
||||
struct nr5_timer_ops_s *ops;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* Power-up timer and get its structure */
|
||||
|
||||
FAR struct nr5_timer_dev_s *nr5_timer_init(int timer);
|
||||
|
||||
/* Power-down timer, mark it as unused */
|
||||
|
||||
int nr5_timer_deinit(FAR struct nr5_timer_dev_s *dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nr5_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Bind the configuration timer to a timer lower half instance and
|
||||
* register the timer drivers at 'devpath'
|
||||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the timer device. This should be of the form
|
||||
* /dev/timer0
|
||||
* timer - the timer number.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; A negated errno value is returned
|
||||
* to indicate the nature of any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TIMER
|
||||
int nr5_timer_initialize(FAR const char *devpath, int timer);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H */
|
||||
@@ -1,159 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_timerisr.c
|
||||
*
|
||||
* Copyright (C) 2009, 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Modified for RISC-V:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "riscv_arch.h"
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
|
||||
* divided by 8. The SysTick can work either with this clock or with the
|
||||
* Cortex clock (HCLK), configurable in the SysTick Control and Status
|
||||
* register.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_NR5_SYSTICK_SCLK
|
||||
# define SYSTICK_RELOAD ((NR5_SCLK_FREQUENCY / CLOCKS_PER_SEC) - 1)
|
||||
#else
|
||||
# define SYSTICK_RELOAD ((NR5_HCLK_FREQUENCY / CLOCKS_PER_SEC) - 1)
|
||||
#endif
|
||||
|
||||
/* The size of the reload field is 30 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x3fffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static uint64_t g_systick = 0;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: nr5m100_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int nr5m100_timerisr(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
nxsched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_get_systick
|
||||
*
|
||||
* Description:
|
||||
* Returns the current value of systick.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint64_t up_get_systick(void)
|
||||
{
|
||||
return g_systick;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
up_clearpri1bit(NR5_IRQ_SYSTICK);
|
||||
up_clearpri2bit(NR5_IRQ_SYSTICK);
|
||||
up_clearpri3bit(NR5_IRQ_SYSTICK);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
irq_attach(NR5_IRQ_SYSTICK, nr5m100_timerisr, NULL);
|
||||
|
||||
/* Configure and enable SysTick to interrupt at the requested rate */
|
||||
|
||||
up_setsystick(0x80000000 | SYSTICK_RELOAD);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(NR5_IRQ_SYSTICK);
|
||||
}
|
||||
@@ -1,263 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_uart.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define MAKE_UINT32(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | d)
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
************************************************************************************/
|
||||
|
||||
struct nr5_uart_buffer_s
|
||||
{
|
||||
uint16_t head;
|
||||
uint16_t tail;
|
||||
uint16_t size;
|
||||
char * buffer;
|
||||
};
|
||||
|
||||
struct nr5_uart_regs_s
|
||||
{
|
||||
uint32_t *pbaud; /* Data status port */
|
||||
uint32_t *pstat; /* Data status port */
|
||||
uint8_t *ptx; /* Data TX port */
|
||||
uint8_t *prx; /* Data RX port */
|
||||
uint32_t *pintctrl; /* Interrupt enable control */
|
||||
int rxirq; /* IRQ number */
|
||||
int txirq; /* IRQ number */
|
||||
};
|
||||
|
||||
struct nr5_uart_s
|
||||
{
|
||||
volatile struct nr5_uart_regs_s *regs;
|
||||
struct nr5_uart_buffer_s *txbuf;
|
||||
struct nr5_uart_buffer_s *rxbuf;
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
/* Static global pointers to access the hardware */
|
||||
|
||||
#ifdef CONFIG_NR5_HAVE_UART1
|
||||
static char g_uart1_rx_buf[CONFIG_NR5_UART_RX_BUF_SIZE];
|
||||
static char g_uart1_tx_buf[CONFIG_NR5_UART_TX_BUF_SIZE];
|
||||
|
||||
static struct nr5_uart_buffer_s g_nr5_uart1_rx_buf =
|
||||
{
|
||||
.head = 0,
|
||||
.tail = 0,
|
||||
.size = CONFIG_NR5_UART_RX_BUF_SIZE,
|
||||
.buffer = g_uart1_rx_buf,
|
||||
};
|
||||
|
||||
static struct nr5_uart_buffer_s g_nr5_uart1_tx_buf =
|
||||
{
|
||||
.head = 0,
|
||||
.tail = 0,
|
||||
.size = CONFIG_NR5_UART_TX_BUF_SIZE,
|
||||
.buffer = g_uart1_tx_buf,
|
||||
};
|
||||
|
||||
static volatile struct nr5_uart_regs_s g_nr5_uart1_regs =
|
||||
{
|
||||
.pbaud = (uint32_t *) NR5_UART1_BAUD_RATE_REG,
|
||||
.pstat = (uint32_t *) NR5_UART1_STATUS_REG,
|
||||
.prx = (uint8_t *) NR5_UART1_RX_REG,
|
||||
.ptx = (uint8_t *) NR5_UART1_TX_REG,
|
||||
.pintctrl = (uint32_t *) NR5_UART1_CTRL_REG,
|
||||
.rxirq = NR5_IRQ_UART1_RX,
|
||||
.txirq = NR5_IRQ_UART1_TX,
|
||||
};
|
||||
|
||||
static struct nr5_uart_s g_nr5_uart1 =
|
||||
{
|
||||
.regs = &g_nr5_uart1_regs,
|
||||
.rxbuf = &g_nr5_uart1_rx_buf,
|
||||
.txbuf = &g_nr5_uart1_tx_buf,
|
||||
};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/* ISR for NanoRisc5 UART RX available. */
|
||||
|
||||
int nr5_uart_rx_isr(int irq_num, void *context)
|
||||
{
|
||||
struct nr5_uart_s *dev = NULL;
|
||||
char rxdata;
|
||||
|
||||
#ifdef CONFIG_NR5_HAVE_UART1
|
||||
if (irq_num == g_nr5_uart1_regs.rxirq)
|
||||
{
|
||||
dev = &g_nr5_uart1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Process the data */
|
||||
|
||||
if (dev != NULL)
|
||||
{
|
||||
/* Read the RX byte */
|
||||
|
||||
rxdata = *dev->regs->prx;
|
||||
*dev->regs->ptx = rxdata;
|
||||
|
||||
dev->rxbuf->buffer[dev->rxbuf->head++] = rxdata;
|
||||
if (dev->rxbuf->head == dev->rxbuf->size)
|
||||
{
|
||||
dev->rxbuf->head = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Routine to initialize the HAL layer. Must be called prior to any other
|
||||
* HAL function.
|
||||
*/
|
||||
|
||||
void nr5_uart_init(int uart)
|
||||
{
|
||||
volatile struct nr5_uart_s *dev = NULL;
|
||||
uint32_t cmpval = MAKE_UINT32('F', 'P', 'G', 'A');
|
||||
|
||||
switch (uart)
|
||||
{
|
||||
#ifdef CONFIG_NR5_HAVE_UART1
|
||||
case 1:
|
||||
dev = &g_nr5_uart1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* If a device was selected above, then initialize it. */
|
||||
|
||||
if (dev != NULL)
|
||||
{
|
||||
/* Attach the ISR and enable the IRQ with the EPIC */
|
||||
|
||||
/* irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL); */
|
||||
|
||||
/* up_enable_irq(dev->regs->rxirq); */
|
||||
|
||||
/* Set the baud rate */
|
||||
|
||||
if (up_getimpid() == cmpval)
|
||||
{
|
||||
*dev->regs->pbaud = 0x0d;
|
||||
}
|
||||
|
||||
/* Now enable the RX IRQ in the UART peripheral */
|
||||
|
||||
/* *dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ; */
|
||||
}
|
||||
}
|
||||
|
||||
/* Routine to get RX byte from console UART. */
|
||||
|
||||
uint8_t nr5_uart_get_rx()
|
||||
{
|
||||
uint8_t rxdata = 0;
|
||||
|
||||
up_disableints();
|
||||
if (g_nr5_uart1.rxbuf->head != g_nr5_uart1.rxbuf->tail)
|
||||
{
|
||||
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
|
||||
|
||||
rxdata = pbuf->buffer[pbuf->tail++];
|
||||
if (pbuf->tail == pbuf->size)
|
||||
pbuf->tail = 0;
|
||||
}
|
||||
|
||||
up_enableints();
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/* Routine to test if RX byte available at console UART */
|
||||
|
||||
int nr5_uart_test_rx_avail()
|
||||
{
|
||||
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
|
||||
int avail;
|
||||
|
||||
up_disableints();
|
||||
avail = !(pbuf->head == pbuf->tail);
|
||||
up_enableints();
|
||||
|
||||
/* If no RX data available then halt the processor until an interrupt */
|
||||
|
||||
if (!avail)
|
||||
{
|
||||
__asm__ volatile ("wfi");
|
||||
}
|
||||
|
||||
return avail;
|
||||
}
|
||||
|
||||
/* Routine to test if RX byte available at console UART. */
|
||||
|
||||
int nr5_uart_test_tx_empty()
|
||||
{
|
||||
return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
|
||||
}
|
||||
|
||||
/* Routine to send TX byte to console UART. */
|
||||
|
||||
void nr5_uart_put_tx(uint8_t ch)
|
||||
{
|
||||
/* Wait for TX to be empty */
|
||||
|
||||
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
|
||||
;
|
||||
|
||||
/* Write to TX */
|
||||
|
||||
*g_nr5_uart1.regs->ptx = ch;
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_uart.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ARCH_RISCV_SRC_NR5_NR5_UART_H
|
||||
#define _ARCH_RISCV_SRC_NR5_NR5_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef CONFIG_NR5_NR5M1XX
|
||||
#include "hardware/nr5m1xx_uart.h"
|
||||
#endif
|
||||
|
||||
void nr5_uart_init(int uart_num);
|
||||
uint8_t nr5_uart_get_rx(void);
|
||||
int nr5_uart_test_rx_avail(void);
|
||||
int nr5_uart_test_tx_empty(void);
|
||||
void nr5_uart_put_tx(uint8_t ch);
|
||||
|
||||
#endif /* _ARCH_RISCV_SRC_NR5_NR5_UART_H */
|
||||
@@ -1,101 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_vectors.S
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include "nr5_csr.h"
|
||||
|
||||
.section .text.vec
|
||||
.global __reset_vec
|
||||
.global __trap_vec
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 00h - RESET
|
||||
************************************************************************************/
|
||||
|
||||
__reset_vec:
|
||||
csrw NR5_EPIC_PRIMASK, 7
|
||||
j __start
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 08h - PRI0 (Illegal Instruction, Bus Error)
|
||||
************************************************************************************/
|
||||
|
||||
__trap_vec:
|
||||
__pri0_vec:
|
||||
j irq_handler
|
||||
nop
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 10h - PRI1 Interrupt Handler
|
||||
************************************************************************************/
|
||||
|
||||
__pri1_vec:
|
||||
j irq_handler
|
||||
nop
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 18h - PRI2 Interrupt Handler
|
||||
************************************************************************************/
|
||||
|
||||
__pri2_vec:
|
||||
j irq_handler
|
||||
nop
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 20h - PRI3 Interrupt Handler
|
||||
************************************************************************************/
|
||||
|
||||
__pri3_vec:
|
||||
j irq_handler
|
||||
nop
|
||||
|
||||
/************************************************************************************
|
||||
* ADDR: 28h - PRI4 Interrupt Handler
|
||||
************************************************************************************/
|
||||
|
||||
__pri4_vec:
|
||||
j irq_handler
|
||||
nop
|
||||
|
||||
/****************************************************************************
|
||||
* Modeline to set vim formatting options for ASM file. For this to work,
|
||||
* you must enable moeline processing in your ~/.vimrc file with:
|
||||
*
|
||||
* ~/.vimrc:
|
||||
* set modeline
|
||||
*
|
||||
* vim: noet:ts=4:sw=4
|
||||
****************************************************************************/
|
||||
@@ -4,8 +4,6 @@
|
||||
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
|
||||
* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
|
||||
*
|
||||
* Based on arch/risc-v/src/nr5m100/up_schedulesigaction.c
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
|
||||
@@ -1022,14 +1022,6 @@ config ARCH_BOARD_PIC32MZ_STARTERKIT
|
||||
|
||||
See www.microchip.com for further information.
|
||||
|
||||
config ARCH_BOARD_NR5M100_NEXYS4
|
||||
bool "NEXT RISC-V NR5M100 on Nexys-4 board"
|
||||
depends on ARCH_CHIP_NR5M100
|
||||
select UART_SERIALDRIVER
|
||||
---help---
|
||||
This is the port NuttX to the NEXT RISC-V processor runnining on a Digilent
|
||||
Nexys-4 (non DDR version) FPGA board.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_F429ZI
|
||||
bool "STMicro NUCLEO-F429ZI"
|
||||
depends on ARCH_CHIP_STM32F429Z
|
||||
@@ -2320,7 +2312,6 @@ config ARCH_BOARD
|
||||
default "nucleo-l476rg" if ARCH_BOARD_NUCLEO_L476RG
|
||||
default "nucleo-l496zg" if ARCH_BOARD_NUCLEO_L496ZG
|
||||
default "nutiny-nuc120" if ARCH_BOARD_NUTINY_NUC120
|
||||
default "nr5m100-nexys4" if ARCH_BOARD_NR5M100_NEXYS4
|
||||
default "olimex-efm32g880f128-stk" if ARCH_BOARD_OLIMEX_EFM32G880F128_STK
|
||||
default "olimex-lpc1766stk" if ARCH_BOARD_LPC1766STK
|
||||
default "olimex-lpc2378" if ARCH_BOARD_OLIMEXLPC2378
|
||||
@@ -3046,9 +3037,6 @@ endif
|
||||
if ARCH_BOARD_GAPUINO
|
||||
source "boards/risc-v/gap8/gapuino/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NR5M100_NEXYS4
|
||||
source "boards/risc-v/nr5m100/nr5m100-nexys4/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_HIFIVE_REVB
|
||||
source "boards/risc-v/fe310/hifive1-revb/Kconfig"
|
||||
endif
|
||||
|
||||
@@ -625,9 +625,6 @@ boards/x86/qemu/qemu-i486
|
||||
Port of NuttX to QEMU in i486 mode. This port will also run on real i486
|
||||
hardware (Google the Bifferboard).
|
||||
|
||||
boards/risc-v/nr5m100/nr5m100-nexys4
|
||||
Port of NuttX to RISC-V platform on IQ-Analog NR5M100 RISC-V FPGA platform.
|
||||
|
||||
boards/arm/s32k1xx/s32k118evb
|
||||
This directory holds the port of NuttX to the NXP S32K118EVB board
|
||||
featuring the S32K118 Cortex-M0+.
|
||||
|
||||
@@ -1,9 +0,0 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_NR5M100_NEXYS4
|
||||
|
||||
|
||||
endif
|
||||
@@ -1,242 +0,0 @@
|
||||
README
|
||||
======
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
IQ-Analog NR5M100 FPGA implementation of a RISC-V core on the Digilent
|
||||
Nexys4 FPGA board.
|
||||
|
||||
The port is currently very minimal, though additional support may be
|
||||
added in the future to address more of the board peripherals supplied
|
||||
on the FPGA board. Those peripherals include:
|
||||
|
||||
Supported:
|
||||
- USB UART (console port)
|
||||
- 16 single color LEDs
|
||||
- 16 slide switch inputs
|
||||
- Two tri-color LEDs
|
||||
- 5 Joystick style pushbuttons
|
||||
- 16 GPIO pins on 2 of the PMOD expansion connectors
|
||||
|
||||
Not supported:
|
||||
- VGA display port
|
||||
- 8 digit 7-segement display
|
||||
- SD card slot
|
||||
- SPI FLASH memory (shared with FPGA configuration data).
|
||||
- USB HID (single device) connector serviced by external PIC uC
|
||||
- Non-DDR (older version): 16 MB Cellular SRAM
|
||||
- DDR (newer version): 128 MB DDR2 SDRAM
|
||||
- Microphone
|
||||
- 10/100 Ethernet PHY
|
||||
- 3-Axis accelerometer
|
||||
- Temperature sensor
|
||||
|
||||
See http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/
|
||||
or http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/
|
||||
for more information about these boards.
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
- NR5M100 Overview
|
||||
- Development Environment
|
||||
- GNU Toolchain Options
|
||||
- Debugger
|
||||
- IDEs
|
||||
- LEDs
|
||||
- PWM
|
||||
- UARTs
|
||||
- Timer Inputs/Outputs
|
||||
- FSMC SRAM
|
||||
- SSD1289
|
||||
- Mikroe-STM32F4-specific Configuration Options
|
||||
- Configurations
|
||||
|
||||
Development Environment
|
||||
=======================
|
||||
The NR5M100 RISC-V core was designed as a low gate count / low performance micro controller
|
||||
for inclusion in an ASIC. It is based on a Verilog RISC-V called picorv32, but has many
|
||||
additions beyond that baseline. The design running on the Digilent Nexys4 FPGA is a
|
||||
validation platform for the core and is presented as an open source project.
|
||||
|
||||
The reason NR5M100 is "low performance" is that it is a state machine based core (like the
|
||||
picorv32) and not a multi-stage pipeline core. This means that it requires an average of
|
||||
4.5 clock cycles to execute each instruction. On a multi-stage pipeline architecture, this
|
||||
average would be closer to 1 clock cycle per instruction (though a bit higher due to
|
||||
pipeline branch misses). The tradeoff for lower performance is a simpler design. There
|
||||
is a single memory bus interface for both instructions and data. Multi-stage pipeline
|
||||
cores require a separate I and D bus with cache SRAM and an external memory cache controller,
|
||||
etc. This in addition to the pipeline registers adds additional gate count.
|
||||
|
||||
The nr5m100-nexys4 core runs at 83.333 MHz which provides about 18 MHz effective operating
|
||||
speed with the multi-clock per instruction architecture. If you are looking for a higher
|
||||
performance platform, you should check out the PULP Platform ( http://www.pulp-platform.org ).
|
||||
That is an FPGA design with a 4-stage pipeline RISC-V core, though not currently supported
|
||||
by NuttX. The NR5M100 project will likely pull in the RISC-V core from that design next,
|
||||
though this will probably not be available soon. With a bit of work, it is possible to
|
||||
run the nr5m100-nexys4 core at 170 MHz with a 6.5 clocks-per-instruction state machine.
|
||||
This would give an effective performance of about 26Mhz.
|
||||
|
||||
Development Environment
|
||||
=======================
|
||||
|
||||
Linux is the best choice for development, though Cygwin on Windows may work.
|
||||
The source has been built only using the GNU toolchain (see below) under a Linux
|
||||
environment. Other toolchains will likely cause problems or not be available yet.
|
||||
|
||||
RISC-V GNU Toolchain
|
||||
====================
|
||||
|
||||
To compile the code, you must first build a RISC-V GNU Toolchain from the sources at
|
||||
https://github.com/riscv/riscv-gnu-toolchain. I don't know of any sources for pre-compiled
|
||||
toolchains (though there may be some out there).
|
||||
|
||||
To build this toolchain, follow these instructions (tested on Ubuntu 12.04):
|
||||
|
||||
1. Create a working directory in your home folder:
|
||||
|
||||
mkdir ~/riscv
|
||||
cd ~/riscv
|
||||
|
||||
2. Clone the GNU source tree:
|
||||
|
||||
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
|
||||
|
||||
3. Ensure the following packages are installed:
|
||||
|
||||
sudo apt-get install texinfo bison flex autoconf automake libgmp-dev libmpfr-dev libmpc-dev
|
||||
|
||||
4. Configure and build the toolchain:
|
||||
|
||||
cd riscv-gnu-toolchain
|
||||
./configure --with-xlen=64 --with-arch=I --disable-float --disable-atomic --enable-multilib --prefix=~/riscv
|
||||
make -j4 (or -j8 based on how many cores you have)
|
||||
|
||||
5. Setup your PATH environment variable to include the toolchain (you may want to add this to
|
||||
your shell login script, such as .bash_profile, etc.):
|
||||
|
||||
export PATH=~/riscv/bin:$PATH
|
||||
|
||||
Windows based toolchain
|
||||
-----------------------
|
||||
May be possible to compile the GNU toolchain described above using Cygwin, but havne't tried it.
|
||||
|
||||
Debugger
|
||||
========
|
||||
The Debug Module within the NR5M100 RISC-V has been designed to work with the RISC-V gdb
|
||||
debugger interfaced with the SiFive implementation of OpenOCD. The interface has been tested
|
||||
with a J-LINK JTAG probe connected to PMOD header B on the FPGA using an adapter board
|
||||
that I designed and fabbed at OSHPark. I will update this README.txt file soon with a link
|
||||
to the shared project for anyone who wishes to build one.
|
||||
|
||||
To build OpenOCD, perform the following:
|
||||
|
||||
1. Ensure the proper packages are installed:
|
||||
|
||||
sudo apt-get install autoconf automake libtool libusb-1.0-0-dev
|
||||
|
||||
2. Download the latest OpenOCD sources from the SiFive github repo:
|
||||
|
||||
cd ~/riscv
|
||||
git clone --recursive https://github.com/sifive/openocd.git
|
||||
|
||||
3. Configure and build OpenOCD. The x86_64 GCC compilers will give errors because of
|
||||
shadowed variable warnings, so disable the -Werror flag also:
|
||||
|
||||
cd openocd
|
||||
sed -i.bak 's/ -Werror//g' configure.ac
|
||||
./bootstrap
|
||||
./configure --enable-jlink --enable-maintainer-mode --enable-ftdi --prefix=~/riscv CFLAGS=-g
|
||||
|
||||
The configuration scripts for openocd and nr5m100-nexys4 have been provided in the
|
||||
nuttx/boards/nr5m100/nr5m100-nexys4/scripts directory. They are configured to use a J-LINK JTAG
|
||||
probe and to search for the IQ-Analog (the company I work for) IDCODE and part number for
|
||||
the FPGA board (7a10 for Artix xc7a100 part on the Digilent Nexys4 board). With FPGA
|
||||
source directly from the nr5m100 github site (to be provided), this ID will match the
|
||||
hardware. If changes are made to the JEDEC ID and/or part number, then the nr5m100.cfg
|
||||
file will need to be modified with the proper CPUID value.
|
||||
|
||||
IDEs
|
||||
====
|
||||
|
||||
NuttX is built using command-line make. It can be used with an IDE, but some
|
||||
effort will be required to create the project. While I haven't tried it as
|
||||
I am not an IDE guy, the team at SiFive have reported that they now have
|
||||
Eclipse working with the RISC-V gdb debugger.
|
||||
|
||||
NOTE: The notes below are taken from an ARM build of NuttX, not RISC-V, so
|
||||
they may or may not work. Try it and see I suppose.
|
||||
|
||||
Makefile Build
|
||||
--------------
|
||||
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
|
||||
simply use the NuttX makefile to build the system. That is almost for free
|
||||
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
|
||||
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
|
||||
there is a lot of help on the internet).
|
||||
|
||||
Native Build
|
||||
------------
|
||||
Here are a few tips before you start that effort:
|
||||
|
||||
1) Select the toolchain that you will be using in your .config file
|
||||
2) Start the NuttX build at least one time from the Cygwin command line
|
||||
before trying to create your project. This is necessary to create
|
||||
certain auto-generated files and directories that will be needed.
|
||||
3) Set up include paths: You will need include/, arch/risc-v/src/rv32im,
|
||||
arch/risc-v/src/common, arch/risc-v/src/nr5m100, and sched/.
|
||||
4) All assembly files need to have the definition option -D __ASSEMBLY__
|
||||
on the command line.
|
||||
|
||||
Startup files will probably cause you some headaches. The NuttX startup file
|
||||
is arch/risc-v/src/nr5m100/nr5_vectors.S. With RIDE, I build NuttX
|
||||
one time from the Cygwin command line in order to obtain the pre-built
|
||||
startup object needed by RIDE.
|
||||
|
||||
LEDs
|
||||
====
|
||||
|
||||
The Nexys4 board has 16 single-color LEDs onboard, as well as 2 tri-color LEDs.
|
||||
These are supported using GPIO Ports A (16-single color) and B (tri-color).
|
||||
Additionally the tri-color LEDs can be driven from the Timer 1 or 2 PWM output
|
||||
signals.
|
||||
|
||||
PWM
|
||||
===
|
||||
|
||||
The nr5m100-nexys4 design has PWM capabilities within the Timer 1 and Timer 2
|
||||
modules. These PWM signals can be muxed to the tri-color LEDs or to I/O
|
||||
pins on one of the PMOD expansion headers.
|
||||
|
||||
UARTs
|
||||
=====
|
||||
|
||||
The nr5m100-nexys4 design has an onboard USB-UART providing an RS-232 interface
|
||||
via the same USB cable that is used to program the FPGA. The core proivdes a
|
||||
fixed 8-Data bit, 1 stop bit, no parity UART connected to this intrface.
|
||||
|
||||
UART PINS
|
||||
---------
|
||||
|
||||
UART1
|
||||
RX FPGA C4 (USB UART device)
|
||||
TX FPGA D4 (USB UART device)
|
||||
|
||||
Default USART/UART Configuration
|
||||
--------------------------------
|
||||
|
||||
UART1 is enabled in all configurations (see */defconfig).
|
||||
|
||||
Configurations
|
||||
==============
|
||||
|
||||
Each nr5m100-nexys4 configuration is maintained in a sub-directory and
|
||||
can be selected as follow:
|
||||
|
||||
tools/configure.sh nr5m100-nexys4:<subdir>
|
||||
|
||||
Where <subdir> is one of the following:
|
||||
|
||||
nsh
|
||||
---
|
||||
This is an NSH example that uses UART1 as the console. UART1 is connected
|
||||
to the USB UART bridge on the FPGA board.
|
||||
@@ -1,55 +0,0 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_NSH_DISABLE_IFCONFIG is not set
|
||||
# CONFIG_NSH_DISABLE_LOSMART is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="risc-v"
|
||||
CONFIG_ARCH_BOARD="nr5m100-nexys4"
|
||||
CONFIG_ARCH_BOARD_NR5M100_NEXYS4=y
|
||||
CONFIG_ARCH_CHIP="nr5m100"
|
||||
CONFIG_ARCH_CHIP_NR5=y
|
||||
CONFIG_ARCH_CHIP_NR5M100=y
|
||||
CONFIG_ARCH_RISCV=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=15000
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DEV_ZERO=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LIBC_PERROR_STDOUT=y
|
||||
CONFIG_LIBC_STRERROR=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NR5_TIMER1=y
|
||||
CONFIG_NR5_TIMER2=y
|
||||
CONFIG_NR5_UART1=y
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_DISABLE_MKRD=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NSH_STRERROR=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_RV32IM_HW_MULDIV=y
|
||||
CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT=y
|
||||
CONFIG_START_DAY=27
|
||||
CONFIG_START_YEAR=2013
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_UART1_SERIAL_CONSOLE=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
@@ -1,168 +0,0 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/nr5m100/nr5m100-nexys4/include/board.h
|
||||
* include/arch/board/board.h
|
||||
*
|
||||
* Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Modified for NR5M100:
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
* Author: Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_RISC-V_NR5M100_NR5M100_NEXYS4_INCLUDE_BOARD_H
|
||||
#define __BOARDS_RISC-V_NR5M100_NR5M100_NEXYS4_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include "nr5.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* The NR5M100_Nexys4 system uses a 100 MHz main oscillator */
|
||||
|
||||
#define NR5_HCLK_FREQUENCY 100000000ul
|
||||
#define NR5_SCLK_FREQUENCY 100000000ul
|
||||
|
||||
/* Timer Frequencies are the same as the HCLK frequency */
|
||||
|
||||
#define NR5_TIMER_FREQUENCY NR5_HCLK_FREQUENCY
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
|
||||
/* If CONFIG_ARCH_LEDS is not defined, then the user can control
|
||||
* the LEDs in any way.
|
||||
* The following definitions are used to access individual LEDs.
|
||||
*/
|
||||
|
||||
/* LED index values for use with stm32_setled() */
|
||||
|
||||
#if 0
|
||||
#define BOARD_LED1 0
|
||||
#define BOARD_LED2 1
|
||||
#define BOARD_LED3 2
|
||||
#define BOARD_LED4 3
|
||||
#endif
|
||||
#define BOARD_NLEDS 0
|
||||
|
||||
#if 1
|
||||
#define BOARD_LED_GREEN BOARD_LED1
|
||||
#define BOARD_LED_ORANGE BOARD_LED2
|
||||
#define BOARD_LED_RED BOARD_LED3
|
||||
#define BOARD_LED_BLUE BOARD_LED4
|
||||
|
||||
/* LED bits for use with nr5_setleds() */
|
||||
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
#define BOARD_LED2_BIT (1 << BOARD_LED2)
|
||||
#define BOARD_LED3_BIT (1 << BOARD_LED3)
|
||||
#define BOARD_LED4_BIT (1 << BOARD_LED4)
|
||||
|
||||
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs
|
||||
* on the board.
|
||||
* The following definitions describe how NuttX controls the LEDs:
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0 /* LED1 */
|
||||
#define LED_HEAPALLOCATE 1 /* LED2 */
|
||||
#define LED_IRQSENABLED 2 /* LED1 + LED2 */
|
||||
#define LED_STACKCREATED 3 /* LED3 */
|
||||
#define LED_INIRQ 4 /* LED1 + LED3 */
|
||||
#define LED_SIGNAL 5 /* LED2 + LED3 */
|
||||
#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
|
||||
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
#define BUTTON_USER 0
|
||||
|
||||
#define NUM_BUTTONS 5
|
||||
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
#endif /* 0 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nr5_ledinit, nr5_setled, and nr5_setleds
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_ARCH_LEDS is defined,
|
||||
* then NuttX will control the on-board LEDs.
|
||||
* If CONFIG_ARCH_LEDS is not defined,
|
||||
* then the following interfacesare available to
|
||||
* control the LEDs from user applications.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_LEDS
|
||||
void nr5_ledinit(void);
|
||||
void nr5_setled(int led, bool ledon);
|
||||
void nr5_setleds(uint8_t ledset);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_RISC-V_NR5M100_NR5M100_NEXYS4_INCLUDE_BOARD_H */
|
||||
@@ -1,64 +0,0 @@
|
||||
############################################################################
|
||||
# boards/risc-v/nr5m100/nr5m100-nexys4/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}"
|
||||
else
|
||||
ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
ASARCHCPUFLAGS += -Wa,-g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS)
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs -melf32lriscv
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g -melf32lriscv
|
||||
endif
|
||||
@@ -1,332 +0,0 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/nr5m100/nr5m100-nexys4/scripts/ld.script
|
||||
*
|
||||
* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Ken Pettit.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Ken Pettit <pettitkd@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/*======================================================================*/
|
||||
/* Linker script for nr5m100_nexys board */
|
||||
/*======================================================================*/
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* Setup */
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/* The OUTPUT_ARCH command specifies the machine architecture where the
|
||||
* argument is one of the names used in the BFD library. More
|
||||
* specifically one of the entries in bfd/cpu-mips.c
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
/* Define the memory regions were we put stuff */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 384K
|
||||
}
|
||||
|
||||
stack_size = 4096;
|
||||
|
||||
/* Define the beginning and ending stack */
|
||||
|
||||
__stack_start = ORIGIN(sram) + LENGTH(sram);
|
||||
__stack_end = __stack_start - stack_size;
|
||||
|
||||
/* The ENTRY command specifies the entry point (ie. first instruction to
|
||||
* execute). The symbol _start is defined in crt0.S
|
||||
*/
|
||||
|
||||
ENTRY( __reset )
|
||||
|
||||
/* The GROUP command is special since the listed archives will be
|
||||
* searched repeatedly until there are no new undefined references. We
|
||||
* need this since -lc depends on -lgloss and -lgloss depends on -lc. I
|
||||
* thought gcc would automatically include -lgcc when needed, but
|
||||
* idt32.ld includes it explicitly here and I was seeing link errors
|
||||
* without it.
|
||||
*/
|
||||
|
||||
/*GROUP( -lc -lgloss -lgcc ) */
|
||||
GROUP( -lc )
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* Sections */
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/* This is where we specify how the input sections map to output
|
||||
* sections. The .= commands set the location counter, and the
|
||||
* sections are inserted in increasing address order according to the
|
||||
* location counter. The following statement will take all of the .bar
|
||||
* input sections and reloate them into the .foo output section which
|
||||
* starts at address 0x1000.
|
||||
*
|
||||
* . = 0.x1000;
|
||||
* .foo : { *(.bar) }
|
||||
*
|
||||
* If we wrap an input specification with a KEEP command then it
|
||||
* prevents it from being eliminted during "link-time garbage
|
||||
* collection". I'm not sure what this is, so I just followed what was
|
||||
* done in idt32.ld.
|
||||
*
|
||||
* We can also set a global external symbol to a specific address in the
|
||||
* output binary with this syntax:
|
||||
*
|
||||
* _etext = .;
|
||||
* PROVIDE( etext = . );
|
||||
*
|
||||
* This will set the global symbol _ftext to the current location. If we
|
||||
* wrap this in a PROVIDE command, the symbol will only be set if it is
|
||||
* not defined. We do this with symbols which don't begin with an
|
||||
* underscore since technically in ansi C someone might have a function
|
||||
* with the same name (eg. etext).
|
||||
*
|
||||
* If we need to label the beginning of a section we need to make sure
|
||||
* that the linker doesn't insert an orphan section between where we
|
||||
* set the symbol and the actual beginning of the section. We can do that
|
||||
* by assigning the location dot to itself.
|
||||
*
|
||||
* . = .
|
||||
* _ftext = .;
|
||||
* .text :
|
||||
* { }
|
||||
*
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Startup vectors
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
. = 0x20000000;
|
||||
_vectors = .;
|
||||
|
||||
/* vectors: Program code section */
|
||||
|
||||
.vectors :
|
||||
{
|
||||
*(.text.vec)
|
||||
*(.text.vec.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
}
|
||||
_evectors = .;
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Code and read-only segment */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
/* Beginning of code and text segment */
|
||||
|
||||
. = 0x20000030;
|
||||
|
||||
_ftext = .;
|
||||
PROVIDE( eprol = . );
|
||||
|
||||
/* text: Program code section */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
}
|
||||
|
||||
/* init: Code to execute before main (called by crt0.S) */
|
||||
|
||||
.init :
|
||||
{
|
||||
KEEP( *(.init) )
|
||||
}
|
||||
|
||||
/* fini: Code to execute after main (called by crt0.S) */
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP( *(.fini) )
|
||||
}
|
||||
|
||||
/* rodata: Read-only data */
|
||||
|
||||
_rodata = .;
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
}
|
||||
|
||||
/* End of code and read-only segment */
|
||||
|
||||
PROVIDE( etext = . );
|
||||
_etext = .;
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Global constructor/destructor segment */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array ))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array ))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Other misc gcc segments (this was in idt32.ld) */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
/* I am not quite sure about these sections but it seems they are for
|
||||
* C++ exception handling. I think .jcr is for "Java Class
|
||||
* Registration" but it seems to end up in C++ binaries as well.
|
||||
*/
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
.eh_frame : { KEEP( *(.eh_frame) ) }
|
||||
.gcc_except_table : { *(.gcc_except_table) }
|
||||
.jcr : { KEEP (*(.jcr)) }
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Initialized data segment */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
/* Start of initialized data segment */
|
||||
|
||||
. = ALIGN(16);
|
||||
_fdata = .;
|
||||
|
||||
/* data: Writable data */
|
||||
|
||||
_sdata = .;
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
}
|
||||
|
||||
/* End of initialized data segment */
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE( edata = . );
|
||||
_edata = .;
|
||||
|
||||
/* Have _gp point to middle of sdata/sbss to maximize displacement range */
|
||||
|
||||
. = ALIGN(16);
|
||||
_gp = . + 0x7FF0;
|
||||
|
||||
/* Writable small data segment */
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.srodata.*)
|
||||
. = ALIGN(16);
|
||||
*(.gnu.linkonce.s.*)
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Uninitialized data segment */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
||||
/* Start of uninitialized data segment */
|
||||
|
||||
. = ALIGN(8);
|
||||
_fbss = .;
|
||||
|
||||
/* Writable uninitialized small data segment */
|
||||
|
||||
.sbss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
}
|
||||
|
||||
/* bss: Uninitialized writeable data section */
|
||||
|
||||
_bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
_bss_end = .;
|
||||
_ebss = .;
|
||||
|
||||
/* End of uninitialized data segment (used by syscalls.c for heap) */
|
||||
|
||||
. = ALIGN(16);
|
||||
PROVIDE( end = . );
|
||||
_end = ALIGN(16);
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -1,63 +0,0 @@
|
||||
############################################################################
|
||||
# boards/risc-v/nr5m100/nr5m100-nexys4/scripts/nr5m1xx.cfg
|
||||
#
|
||||
# Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
# Author: Ken Pettit <pettitkd@gmail.com>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
proc init_board {} {
|
||||
reset_config srst_only
|
||||
}
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME nr5m1xx
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x17a1092d
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x5 -irmask 0x1f -expected-id $_CPUTAPID
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME riscv -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20018000 -work-area-size 0x2000 -work-area-backup 0
|
||||
@@ -1,60 +0,0 @@
|
||||
############################################################################
|
||||
# boards/risc-v/nr5m100/nr5m100-nexys4/scripts/openocd.cfg
|
||||
#
|
||||
# Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
# Author: Ken Pettit <pettitkd@gmail.com>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
#======================================
|
||||
#
|
||||
# Define the interface
|
||||
#
|
||||
#=====================================
|
||||
|
||||
interface jlink
|
||||
adapter_khz 2000
|
||||
|
||||
#======================================
|
||||
#
|
||||
# Define the target
|
||||
#
|
||||
#=====================================
|
||||
|
||||
source [find nr5m1xx.cfg]
|
||||
|
||||
#======================================
|
||||
#
|
||||
# Init and halt the processor
|
||||
#
|
||||
#=====================================
|
||||
|
||||
init
|
||||
reset halt
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user