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Update kconfig2html.c

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Fix nuttx coding style
This commit is contained in:
simbit18
2023-12-14 15:22:07 +01:00
committed by Xiang Xiao
parent e03599d9ae
commit c494ce4a96
78 changed files with 193 additions and 154 deletions
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arch/arm/include/cxd56xx/gnss_type.h
+1 -1
View File
@@ -223,7 +223,7 @@ extern "C"
/* GNSS positionig data elements */
/* Day (UTC) */
/* Day (UTC) */
struct cxd56_gnss_date_s
{
arch/arm/include/eoss3/chip.h
+1 -1
View File
@@ -40,4 +40,4 @@
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt pri used */
#endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */
#endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */
arch/arm/include/imxrt/imxrt105x_irq.h
+1 -1
View File
@@ -136,7 +136,7 @@
#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */
#define IMXRT_IRQ_RESERVED99 (IMXRT_IRQ_EXTINT + 99) /* Reserved */
#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
arch/arm/include/imxrt/imxrt106x_irq.h
+1 -1
View File
@@ -136,7 +136,7 @@
#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */
#define IMXRT_IRQ_RESERVED99 (IMXRT_IRQ_EXTINT + 99) /* Reserved */
#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
arch/arm/include/kinetis/kinetis_k40irq.h
+1 -1
View File
@@ -93,7 +93,7 @@
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST + 39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST + 40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST + 41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST + 43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST + 44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 45) /* 45: UART0 status */
arch/arm/include/kinetis/kinetis_k60irq.h
+1 -1
View File
@@ -93,7 +93,7 @@
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST + 39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST + 40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST + 41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST + 43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST + 44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 45) /* 45: UART0 status */
arch/arm/include/samv7/same70_irq.h
+2 -2
View File
@@ -153,11 +153,11 @@
#define SAM_IRQ_MCAN01 (SAM_IRQ_EXTINT+SAM_PID_MCAN01) /* CAN0 IRQ line 1 */
#define SAM_IRQ_MCAN10 (SAM_IRQ_EXTINT+SAM_PID_MCAN10) /* CAN1 IRQ line 0 */
#define SAM_IRQ_MCAN11 (SAM_IRQ_EXTINT+SAM_PID_MCAN11) /* CAN1 IRQ line 1 */
#define SAM_IRQ_EMAC0 (SAM_IRQ_EXTINT+SAM_PID_EMAC0) /* Ethernet MAC */
#define SAM_IRQ_EMAC0 (SAM_IRQ_EXTINT+SAM_PID_EMAC0) /* Ethernet MAC */
#define SAM_IRQ_AFEC1 (SAM_IRQ_EXTINT+SAM_PID_AFEC1) /* Analog Front End 1 */
#define SAM_IRQ_TWIHS2 (SAM_IRQ_EXTINT+SAM_PID_TWIHS2) /* Two-Wire Interface 2 */
#define SAM_IRQ_SPI1 (SAM_IRQ_EXTINT+SAM_PID_SPI1) /* Serial Peripheral Interface 1 */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+SAM_PID_QSPI) /* Quad I/O Serial Peripheral Interface */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+SAM_PID_QSPI) /* Quad I/O Serial Peripheral Interface */
#define SAM_IRQ_UART2 (SAM_IRQ_EXTINT+SAM_PID_UART2) /* Universal Asynchronous Receiver Transmitter 2 */
#define SAM_IRQ_UART3 (SAM_IRQ_EXTINT+SAM_PID_UART3) /* Universal Asynchronous Receiver Transmitter 3 */
#define SAM_IRQ_UART4 (SAM_IRQ_EXTINT+SAM_PID_UART4) /* Universal Asynchronous Receiver Transmitter 4 */
arch/arm/include/samv7/samv71_irq.h
+2 -2
View File
@@ -153,11 +153,11 @@
#define SAM_IRQ_MCAN01 (SAM_IRQ_EXTINT+SAM_PID_MCAN01) /* CAN0 IRQ line 1 */
#define SAM_IRQ_MCAN10 (SAM_IRQ_EXTINT+SAM_PID_MCAN10) /* CAN1 IRQ line 0 */
#define SAM_IRQ_MCAN11 (SAM_IRQ_EXTINT+SAM_PID_MCAN11) /* CAN1 IRQ line 1 */
#define SAM_IRQ_EMAC0 (SAM_IRQ_EXTINT+SAM_PID_EMAC0) /* Ethernet MAC */
#define SAM_IRQ_EMAC0 (SAM_IRQ_EXTINT+SAM_PID_EMAC0) /* Ethernet MAC */
#define SAM_IRQ_AFEC1 (SAM_IRQ_EXTINT+SAM_PID_AFEC1) /* Analog Front End 1 */
#define SAM_IRQ_TWIHS2 (SAM_IRQ_EXTINT+SAM_PID_TWIHS2) /* Two-Wire Interface 2 */
#define SAM_IRQ_SPI1 (SAM_IRQ_EXTINT+SAM_PID_SPI1) /* Serial Peripheral Interface 1 */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+SAM_PID_QSPI) /* Quad I/O Serial Peripheral Interface */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+SAM_PID_QSPI) /* Quad I/O Serial Peripheral Interface */
#define SAM_IRQ_UART2 (SAM_IRQ_EXTINT+SAM_PID_UART2) /* Universal Asynchronous Receiver Transmitter 2 */
#define SAM_IRQ_UART3 (SAM_IRQ_EXTINT+SAM_PID_UART3) /* Universal Asynchronous Receiver Transmitter 3 */
#define SAM_IRQ_UART4 (SAM_IRQ_EXTINT+SAM_PID_UART4) /* Universal Asynchronous Receiver Transmitter 4 */
arch/arm/src/at32/at32_can_sock.c
+3 -3
View File
@@ -1149,10 +1149,10 @@ static int at32can_txavail(struct net_driver_s *dev)
static int at32can_netdev_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg)
{
#if 0
#if 0
struct at32_can_s *priv = (struct at32_can_s *)dev->d_private;
#endif
int ret = OK;
#endif
int ret = OK;
switch (cmd)
{
arch/arm/src/at32/at32_eth.c
+1 -1
View File
@@ -4020,7 +4020,7 @@ void arm_netinitialize(void)
#ifdef CONFIG_AT32_CAN2
at32_cansockinitialize(2);
#endif
#endif
#endif
}
arch/arm/src/at32/at32_serial.c
+1 -1
View File
@@ -105,7 +105,7 @@
DMA_CCR_MSIZE_8BITS | \
CONFIG_USART_RXDMAPRIO)
#endif /* SERIAL_HAVE_RXDMA */
#endif /* SERIAL_HAVE_RXDMA */
#ifdef SERIAL_HAVE_TXDMA
arch/arm/src/at32/at32f43xx_flash.c
+2 -2
View File
@@ -102,7 +102,7 @@ static void flash_unlock(void)
putreg32(FLASH_KEY2, AT32_FLASH_UNLOCK2);
}
}
#endif
#endif
}
static void flash_lock(void)
@@ -112,7 +112,7 @@ static void flash_lock(void)
#ifdef AT32_FLASH_BANK2_START
if (AT32_FLASH_BANK2_START < AT32_FLASH_NPAGES)
modifyreg32(AT32_FLASH_CTRL2, 0, FLASH_CTRL_OPLK);
#endif
#endif
}
#if defined(CONFIG_AT32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
arch/arm/src/cxd56xx/cxd56_nxaudio.c
+4 -4
View File
@@ -352,13 +352,13 @@ static int cxd56_start(struct audio_lowerhalf_s *lower,
#ifndef CONFIG_AUDIO_EXCLUDE_STOP
static int cxd56_stop(struct audio_lowerhalf_s *lower,
void *session);
#endif /* CONFIG_AUDIO_EXCLUDE_STOP */
#endif /* CONFIG_AUDIO_EXCLUDE_STOP */
#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME
static int cxd56_pause(struct audio_lowerhalf_s *lower,
void *session);
static int cxd56_resume(struct audio_lowerhalf_s *lower,
void *session);
#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */
#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */
static int cxd56_reserve(struct audio_lowerhalf_s *lower,
void **session);
static int cxd56_release(struct audio_lowerhalf_s *lower,
@@ -370,11 +370,11 @@ static int cxd56_configure(struct audio_lowerhalf_s *lower,
static int cxd56_start(struct audio_lowerhalf_s *lower);
#ifndef CONFIG_AUDIO_EXCLUDE_STOP
static int cxd56_stop(struct audio_lowerhalf_s *lower);
#endif /* CONFIG_AUDIO_EXCLUDE_STOP */
#endif /* CONFIG_AUDIO_EXCLUDE_STOP */
#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME
static int cxd56_pause(struct audio_lowerhalf_s *lower);
static int cxd56_resume(struct audio_lowerhalf_s *lower);
#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */
#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */
static int cxd56_reserve(struct audio_lowerhalf_s *lower);
static int cxd56_release(struct audio_lowerhalf_s *lower);
#endif /* CONFIG_AUDIO_MULTI_SESSION */
arch/arm/src/cxd56xx/cxd56_nxaudio.h
+1 -1
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@@ -282,7 +282,7 @@ struct cxd56_dev_s
uint32_t samplerate; /* Sample rate */
#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
int16_t volume; /* Output volume {0..63} */
#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
uint8_t channels; /* Number of channels (1..8) */
uint16_t mic_gain; /* Mic gain */
arch/arm/src/imxrt/imxrt_lpspi.c
+1 -1
View File
@@ -1584,7 +1584,7 @@ static void imxrt_lpspi_exchange(struct spi_dev_s *dev,
}
}
#endif /* CONFIG_IMXRT_SPI_DMA */
#endif /* CONFIG_IMXRT_SPI_DMA */
/****************************************************************************
* Name: imxrt_lpspi_sndblock
arch/arm/src/kinetis/kinetis_spi.c
+1 -1
View File
@@ -1275,7 +1275,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
0);
}
#endif /* CONFIG_KINETIS_SPI_DMA */
#endif /* CONFIG_KINETIS_SPI_DMA */
/****************************************************************************
* Name: spi_sndblock
*
arch/arm/src/nrf53/nrf53_adc.h
+1 -1
View File
@@ -159,4 +159,4 @@ struct adc_dev_s *nrf53_adcinitialize(
const struct nrf53_adc_channel_s *chan,
int channels);
#endif /* __ARCH_ARM_SRC_NRF53_NRF53_ADC_H */
#endif /* __ARCH_ARM_SRC_NRF53_NRF53_ADC_H */
arch/arm/src/nrf53/nrf53_qspi.c
+1 -1
View File
@@ -135,7 +135,7 @@ static const struct qspi_ops_s g_qspi_ops =
.setbits = nrf53_qspi_setbits,
#ifdef CONFIG_QSPI_HWFEATURES
.hwfeatures = NULL,
#endif
#endif
.command = nrf53_qspi_command,
.memory = nrf53_qspi_memory,
.alloc = nrf53_qspi_alloc,
arch/arm/src/nrf91/nrf91_spu.c
+1 -1
View File
@@ -169,7 +169,7 @@ static void nrf91_spu_periph(void)
modifyreg32(NRF91_SPU_GPIOPORTPERM(0), 0xffffffff, 0);
}
#endif /* NRF91_CONFIG_NONSECURE */
#endif /* NRF91_CONFIG_NONSECURE */
/****************************************************************************
* Public Functions
arch/arm/src/phy62xx/core_bumbee_m0.h
+1 -1
View File
@@ -102,4 +102,4 @@ extern "C"
}
#endif
#endif /* PHY_BUMBEE_M0 */
#endif /* PHY_BUMBEE_M0 */
arch/arm/src/rp2040/rp2040_ws2812.c
+6 -6
View File
@@ -412,17 +412,17 @@ static ssize_t my_write(struct file *filep,
/* Copy swapping WWRRGGBB to GGRRBBWW */
#ifdef CONFIG_BIG_ENDIAN
#ifdef CONFIG_BIG_ENDIAN
xfer_p[3] = *data++;
xfer_p[1] = *data++;
xfer_p[0] = *data++;
xfer_p[2] = *data++;
#else /* CONFIG_BIG_ENDIAN */
#else /* CONFIG_BIG_ENDIAN */
xfer_p[1] = *data++;
xfer_p[3] = *data++;
xfer_p[2] = *data++;
xfer_p[0] = *data++;
#endif /* CONFIG_BIG_ENDIAN */
#endif /* CONFIG_BIG_ENDIAN */
xfer_p += 4;
position += 4;
@@ -490,17 +490,17 @@ static ssize_t my_read(struct file *filep,
/* Copy swapping GGRRBBWW to WWRRGGBB */
#ifdef CONFIG_BIG_ENDIAN
#ifdef CONFIG_BIG_ENDIAN
*data++ = xfer_p[3];
*data++ = xfer_p[1];
*data++ = xfer_p[0];
*data++ = xfer_p[2];
#else /* CONFIG_BIG_ENDIAN */
#else /* CONFIG_BIG_ENDIAN */
*data++ = xfer_p[1];
*data++ = xfer_p[3];
*data++ = xfer_p[2];
*data++ = xfer_p[0];
#endif /* CONFIG_BIG_ENDIAN */
#endif /* CONFIG_BIG_ENDIAN */
xfer_p += 4;
position += 4;
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
+1 -1
View File
@@ -1763,7 +1763,7 @@ static void s32k1xx_lpspi_exchange(struct spi_dev_s *dev,
(uintptr_t)rxbuffer + nbytes);
}
#endif /* CONFIG_S32K1XX_SPI_DMA */
#endif /* CONFIG_S32K1XX_SPI_DMA */
/****************************************************************************
* Name: s32k1xx_lpspi_sndblock
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
+1 -1
View File
@@ -1827,7 +1827,7 @@ static void s32k3xx_lpspi_exchange(struct spi_dev_s *dev,
}
}
#endif /* CONFIG_S32K3XX_SPI_DMA */
#endif /* CONFIG_S32K3XX_SPI_DMA */
/****************************************************************************
* Name: s32k3xx_lpspi_sndblock
arch/arm/src/sama5/sam_spi.c
+1 -1
View File
@@ -302,7 +302,7 @@ static const struct spi_ops_s g_spi0ops =
.setfrequency = spi_setfrequency,
#ifdef CONFIG_SPI_DELAY_CONTROL
.setdelay = spi_setdelay,
#endif
#endif
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
arch/arm/src/samv7/hardware/sam_pwm.h
+1 -1
View File
@@ -463,4 +463,4 @@
#define LEBR_PWMHFEN (1 << 18) /* Bit 17: PWMH Falling Edge Enable */
#define LEBR_PWMHREN (1 << 19) /* Bit 18: PWMH Rising Edge Enable */
#endif /* CONFIG_SAMV7_PWM */
#endif /* CONFIG_SAMV7_PWM */
arch/arm/src/samv7/sam_qspi_spi.c
+1 -1
View File
@@ -741,7 +741,7 @@ static void qspi_spi_recvblock(struct spi_dev_s *dev, void *buffer,
qspi_spi_exchange(dev, NULL, buffer, nwords);
}
#endif /* CONFIG_SPI_EXCHANGE */
#endif /* CONFIG_SPI_EXCHANGE */
/****************************************************************************
* Public Functions
arch/arm/src/stm32/hardware/stm32_dbgmcu.h
+2 -2
View File
@@ -145,7 +145,7 @@
# define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */
# define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */
#endif
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */
#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3
@@ -178,7 +178,7 @@
# define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */
# define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */
#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */
/****************************************************************************
* Public Types
arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
+1 -1
View File
@@ -113,4 +113,4 @@
#define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */
#define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_COMP_H */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_COMP_H */
arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h
+1 -1
View File
@@ -164,4 +164,4 @@
#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status */
#define COMP_CSR_LOCK (1 << 31) /* Bit 31: Register lock */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_COMP_H */
arch/arm/src/stm32/stm32_fdcan_sock.c
+1 -1
View File
@@ -3191,7 +3191,7 @@ static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd,
return ret;
}
#endif /* CONFIG_NETDEV_IOCTL */
#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Public Functions
arch/arm/src/stm32/stm32_foc.c
+3 -3
View File
@@ -161,7 +161,7 @@
# if CONFIG_STM32_TIM1_MODE != 2
# error TIM1 must be configured in center-aligned mode 1
# endif
#endif /* CONFIG_STM32_FOC_FOC0 */
#endif /* CONFIG_STM32_FOC_FOC0 */
/* FOC1 always use TIMER8 for PWM */
@@ -901,7 +901,7 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 =
.cntr = 0,
.lock = NXMUTEX_INITIALIZER,
};
# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */
# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */
# ifdef CONFIG_STM32_HAVE_IP_ADC_V2
# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2)
@@ -2457,7 +2457,7 @@ struct adc_dev_s *stm32_foc_adc_init(struct stm32_foc_adc_s *adc_cfg)
{
adc_chan[i] = adc_cfg->chan[i - 1];
}
#endif /* CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND */
#endif /* CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND */
/* Get the ADC interface */
arch/arm/src/stm32/stm32_serial.c
+2 -2
View File
@@ -218,7 +218,7 @@
CONFIG_USART_RXDMAPRIO)
# endif
#endif /* SERIAL_HAVE_RXDMA */
#endif /* SERIAL_HAVE_RXDMA */
#ifdef SERIAL_HAVE_TXDMA
@@ -368,7 +368,7 @@
# error "Unknown STM32 DMA"
# endif
#endif /* SERIAL_HAVE_TXDMA */
#endif /* SERIAL_HAVE_TXDMA */
/* Power management definitions */
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+1 -1
View File
@@ -226,7 +226,7 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif /* CONFIG_STM32F7_OTGFSHS */
#endif /* CONFIG_STM32F7_OTGFSHS */
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
arch/arm/src/stm32h7/stm32_rcc.c
+1 -1
View File
@@ -120,7 +120,7 @@ void stm32_clockconfig(void)
stm32_stdclockconfig();
# endif
#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */
#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */
/* Enable peripheral clocking */
arch/arm/src/stm32h7/stm32_spi_slave.c
+3 -3
View File
@@ -121,7 +121,7 @@
# if SPI123_KERNEL_CLOCK_FREQ > 200000000
# error Not supported SPI123 frequency
# endif
#endif /* SPI123 */
#endif /* SPI123 */
#if defined(CONFIG_STM32H7_SPI4_SLAVE) || defined(CONFIG_STM32H7_SPI5_SLAVE)
# if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB
@@ -132,7 +132,7 @@
# if SPI45_KERNEL_CLOCK_FREQ > 100000000
# error Not supported SPI45 frequency
# endif
#endif /* SPI45 */
#endif /* SPI45 */
#if defined(CONFIG_STM32H7_SPI6_SLAVE)
# if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4
@@ -143,7 +143,7 @@
# if SPI6_KERNEL_CLOCK_FREQ > 100000000
# error Not supported SPI6 frequency
# endif
#endif /* SPI6 */
#endif /* SPI6 */
#if defined (CONFIG_STM32H7_SPI_SLAVE_QSIZE)
# if CONFIG_STM32H7_SPI_SLAVE_QSIZE > 65535
arch/arm/src/stm32l4/stm32l4_adc.c
+6 -6
View File
@@ -1169,7 +1169,7 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable)
}
}
}
#endif /* ADC_HAVE_INJECTED */
#endif /* ADC_HAVE_INJECTED */
/****************************************************************************
* Name: adc_rccreset
@@ -2279,7 +2279,7 @@ static int adc3_interrupt(int irq, void *context, void *arg)
return OK;
}
#endif
#endif /* CONFIG_STM32L4_ADC_NOIRQ */
#endif /* CONFIG_STM32L4_ADC_NOIRQ */
#ifdef ADC_HAVE_DMA
/****************************************************************************
@@ -2408,7 +2408,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle,
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN);
}
#endif
#endif /* ADC_HAVE_DMA */
#endif /* ADC_HAVE_DMA */
#ifdef CONFIG_STM32L4_ADC_LL_OPS
@@ -2589,7 +2589,7 @@ static void adc_llops_dma_stop(struct stm32_adc_dev_s *adc)
}
}
#endif /* ADC_HAVE_DMA */
#endif /* ADC_HAVE_DMA */
/****************************************************************************
* Name: adc_llops_extsel_set
@@ -2644,7 +2644,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev,
adc_inj_startconv(priv, enable);
}
#endif /* ADC_HAVE_INJECTED */
#endif /* ADC_HAVE_INJECTED */
/****************************************************************************
* Name: adc_llops_dumpregs
@@ -2657,7 +2657,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev)
adc_dumpregs(priv);
}
#endif /* CONFIG_STM32L4_ADC_LL_OPS */
#endif /* CONFIG_STM32L4_ADC_LL_OPS */
/****************************************************************************
* Public Functions
arch/arm/src/stm32l4/stm32l4_adc.h
+1 -1
View File
@@ -582,7 +582,7 @@ struct stm32_adc_ops_s
void (*dump_regs)(struct stm32_adc_dev_s *dev);
};
#endif /* CONFIG_STM32L4_ADC_LL_OPS */
#endif /* CONFIG_STM32L4_ADC_LL_OPS */
/****************************************************************************
* Public Function Prototypes
arch/mips/src/pic32mx/pic32mx_decodeirq.c
+1 -1
View File
@@ -24,7 +24,7 @@
#include <nuttx/config.h>
#include <debug.h>
#include <debug.h>
#include <stdint.h>
#include <assert.h>
arch/mips/src/pic32mz/pic32mz_decodeirq.c
+1 -1
View File
@@ -24,7 +24,7 @@
#include <nuttx/config.h>
#include <debug.h>
#include <debug.h>
#include <stdint.h>
#include <assert.h>
arch/risc-v/include/litex/irq.h
+1 -1
View File
@@ -29,7 +29,7 @@
#include CONFIG_LITEX_CUSTOM_IRQ_DEFINITIONS_PATH
#else
#include <arch/mode.h>
#include <arch/mode.h>
/****************************************************************************
* Pre-processor Definitions
arch/xtensa/src/esp32/esp32_wlan.c
+2 -2
View File
@@ -1594,7 +1594,7 @@ static int wlan_ioctl(struct net_driver_s *dev,
return ret;
}
#endif /* CONFIG_NETDEV_IOCTL */
#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Name: esp32_net_initialize
@@ -1923,4 +1923,4 @@ int esp32_wlan_softap_initialize(void)
}
#endif /* ESP32_WLAN_HAS_SOFTAP */
#endif /* CONFIG_ESP32_WIFI */
#endif /* CONFIG_ESP32_WIFI */
arch/xtensa/src/esp32s2/esp32s2_i2s.c
+2 -2
View File
@@ -356,12 +356,12 @@ static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
static const struct i2s_ops_s g_i2sops =
{
#ifdef I2S_HAVE_TX
#ifdef I2S_HAVE_TX
.i2s_txchannels = i2s_txchannels,
.i2s_txsamplerate = i2s_txsamplerate,
.i2s_txdatawidth = i2s_txdatawidth,
.i2s_send = i2s_send,
#endif /* I2S_HAVE_TX */
#endif /* I2S_HAVE_TX */
#ifdef I2S_HAVE_RX
.i2s_rxchannels = i2s_rxchannels,
arch/xtensa/src/esp32s3/esp32s3_wlan.c
+2 -2
View File
@@ -1258,7 +1258,7 @@ static int wlan_ioctl(struct net_driver_s *dev,
return ret;
}
#endif /* CONFIG_NETDEV_IOCTL */
#endif /* CONFIG_NETDEV_IOCTL */
/****************************************************************************
* Name: esp32s3_net_initialize
@@ -1595,4 +1595,4 @@ int esp32s3_wlan_softap_initialize(void)
}
#endif /* ESP32S3_WLAN_HAS_SOFTAP */
#endif /* CONFIG_ESP32S3_WIFI */
#endif /* CONFIG_ESP32S3_WIFI */
boards/arm/at32/at32f437-mini/src/at32_gpio.c
+2 -2
View File
@@ -101,9 +101,9 @@ static const struct gpio_operations_s gpint_ops =
#if (BOARD_NGPIOIN > 0)
static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
{
#if 0
#if 0
GPIO_IN1,
#endif
#endif
};
static struct at32gpio_dev_s g_gpin[BOARD_NGPIOIN];
boards/arm/at32/at32f437-mini/src/at32_usb.c
+3 -3
View File
@@ -141,7 +141,7 @@ void at32_usbinitialize(void)
at32_configgpio(GPIO_OTGFS_VBUS);
at32_configgpio(GPIO_OTGFS_PWRON);
at32_configgpio(GPIO_OTGFS_OVER);
#endif
#endif
#endif
}
@@ -294,7 +294,7 @@ void at32_usbhost_vbusdrive(int iface, bool enable)
at32_gpiowrite(GPIO_OTGFS_PWRON, true);
}
#endif
#endif
}
#endif
@@ -320,7 +320,7 @@ int at32_setup_overcurrent(xcpt_t handler, void *arg)
{
#ifdef CONFIG_AT32_OTGFS_VBUS_CONTROL
return at32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
#endif
#endif
return 0;
}
boards/arm/cxd56xx/common/src/cxd56_bmi160_scu.c
+2 -2
View File
@@ -165,5 +165,5 @@ int board_bmi160_initialize(int bus)
return ret;
}
#endif /* CONFIG_SENSORS_BMI160_SCU_SPI */
#endif /* CONFIG_SENSORS_BMI160_SCU */
#endif /* CONFIG_SENSORS_BMI160_SCU_SPI */
#endif /* CONFIG_SENSORS_BMI160_SCU */
boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c
+2 -2
View File
@@ -46,11 +46,11 @@
#ifndef MIN
# define MIN(a,b) (((a) < (b)) ? (a) : (b))
#endif /* MIN */
#endif /* MIN */
#ifndef MAX
# define MAX(a,b) (((a) > (b)) ? (a) : (b))
#endif /* MAX */
#endif /* MAX */
/* Configurations */
boards/arm/cxd56xx/spresense/include/board_lcdpins.h
+1 -1
View File
@@ -143,4 +143,4 @@
#endif
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_BOARD_LCDPINS_H */
#endif /* __BOARDS_ARM_CXD56XX_SPRESENSE_INCLUDE_BOARD_LCDPINS_H */
boards/arm/imxrt/imxrt1064-evk/src/imxrt1064-evk.h
+1 -1
View File
@@ -329,7 +329,7 @@ int imxrt_flexspi_nor_initialize(void);
#ifdef HAVE_PROGMEM_CHARDEV
int imxrt_progmem_init(void);
#endif /* HAVE_PROGMEM_CHARDEV */
#endif /* HAVE_PROGMEM_CHARDEV */
#endif
#endif /* __ASSEMBLY__ */
boards/arm/imxrt/teensy-4.x/src/imxrt_autoleds.c
+1 -1
View File
@@ -161,4 +161,4 @@ void board_autoled_off(int led)
imxrt_gpio_write(GPIO_LED, false); /* Low illuminates */
}
#endif /* CONFIG_ARCH_LEDS */
#endif /* CONFIG_ARCH_LEDS */

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