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https://github.com/apache/nuttx.git
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Add clock configuration logic for the STM32F40
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4123 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -51,12 +51,12 @@
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#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */
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#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */
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#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */
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#define STM32_RCC_AH1BENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
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#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
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#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */
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#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
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#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
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#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
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#define STM32_RCC_AH1BLPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
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#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
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#define STM32_RCC_AH2BLPENR_OFFSET 0x0054 /* RCC AHB2 low power modeperipheral clock enable register */
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#define STM32_RCC_AH3BLPENR_OFFSET 0x0058 /* RCC AHB3 low power modeperipheral clock enable register */
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#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power modeperipheral clock enable register */
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@@ -82,7 +82,7 @@
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#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
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#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
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#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
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#define STM32_RCC_AH1BLPENR (STM32_RCC_BASE+STM32_RCC_AH1BLPENR_OFFSET)
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#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
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#define STM32_RCC_AH2BLPENR (STM32_RCC_BASE+STM32_RCC_AH2BLPENR)
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#define STM32_RCC_AH3BLPENR (STM32_RCC_BASE+STM32_RCC_AH3BLPENR_OFFSET)
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#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
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@@ -121,18 +121,23 @@
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#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT)
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# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
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#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
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#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLSRC)
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# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLSRC) /* 00: PLLP = 2 */
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# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLSRC) /* 01: PLLP = 4 */
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# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLSRC) /* 10: PLLP = 6 */
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# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLSRC) /* 11: PLLP = 8 */
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#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT)
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# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
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# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
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# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
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# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
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# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */
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#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S)
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* entry clock source */
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# define RCC_PLLCFG_PLLSRC_HSI (0)
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# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC
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#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider
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* (USB OTG FS, SDIO and RNG clocks) */
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#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
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# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
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#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */
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/* Clock configuration register */
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#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
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@@ -294,27 +299,27 @@
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/* AHB1 Peripheral Clock enable register */
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#define RCC_AH1BENR_GPIOEN(n) (1 << (n))
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#define RCC_AH1BENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
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#define RCC_AH1BENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
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#define RCC_AH1BENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
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#define RCC_AH1BENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
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#define RCC_AH1BENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
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#define RCC_AH1BENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
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#define RCC_AH1BENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
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#define RCC_AH1BENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
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#define RCC_AH1BENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
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#define RCC_AH1BENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
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#define RCC_AH1BENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
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#define RCC_AH1BENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
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#define RCC_AH1BENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
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#define RCC_AH1BENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
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#define RCC_AH1BENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
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#define RCC_AH1BENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
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#define RCC_AH1BENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
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#define RCC_AH1BENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
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#define RCC_AH1BENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
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#define RCC_AH1BENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
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#define RCC_AHB1ENR_GPIOEN(n) (1 << (n))
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#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
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#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
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#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
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#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
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#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
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#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
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#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
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#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
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#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
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#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
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#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
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#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
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#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
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#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
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#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
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#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
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#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
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#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
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#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
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#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
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/* AHB2 Peripheral Clock enable register */
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@@ -372,30 +377,30 @@
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/* RCC AHB1 low power modeperipheral clock enable register */
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#define RCC_AH1BLPENR_GPIOLPEN(n) (1 << (n))
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#define RCC_AH1BLPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
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#define RCC_AH1BLPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
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#define RCC_AH1BLPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
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#define RCC_AH1BLPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
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#define RCC_AH1BLPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
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#define RCC_AH1BLPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
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#define RCC_AH1BLPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
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#define RCC_AH1BLPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
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#define RCC_AH1BLPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
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#define RCC_AH1BLPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
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#define RCC_AH1BLPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
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#define RCC_AH1BLPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
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#define RCC_AH1BLPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
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#define RCC_AH1BLPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
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#define RCC_AH1BLPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
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#define RCC_AH1BLPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n))
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#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
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#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
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#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
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#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
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#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
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#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
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#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
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#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
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#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
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#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
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#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
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#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
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#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
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#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
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#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
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#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
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/* RCC AHB2 low power modeperipheral clock enable register */
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@@ -43,7 +43,8 @@
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway.
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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File diff suppressed because it is too large
Load Diff
@@ -287,7 +287,6 @@ STM3240G-EVAL-specific Configuration Options
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CONFIG_STM32_I2C3
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CONFIG_STM32_CAN1
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CONFIG_STM32_CAN2
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CONFIG_STM32_PWR
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CONFIG_STM32_DAC
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APB2
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@@ -54,48 +54,90 @@
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************************************************************************************/
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/* Clocking *************************************************************************/
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#warning "Revisit -- this is from the STM3210E-EVAL"
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/* Four clock sources are available on STM3240G-EVAL evaluation board for
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* STM32F407IGH6 and RTC embedded:
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*
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* X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is
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* provided by MCO pin of the MCU
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* X2, 26 MHz crystal for USB OTG HS PHY
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* X3, 32 kHz crystal for embedded RTC
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* X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed
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* from socket when internal RC clock is used.)
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*
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* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL)
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* PLLM : 25 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PPQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* On-board crystal frequency is 8MHz (HSE) */
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 25MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_BOARD_XTAL 25000000ul
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (25,000,000 / 25) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
|
||||
/* USB divider -- Divide PLL clock by 1.5 */
|
||||
|
||||
#define STM32_CFGR_USBPRE 0
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8 are on APB2, others on APB1 */
|
||||
* Note: TIM1,8 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
|
||||
@@ -157,7 +157,6 @@ CONFIG_STM32_I2C2=n
|
||||
CONFIG_STM32_I2C3=n
|
||||
CONFIG_STM32_CAN1=n
|
||||
CONFIG_STM32_CAN2=n
|
||||
CONFIG_STM32_PWR=n
|
||||
CONFIG_STM32_DAC=n
|
||||
# APB2:
|
||||
CONFIG_STM32_TIM1=n
|
||||
@@ -169,7 +168,7 @@ CONFIG_STM32_ADC2=n
|
||||
CONFIG_STM32_ADC3=n
|
||||
CONFIG_STM32_SDIO=n
|
||||
CONFIG_STM32_SPI1=n
|
||||
CONFIG_STM32_SYSCFG=n
|
||||
CONFIG_STM32_SYSCFG=y
|
||||
CONFIG_STM32_TIM9=n
|
||||
CONFIG_STM32_TIM10=n
|
||||
CONFIG_STM32_TIM11=n
|
||||
|
||||
Reference in New Issue
Block a user