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xtensa/espressif: Update common-source integration for Xtensa devices

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This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.

Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements

Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
  options from interrupt sources to CPU interrupts, providing flexibility
  required by modern peripherals. Although this introduces breaking changes
  to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
  Kconfig option is explicitly checked during startup to ensure proper
  configuration. This validation prevents runtime issues from configuration
  mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
  NuttX-native implementations of xt_ints_on/off and interrupt handlers,
  avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
  RTC/RT-timer code to common-source Espressif integration, including
  esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
  implementation, including common-source auto-sleep behavior, UART/Wi-Fi
  wakeup coordination, and tickless-safe sleep flow compatibility.

Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.

Tested configurations:
- All defconfigs were tested, including `ostest`.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit is contained in:
Tiago Medicci Serrano
2026-03-29 00:33:11 +08:00
committed by Xiang Xiao
parent c64b95ccbf
commit c17e16eaed
621 changed files with 11436 additions and 53138 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/src/common/espressif/Make.defs
+1 -1
View File
@@ -207,7 +207,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309
ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/xtensa/Kconfig
+3
View File
@@ -22,6 +22,7 @@ config ARCH_CHIP_ESP32
select ARCH_HAVE_TESTSET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
@@ -56,6 +57,7 @@ config ARCH_CHIP_ESP32S2
select ARCH_HAVE_RESET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
@@ -92,6 +94,7 @@ config ARCH_CHIP_ESP32S3
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
arch/xtensa/include/esp32/irq.h
+27 -10
View File
@@ -39,7 +39,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32_setup_irq needs.
* code calling esp_setup_irq needs.
*/
#define ESP32_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -190,24 +190,39 @@
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
* interrupts. These use negative source IDs for internal CPU interrupts.
*/
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* Legacy definitions for compatibility */
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id)+XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32_PERIPH2IRQ(id)
/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
@@ -299,7 +314,7 @@
#define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS
#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* The PRO and APP CPU have different interrupts sources for the GPIO
* peripheral. Each CPU needs to allocate a separate interrupt and attach
@@ -325,6 +340,8 @@
# define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1)
# define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ)
# define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32_IRQ2PIN(i)
#else
# define ESP32_NIRQ_GPIO 0
#endif
@@ -477,7 +494,7 @@
* Inline functions
****************************************************************************/
#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
#ifdef CONFIG_SMP
static inline_function int esp32_irq_gpio(int cpu)
{
arch/xtensa/include/esp32s2/irq.h
+19 -9
View File
@@ -197,14 +197,19 @@
* interrupts
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -213,6 +218,9 @@
#define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32S2_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S2_PERIPH2IRQ(id)
#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC_NMI)
@@ -304,12 +312,14 @@
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 47
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S2_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S2_IRQ2PIN(i)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
@@ -360,7 +370,7 @@
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
arch/xtensa/include/esp32s3/irq.h
+20 -11
View File
@@ -41,7 +41,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32s3_setup_irq needs.
* code calling esp_setup_irq needs.
*/
#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -156,7 +156,6 @@
#define ESP32S3_PERIPH_AES 77
#define ESP32S3_PERIPH_SHA 78
#define ESP32S3_PERIPH_INT_FROM_CPU0 79
#define ESP32S3_PERIPH_INT_FROM_CPU1 80
#define ESP32S3_PERIPH_INT_FROM_CPU2 81
#define ESP32S3_PERIPH_INT_FROM_CPU3 82
@@ -201,14 +200,19 @@
* interrupts.
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -217,6 +221,9 @@
#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32S3_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S3_PERIPH2IRQ(id)
#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
@@ -329,7 +336,7 @@
#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
#ifdef CONFIG_ESP32S3_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
@@ -341,6 +348,8 @@
# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S3_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S3_IRQ2PIN(i)
#else
# define ESP32S3_NIRQ_GPIO 0
#endif
@@ -392,7 +401,7 @@
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
arch/xtensa/src/common/espressif/Kconfig
+243 -20
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/Make.defs
+15 -4
View File
@@ -20,6 +20,10 @@
#
############################################################################
# Silent preprocessor warnings
CFLAGS += -Wno-shadow -Wno-undef
ifeq ($(CONFIG_ESP_RMT),y)
CHIP_CSRCS += esp_rmt.c
ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y)
@@ -124,19 +128,26 @@ ifeq ($(CONFIG_ESPRESSIF_ADC),y)
CHIP_CSRCS += esp_adc.c
endif
ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp_pm_initialize.c
endif
CHIP_CSRCS += esp_pm.c
LDFLAGS += -u esp_timer_init_include_func
endif
endif
CHIP_CSRCS += esp_efuse.c
CHIP_CSRCS += esp_efuse.c esp_irq.c esp_xtensa_intr.c esp_gpio.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp_rtc.c
endif
ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y)
CHIP_CSRCS += esp_timer_adapter.c
endif
LDFLAGS += -u esp_system_include_startup_funcs
LDFLAGS += -u esp_timer_init_include_func
ifeq ($(CONFIG_ESPRESSIF_EFUSE),y)
LDFLAGS += -u esp_efuse_startup_include_func
endif
arch/xtensa/src/common/espressif/Wireless.mk
+52 -14
View File
@@ -20,6 +20,8 @@
#
############################################################################
WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
ifeq ($(CONFIG_ARCH_CHIP_ESP32),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include
endif
@@ -27,6 +29,7 @@ ifeq ($(CONFIG_ARCH_CHIP_ESP32S3),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)$(DELIM)wifi_apps$(DELIM)roaming_app$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi
@@ -59,21 +62,32 @@ ifeq ($(CONFIG_WPA_WAPI_PSK),y)
EXTRA_LIBS += -lwapi
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
ifeq ($(CONFIG_ESPRESSIF_WIFI),y)
## ESP-IDF's mbedTLS
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
### Define Espressif's configs for mbedTLS
CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="<mbedtls/esp_config.h>"
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
CHIP_CSRCS += aes.c
CHIP_CSRCS += aria.c
CHIP_CSRCS += bignum_core.c
@@ -110,21 +124,48 @@ CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
CHIP_CSRCS += pk_rsa.c
CHIP_CSRCS += psa_util.c
CHIP_CSRCS += psa_crypto_ffdh.c
CHIP_CSRCS += psa_crypto_ecp.c
CHIP_CSRCS += psa_crypto_rsa.c
CHIP_CSRCS += psa_crypto_cipher.c
CHIP_CSRCS += psa_crypto_mac.c
CHIP_CSRCS += psa_crypto_hash.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core
CHIP_CSRCS += psa_crypto_client.c
CHIP_CSRCS += psa_crypto_driver_wrappers_no_static.c
CHIP_CSRCS += psa_crypto_slot_management.c
CHIP_CSRCS += psa_crypto_storage.c
CHIP_CSRCS += psa_crypto.c
CHIP_CSRCS += psa_its_file.c
CHIP_CSRCS += tf_psa_crypto_config.c
CHIP_CSRCS += tf_psa_crypto_version.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
CHIP_CSRCS += esp_psa_crypto_init.c
CHIP_CSRCS += esp_hardware.c
CHIP_CSRCS += esp_mem.c
CHIP_CSRCS += esp_timing.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md
# Ensure PSA crypto initialization is included in the build
CHIP_CSRCS += esp_md.c
LDFLAGS += -u mbedtls_psa_crypto_init_include_impl
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_mac
ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
CHIP_CSRCS += psa_crypto_driver_esp_hmac_opaque.c
endif
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_md
CHIP_CSRCS += psa_crypto_driver_esp_md5.c
## WPA Supplicant
WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
CFLAGS += $(DEFINE_PREFIX)__ets__
CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS
CFLAGS += $(DEFINE_PREFIX)CONFIG_ECC
@@ -132,14 +173,18 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W
CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE
CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD
CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1
CFLAGS += $(DEFINE_PREFIX)TF_PSA_CRYPTO_USER_CONFIG_FILE=\"mbedtls/esp_config.h\"
CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT
CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE
CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESPRESSIF_WIFI_SOFTAP_SAE_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
endif
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
endif
@@ -160,9 +205,6 @@ ifeq ($(CONFIG_ESPRESSIF_WIFI_GMAC_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
@@ -193,7 +235,6 @@ VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto
CHIP_CSRCS += aes-ccm.c
CHIP_CSRCS += aes-gcm.c
CHIP_CSRCS += aes-omac1.c
CHIP_CSRCS += aes-unwrap.c
CHIP_CSRCS += aes-wrap.c
CHIP_CSRCS += ccmp.c
@@ -246,8 +287,6 @@ CHIP_CSRCS += os_xtensa.c
## ESP Supplicant (Espressif's WPA supplicant extension)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
@@ -272,7 +311,6 @@ CHIP_CSRCS += crypto_mbedtls.c
CHIP_CSRCS += tls_mbedtls.c
CHIP_CSRCS += aes-siv.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)lib_printf.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)regulatory$(DELIM)esp_wifi_regulatory.c
arch/xtensa/src/common/espressif/esp_adc.c
+4 -7
View File
@@ -45,16 +45,16 @@
#include "hal/adc_oneshot_hal.h"
#include "hal/adc_ll.h"
#include "hal/sar_ctrl_ll.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/periph_defs.h"
#include "esp_clk_tree.h"
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "esp32_gpio.h"
#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -66,15 +66,12 @@
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32
# define esp_configgpio esp32_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_3
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S2
# define esp_configgpio esp32s2_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S3
# define esp_configgpio esp32s3_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
arch/xtensa/src/common/espressif/esp_dedic_gpio.c
+26 -41
View File
@@ -46,19 +46,14 @@
#include "chip.h"
#include "esp_dedic_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_irq.h"
#include "esp32s2_gpio.h"
#endif
#include "espressif/esp_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "soc/dedic_gpio_struct.h"
#endif
#include "hal/dedic_gpio_ll.h"
#include "hal/dedic_gpio_cpu_ll.h"
#include "soc/dedic_gpio_periph.h"
#include "hal/dedic_gpio_periph.h"
#include "hal/dedic_gpio_caps.h"
#include "soc/gpio_sig_map.h"
#include "periph_ctrl.h"
#include "soc/soc_caps.h"
@@ -71,19 +66,11 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#endif
/****************************************************************************
@@ -252,7 +239,7 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
}
/****************************************************************************
* Name: esp_pcnt_isr_register
* Name: esp_dedic_gpio_isr_register
*
* Description:
* This function registers an interrupt service routine (ISR) for the
@@ -271,29 +258,23 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
static int esp_dedic_gpio_isr_register(void)
{
int cpuint;
#ifndef CONFIG_ARCH_CHIP_ESP32S2
int ret;
#endif
int cpu = this_cpu();
uint32_t status;
cpuint = esp_setup_irq(dedic_gpio_periph_signals.irq,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL);
ESP_IRQ_TRIGGER_LEVEL,
esp_dedic_gpio_isr_default,
&dedic_gpio_common[cpu]);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
ret = irq_attach(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH,
esp_dedic_gpio_isr_default,
&dedic_gpio_common[cpu]);
if (ret < 0)
{
cperr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(dedic_gpio_periph_signals.irq, cpuint);
return ERROR;
}
status = dedic_gpio_ll_get_interrupt_status(dedic_gpio_common[cpu].dev);
dedic_gpio_ll_clear_interrupt_status(dedic_gpio_common[cpu].dev, status);
up_enable_irq(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH);
@@ -538,9 +519,9 @@ struct file *esp_dedic_gpio_new_bundle(
}
dedic_gpio_common[cpu].out_occupied_mask =
UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1);
dedic_gpio_common[cpu].in_occupied_mask =
UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1);
spin_unlock_irqrestore(&dedic_gpio_common[cpu].spinlock, flags);
}
@@ -557,11 +538,12 @@ struct file *esp_dedic_gpio_new_bundle(
out_offset = 0;
if (config->flags->output_enable)
{
if (config->array_size > SOC_DEDIC_GPIO_OUT_CHANNELS_NUM)
if (config->array_size > DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU))
{
gpioerr("ERROR: array size(%d) exceeds maximum supported out\
gpioerr("ERROR: array size(%d) exceeds maximum supported out \
channels(%d)\n",
config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM);
config->array_size,
DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -569,8 +551,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size;
i++)
i <= (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - \
config->array_size);
i++)
{
if ((dedic_gpio_common[cpu].out_occupied_mask & (pattern << i))
== 0)
@@ -608,11 +591,12 @@ struct file *esp_dedic_gpio_new_bundle(
if (config->flags->input_enable)
{
if (config->array_size > SOC_DEDIC_GPIO_IN_CHANNELS_NUM)
if (config->array_size > DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU))
{
gpioerr("ERROR: array size(%d) exceeds maximum supported in\
channels(%d)\n",
config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM);
config->array_size,
DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -620,8 +604,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size;
i++)
i <= (DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - \
config->array_size);
i++)
{
if ((dedic_gpio_common[cpu].in_occupied_mask &
(pattern << i)) == 0)
arch/xtensa/src/common/espressif/esp_efuse.c
+4 -10
View File
@@ -42,6 +42,7 @@
#include "xtensa.h"
#include "soc/syscon_reg.h"
#include "esp_efuse_table.h"
#include "hal/efuse_ll.h"
#endif
/****************************************************************************
@@ -345,16 +346,9 @@ uint32_t esp_efuse_hal_chip_revision(void)
uint32_t combine_value;
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1,
&eco_bit0,
ESP_EFUSE_CHIP_VER_REV1[0]->bit_count);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2,
&eco_bit1,
ESP_EFUSE_CHIP_VER_REV2[0]->bit_count);
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION_MINOR,
&minor_chip_version,
ESP_EFUSE_WAFER_VERSION_MINOR[0]->bit_count);
eco_bit0 = efuse_ll_get_chip_ver_rev1();
eco_bit1 = efuse_ll_get_chip_ver_rev2();
minor_chip_version = efuse_ll_get_chip_wafer_version_minor();
eco_bit2 = (getreg32(SYSCON_DATE_REG) & 0x80000000) >> 31;
combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
+1 -1
View File
@@ -47,7 +47,7 @@
#include <nuttx/wdog.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_now.h"
#include "esp_mac.h"
#include "esp_espnow_pktradio.h"
arch/xtensa/src/common/espressif/esp_gpio.c
+457
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s2/esp32s2_gpio.h → arch/xtensa/src/common/espressif/esp_gpio.h
+150 -143
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h → arch/xtensa/src/common/espressif/esp_hr_timer.h
+8 -30
View File
@@ -1,5 +1,7 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
* arch/xtensa/src/common/espressif/esp_hr_timer.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,39 +20,15 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* This is a compatibility wrapper for the new ESP-HAL timer adapter */
#ifdef CONFIG_RTC_DRIVER
#include "esp_timer_adapter.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int esp32s3_rtc_driverinit(void);
#endif /* CONFIG_RTC_DRIVER */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H */
arch/xtensa/src/common/espressif/esp_i2c_bitbang.c
+19 -19
View File
@@ -33,16 +33,16 @@
#include <nuttx/kmalloc.h>
#include "espressif/esp_i2c_bitbang.h"
#include "espressif/esp_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "esp32s2_gpio_sigmap.h"
# include "esp32s2_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp32s3_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp32_gpio_sigmap.h"
# error "Unsupported chip"
#endif
/****************************************************************************
@@ -50,23 +50,23 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s2_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#else
#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
#define GPIO_READ(pin) esp3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#endif
/****************************************************************************
arch/xtensa/src/common/espressif/esp_i2c_slave.c
+11 -62
View File
@@ -54,16 +54,16 @@
#include "esp_i2c_slave.h"
#include "xtensa.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp32s3_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "esp32s2_irq.h"
#include "espressif/esp_gpio.h"
#include "espressif/esp_irq.h"
#include "esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -73,7 +73,7 @@
#include "hal/i2c_ll.h"
#include "soc/system_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/i2c_periph.h"
#include "hal/i2c_periph.h"
/****************************************************************************
* Pre-processor Definitions
@@ -85,48 +85,21 @@
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S3_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S3_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S3_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define esp_setup_irq esp32s3_setup_irq
#define esp_teardown_irq esp32s3_teardown_irq
#define esp_gpiowrite(pin, value) esp32s3_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32s3_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv) esp32s3_gpio_matrix_in(pin, \
idx, inv)
#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32S2_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32S2_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S2_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S2_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S2_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_gpiowrite(pin, value) esp32s2_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32s2_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv, en_inv) esp32s2_gpio_matrix_in(pin, \
idx, inv, en_inv)
#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
idx, inv, en_inv)
#else
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT 1
#define esp_setup_irq esp32_setup_irq
#define esp_teardown_irq esp32_teardown_irq
#define esp_gpiowrite(pin, value) esp32_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv) esp32_gpio_matrix_in(pin, \
idx, inv)
#define esp_gpio_matrix_out(pin, idx, inv) esp32_gpio_matrix_out(pin, \
idx, inv)
#endif
#define I2C_FIFO_FULL_THRESH_VAL 28
@@ -935,20 +908,13 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
/* Disable the previous IRQ */
up_disable_irq(config->irq);
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph, priv->cpuint);
esp_teardown_irq(config->periph, priv->cpuint);
}
priv->cpuint = esp_setup_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph,
priv->cpuint = esp_setup_irq(config->periph,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL);
ESP_IRQ_TRIGGER_LEVEL,
esp_i2c_slave_irq, priv);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type. */
@@ -959,23 +925,6 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
return NULL;
}
ret = irq_attach(config->irq, esp_i2c_slave_irq, priv);
if (ret != OK)
{
/* Failed to attach IRQ, free the allocated CPU interrupt */
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph, priv->cpuint);
priv->cpuint = -ENOMEM;
priv->refs--;
nxmutex_unlock(&priv->lock);
return NULL;
}
/* Enable the CPU interrupt that is linked to the I2C device. */
up_enable_irq(config->irq);
arch/xtensa/src/common/espressif/esp_i2s.c
+29 -89
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_irq.c
+955
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_irq.h
+296
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_ledc.c
+20 -16
View File
@@ -37,15 +37,15 @@
#include "esp_ledc.h"
#include "xtensa.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp_gpio.h"
# include "hardware/esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "hardware/esp32_gpio_sigmap.h"
# include "espressif/esp_gpio.h"
# include "hardware/esp32s2_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp_gpio.h"
# include "hardware/esp32s3_gpio_sigmap.h"
#endif
#include "esp_private/periph_ctrl.h"
@@ -61,8 +61,6 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
# define esp_configgpio esp32s3_configgpio
# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
# ifdef CONFIG_ESP32S3_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S3_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S3_LEDC_CHANNEL1_PIN
@@ -94,8 +92,6 @@
# endif /* CONFIG_ESP32S3_LEDC_TIM3 */
# endif /* CONFIG_ESP32S3_LEDC */
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# define esp_configgpio esp32s2_configgpio
# define esp_gpio_matrix_out esp32s2_gpio_matrix_out
# ifdef CONFIG_ESP32S2_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S2_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S2_LEDC_CHANNEL1_PIN
@@ -540,7 +536,6 @@ static bool ledc_ctx_create(void)
ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), LEDC_LOW_SPEED_MODE);
ledc_new_mode_obj->glb_clk = LEDC_SLOW_CLK_UNINIT;
p_ledc_obj = ledc_new_mode_obj;
periph_module_enable(PERIPH_LEDC_MODULE);
}
}
@@ -1235,7 +1230,7 @@ static int ledc_channel_output_enable(ledc_channel_t channel)
}
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, true);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, true);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
return OK;
}
@@ -1270,7 +1265,7 @@ static int ledc_channel_output_disable(ledc_channel_t channel)
ledc_hal_set_idle_level(&(p_ledc_obj->ledc_hal), channel, 0);
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, false);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, false);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
leave_critical_section(flags);
return OK;
@@ -1532,10 +1527,19 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
if (p_ledc_obj != NULL)
{
periph_module_disable(PERIPH_LEDC_MODULE);
kmm_free(p_ledc_obj);
p_ledc_obj = NULL;
s_ledc_slow_clk_rc_fast_freq = 0;
LEDC_BUS_CLOCK_ATOMIC()
{
ledc_ll_enable_bus_clock(false);
ledc_ll_enable_reset_reg(true);
}
LEDC_FUNC_CLOCK_ATOMIC()
{
ledc_ll_enable_clock(LEDC_LL_GET_HW(), false);
}
}
else
{
arch/xtensa/src/common/espressif/esp_loader.c
+1 -1
View File
@@ -47,7 +47,7 @@
# include "bootloader_flash_priv.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "esp_rom_uart.h"
# include "esp_rom_serial_output.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
arch/xtensa/src/common/espressif/esp_mcpwm.c
+72 -49
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_openeth.c
+3 -6
View File
@@ -514,8 +514,9 @@ int esp_openeth_initialize(void)
/* Setup interrupts */
priv->cpuint = OPENETH_SETUP_IRQ(0, OPENETH_PERIPH_MAC,
1, OPENETH_CPUINT_LEVEL);
priv->cpuint = OPENETH_SETUP_IRQ(OPENETH_PERIPH_MAC,
1, OPENETH_CPUINT_LEVEL,
openeth_isr_handler, priv);
if (priv->cpuint < 0)
{
nerr("ERROR: Failed allocate interrupt\n");
@@ -531,10 +532,6 @@ int esp_openeth_initialize(void)
"\x00\x02\x03\x04\x05\x06\x07\x08", ETH_ALEN);
openeth_set_addr(priv->dev.netdev.d_mac.ether.ether_addr_octet);
/* Attach the interrupt */
ret = irq_attach(OPENETH_IRQ_MAC, openeth_isr_handler, priv);
/* Register the device with the OS so that socket IOCTLs can be
* performed.
*/
arch/xtensa/src/common/espressif/esp_pcnt.c
+55 -74
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_pm.c
+306 -62
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_pm.h
+39 -13
View File
@@ -44,11 +44,32 @@ extern "C"
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Types
****************************************************************************/
typedef bool (*skip_light_sleep_cb_t)(void);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_pm_sleep_enable_timer_wakeup
*
* Description:
* Configure wakeup interval
*
* Input Parameters:
* time_in_us - Sleep duration in microseconds.
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp_pm_light_sleep_start
*
@@ -115,52 +136,57 @@ void esp_pmstandby(uint64_t time_in_us);
void esp_pmsleep(uint64_t time_in_us);
/****************************************************************************
* Name: esp_pm_lockacquire
* Name: esp_pmconfigure
*
* Description:
* Take a power management lock
* Configure power manager.
*
* Input Parameters:
* None
*
* Returned Value:
* None
* Returns OK on success; a negated errno value on failure.
*
****************************************************************************/
void esp_pm_lockacquire(void);
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
int esp_pmconfigure(void);
#endif
/****************************************************************************
* Name: esp_pm_lockrelease
* Name: esp_pm_wakeup_set_last_reason
*
* Description:
* Release the lock taken using esp_pm_lockacquire.
* Store the sleep exit wakeup cause after light sleep. Used with
* esp_pm_wakeup_set_last_time() so the skip-light-sleep hook can
* detect a recent UART wakeup.
*
* Input Parameters:
* None
* reason - Value from esp_sleep_get_wakeup_cause().
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_lockrelease(void);
void esp_pm_wakeup_set_last_reason(int32_t reason);
/****************************************************************************
* Name: esp_pm_lockstatus
* Name: esp_pm_wakeup_set_last_time
*
* Description:
* Return power management lock status.
* Store the high-resolution timestamp (microseconds) aligned with
* the wakeup cause set by esp_pm_wakeup_set_last_reason().
*
* Input Parameters:
* None
* time_us - Time from esp_hr_timer_time_us() at exit from light sleep.
*
* Returned Value:
* Current pm_wakelock count
* None
*
****************************************************************************/
uint32_t esp_pm_lockstatus(void);
void esp_pm_wakeup_set_last_time(uint64_t time_us);
#endif /* CONFIG_PM */
arch/xtensa/src/common/espressif/esp_rmt.c
+222 -1756
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_rmt.h
+21 -23
View File
@@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
/****************************************************************************
* Included Files
@@ -67,6 +67,22 @@ extern "C"
#if defined(CONFIG_ESP_RMT)
/****************************************************************************
* Name: esp_rmt_rx_init
*
* Description:
* Initialize the selected RMT device in RX mode
*
* Input Parameters:
* rx_pin - The pin used for the RX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_rx_init(int rx_pin);
/****************************************************************************
* Name: esp_rmt_tx_init
*
@@ -74,32 +90,14 @@ extern "C"
* Initialize the selected RMT device in TX mode
*
* Input Parameters:
* ch - The RMT's channel that will be used
* pin - The pin used for the TX channel
* tx_pin - The pin used for the TX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin);
/****************************************************************************
* Name: esp_rmt_rx_init
*
* Description:
* Initialize the selected RMT device in RC mode
*
* Input Parameters:
* ch - The RMT's channel that will be used
* pin - The pin used for the RX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
struct rmt_dev_s *esp_rmt_tx_init(int tx_pin);
#endif
@@ -108,4 +106,4 @@ struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H */
arch/xtensa/src/common/espressif/esp_rtc.c
+895
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h → arch/xtensa/src/common/espressif/esp_rtc.h
+12 -15
View File
@@ -1,5 +1,7 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
* arch/xtensa/src/common/espressif/esp_rtc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
/****************************************************************************
* Included Files
@@ -27,30 +29,25 @@
#include <nuttx/config.h>
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_rtc_driverinit
* Name: esp_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
* Initialize and register an RTC lower half driver.
*
* Input Parameters:
* None
* None.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
int esp32_rtc_driverinit(void);
int esp_rtc_driverinit(void);
#endif /* CONFIG_RTC_DRIVER */
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H */
arch/xtensa/src/common/espressif/esp_sdm.c
+27 -35
View File
@@ -42,40 +42,27 @@
#include <nuttx/spinlock.h>
#include "esp_sdm.h"
#include "hal/gpio_ll.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#include "hardware/esp32s3_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#include "hardware/esp32s2_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#include "esp32_gpio.h"
#include "hardware/esp32_soc.h"
#include "esp_gpio.h"
#endif
#include "esp_clk_tree.h"
#include "hal/sdm_hal.h"
#include "hal/sdm_ll.h"
#include "soc/sdm_periph.h"
#include "hal/sdm_periph.h"
#include "hal/sdm_caps.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#define esp_configgpio esp32_configgpio
#define esp_gpio_matrix_in esp32_gpio_matrix_in
#define esp_gpio_matrix_out esp32_gpio_matrix_out
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@@ -92,18 +79,18 @@ struct esp_sdm_channel_priv_s
struct esp_sdm_group_priv_s
{
int group_id; /* Group ID, index from 0 */
spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
sdm_hal_context_t hal; /* Common layer context */
soc_periph_sdm_clk_src_t clk_src; /* Clock source */
struct esp_sdm_channel_priv_s *channels[SOC_SDM_CHANNELS_PER_GROUP]; /* Array of SDM channels */
int group_id; /* Group ID, index from 0 */
spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
sdm_hal_context_t hal; /* Common layer context */
soc_periph_sdm_clk_src_t clk_src; /* Clock source */
struct esp_sdm_channel_priv_s *channels[SDM_CAPS_GET(CHANS_PER_INST)]; /* Array of SDM channels */
};
struct esp_sdm_priv_s
{
rmutex_t lock; /* Lock for protecting concurrent operations */
struct esp_sdm_group_priv_s *groups[SOC_SDM_GROUPS]; /* SDM group pool */
int group_ref_counts[SOC_SDM_GROUPS]; /* Reference count used to protect group install/uninstall */
rmutex_t lock; /* Lock for protecting concurrent operations */
struct esp_sdm_group_priv_s *groups[SDM_CAPS_GET(INST_NUM)]; /* SDM group pool */
int group_ref_counts[SDM_CAPS_GET(INST_NUM)]; /* Reference count used to protect group install/uninstall */
};
/****************************************************************************
@@ -382,7 +369,7 @@ struct esp_sdm_channel_priv_s *esp_sdm_create_config_channel(
esp_configgpio(config.gpio_num, attr);
esp_gpio_matrix_out(config.gpio_num,
sigma_delta_periph_signals.channels[ret->chan_id].sd_sig,
soc_sdm_signals[group_id].channels[ret->chan_id].sig_id_matrix,
(config.flags && INVERT_OUT), false);
esp_clk_tree_src_get_freq_hz(g_esp_sdm.groups[ret->group_id]->clk_src,
@@ -431,7 +418,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
for (i = 0; i < SOC_SDM_GROUPS; i++)
for (i = 0; i < SDM_CAPS_GET(INST_NUM); i++)
{
nxrmutex_lock(&(g_esp_sdm.lock));
if (g_esp_sdm.groups[i] == NULL)
@@ -445,16 +432,21 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
else
{
sdm_hal_init_config_t hal_config =
{
.group_id = group_id,
};
g_esp_sdm.groups[i]->group_id = i;
g_esp_sdm.groups[i]->clk_src = SDM_CLK_SRC_DEFAULT;
group_id = i;
sdm_hal_init(&g_esp_sdm.groups[i]->hal, i);
sdm_hal_init(&g_esp_sdm.groups[i]->hal, &hal_config);
sdm_ll_enable_clock(g_esp_sdm.groups[i]->hal.dev, true);
ainfo("new group (%d) at %p\n", i, g_esp_sdm.groups[i]);
break;
}
}
else if (g_esp_sdm.group_ref_counts[i] < SOC_SDM_CHANNELS_PER_GROUP)
else if (g_esp_sdm.group_ref_counts[i] < SDM_CAPS_GET(CHANS_PER_INST))
{
group_id = i;
break;
@@ -462,7 +454,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
if (g_esp_sdm.group_ref_counts[group_id] >=
SOC_SDM_CHANNELS_PER_GROUP)
SDM_CAPS_GET(CHANS_PER_INST))
{
aerr("ERROR! No free slot available\n");
return NULL;
@@ -473,7 +465,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
nxrmutex_unlock(&(g_esp_sdm.lock));
flags = spin_lock_irqsave(&group->spinlock);
for (j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++)
for (j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++)
{
if (group->channels[j] == NULL)
{
@@ -541,7 +533,7 @@ int esp_sdm_create_channel(struct esp_sdm_chan_config_s config,
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
for (i = 0; i < SOC_SDM_CHANNELS_PER_GROUP; i++)
for (i = 0; i < SDM_CAPS_GET(CHANS_PER_INST); i++)
{
if (group->channels[i] == NULL)
{
@@ -602,7 +594,7 @@ struct dac_dev_s *esp_sdminitialize(struct esp_sdm_chan_config_s config)
{
ret->ad_priv = (void *)sdm;
ret->ad_ops = &ops;
ret->ad_nchannel = SOC_SDM_CHANNELS_PER_GROUP;
ret->ad_nchannel = SDM_CAPS_GET(CHANS_PER_INST);
}
return (struct dac_dev_s *)ret;
arch/xtensa/src/common/espressif/esp_sha.c
+22 -1
View File
@@ -39,11 +39,19 @@
#include "esp_sha.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "soc/periph_defs.h"
#include "hal/sha_ll.h"
#include "hal/sha_hal.h"
#include "soc/soc_caps.h"
#include "rom/cache.h"
/* Crypto DMA, shared between AES and SHA */
#if SOC_AES_CRYPTO_DMA && SOC_SHA_CRYPTO_DMA
# include "hal/crypto_dma_ll.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -276,6 +284,7 @@ int esp_sha1_update(struct esp_sha1_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -500,6 +509,7 @@ int esp_sha256_update(struct esp_sha256_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -721,6 +731,7 @@ int esp_sha512_update(struct esp_sha512_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -852,7 +863,17 @@ int esp_sha_init(void)
{
if (!g_sha_inited)
{
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC()
{
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
#if SOC_SHA_CRYPTO_DMA
crypto_dma_ll_enable_bus_clock(true);
crypto_dma_ll_reset_register();
#endif
}
g_sha_inited = true;
}
else
arch/xtensa/src/common/espressif/esp_spi_bitbang.c
+12 -12
View File
@@ -43,13 +43,13 @@
#include <nuttx/spi/spi_bitbang.c>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#include "esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp_gpio.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -58,16 +58,17 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#else
#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
#else#if defined(CONFIG_ARCH_CHIP_ESP32)
#endif
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#endif
@@ -231,11 +232,10 @@ struct spi_dev_s *esp_spi_bitbang_init(void)
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, true);
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_CLKPIN, true);
#if CONFIG_ESPRESSIF_SPI_SWCS
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, SIG_GPIO_OUT_IDX,
0, 0);
#endif
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, SIG_GPIO_OUT_IDX,
0, 0);
arch/xtensa/src/common/espressif/esp_spi_bitbang.h
+8 -8
View File
@@ -47,11 +47,11 @@ extern "C"
#include <nuttx/spi/spi.h>
#include <nuttx/spi/spi_bitbang.h>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#else
#include "esp32_gpio.h"
#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -59,13 +59,13 @@ extern "C"
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s2_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#else
#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp3_gpioread(pin)
#endif
arch/xtensa/src/common/espressif/esp_spiflash.c
+3 -175
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_spiflash.h
-16
View File
@@ -106,22 +106,6 @@ int esp_spiflash_erase(uint32_t address, uint32_t length);
int esp_spiflash_write(uint32_t address, const void *buffer,
uint32_t length);
/****************************************************************************
* Name: esp_spiflash_init
*
* Description:
* Initialize ESP SPI flash driver.
*
* Input Parameters:
* None.
*
* Returned Value:
* OK if success or a negative value if fail.
*
****************************************************************************/
int esp_spiflash_init(void);
#ifdef __cplusplus
}
#endif
arch/xtensa/src/common/espressif/esp_temperature_sensor.c
+4 -8
View File
@@ -61,8 +61,7 @@
#include "hal/regi2c_ctrl.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/temperature_sensor_types.h"
#include "soc/temperature_sensor_periph.h"
#include "esp_efuse_rtc_calib.h"
#include "hal/temperature_sensor_periph.h"
#include "hal/adc_ll.h"
/****************************************************************************
@@ -105,7 +104,6 @@ struct esp_temp_priv_s
const temperature_sensor_attribute_t *tsens_attribute; /* Attribute struct of the common layer */
struct esp_temp_sensor_config_t cfg; /* Configuration struct of the common layer */
temperature_sensor_clk_src_t clk_src; /* Clock source to use */
int module; /* Peripheral module */
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -197,7 +195,6 @@ struct esp_temp_priv_s esp_temp_priv =
0
},
.clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT,
.module = PERIPH_TEMPSENSOR_MODULE,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -321,11 +318,10 @@ static int temperature_sensor_choose_best_range(struct esp_temp_priv_s *priv)
static int temperature_sensor_read_delta_t(void)
{
if (esp_efuse_rtc_calib_get_tsens_val(&g_delta_t) != OK)
g_delta_t = temperature_sensor_ll_load_calib_param();
if (g_delta_t == 0)
{
snwarn("Calibration failed");
g_delta_t = 0;
return ERROR;
snwarn("No calibration param in eFuse");
}
sninfo("delta_T = %f", g_delta_t);
arch/xtensa/src/common/espressif/esp_timer_adapter.c
+492
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_timer_adapter.h
+324
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_ulp.mk
+8 -1
View File
@@ -36,6 +36,14 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)ulp
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
@@ -68,7 +76,6 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)c
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_core$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include
# Linker scripts
arch/xtensa/src/common/espressif/esp_wireless.c
+27 -179
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_wireless.h
+1 -9
View File
@@ -33,16 +33,8 @@
#include <nuttx/config.h>
#include <nuttx/list.h>
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "xtensa_attr.h"
#include "esp32_rt_timer.h"
#elif CONFIG_ARCH_CHIP_ESP32S2
#include "esp_attr.h"
#include "esp32s2_rt_timer.h"
#elif CONFIG_ARCH_CHIP_ESP32S3
#include "esp_attr.h"
#include "esp32s3_rt_timer.h"
#endif
#include "esp_hr_timer.h"
#ifdef CONFIG_ESPRESSIF_WIFI
# include "os.h"
arch/xtensa/src/common/espressif/esp_wlan_netdev.c
+2 -2
View File
@@ -970,14 +970,14 @@ void IRAM_ATTR esp_wifi_tx_done_cb(uint8_t ifidx,
bool txstatus)
{
#ifdef ESP_WLAN_HAS_STA
if (ifidx == ESP_IF_WIFI_STA)
if (ifidx == WIFI_IF_STA)
{
netdev_lower_txdone(&g_wlan_sta.dev);
}
#endif
#ifdef ESP_WLAN_HAS_SOFTAP
if (ifidx == ESP_IF_WIFI_AP)
if (ifidx == WIFI_IF_AP)
{
netdev_lower_txdone(&g_wlan_softap.dev);
}
arch/xtensa/src/common/espressif/esp_ws2812.c
+28 -7
View File
@@ -35,6 +35,8 @@
#include "hal/rmt_types.h"
#include "soc/soc.h"
#include "esp_private/rmt.h"
#include "driver/rmt_common.h"
#include "esp_rmt.h"
@@ -67,6 +69,21 @@ struct rgbw_led_s
};
};
struct rmt_dev_lowerhalf_s
{
/* The following block is part of the upper-half device struct */
const struct rmt_ops_s *ops;
struct circbuf_s *circbuf;
sem_t *recvsem;
int minor;
/* The following is private to the ESP32 RMT driver */
rmt_channel_handle_t handle;
rmt_encoder_handle_t encoder;
};
struct esp_ws2812_dev_s
{
struct rmt_dev_s *rmt;
@@ -151,15 +168,19 @@ static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev,
uint16_t t0l;
uint16_t t1h;
uint16_t t1l;
uint32_t clock_period_ps;
uint32_t resolution_hz;
uint32_t rmt_period_ps;
esp_err_t ret;
struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev->rmt;
#if SOC_RMT_CHANNEL_CLK_INDEPENDENT
clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor];
#else
clock_period_ps = 1000000000000 / g_rmt_source_clock_hz;
#endif
rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV;
ret = rmt_get_channel_resolution(priv->handle, &resolution_hz);
if (ret != ESP_OK)
{
lederr("esp_ws2812 map_byte_to_words failed: %d\n", ret);
return 0;
}
rmt_period_ps = 1000000000000 / resolution_hz;
/* Calculate the RMT period to encode WS2812 frames */
arch/xtensa/src/common/espressif/esp_xtensa_intr.c
+153
View File
@@ -0,0 +1,153 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_xtensa_intr.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/kmalloc.h>
#include <arch/xtensa/xtensa_specregs.h>
#include "xtensa.h"
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "platform/os.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef XCHAL_NUM_INTERRUPTS
# define XCHAL_NUM_INTERRUPTS 32
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* Handler table entry structure - must match HAL's xt_handler_table_entry */
typedef struct xt_handler_table_entry
{
void *handler;
void *arg;
} xt_handler_table_entry;
/****************************************************************************
* Public Data
****************************************************************************/
/* Interrupt handler table - exported as _xt_interrupt_table for HAL
* compatibility. The HAL's xtensa_intr.c expects this to be defined
* externally (originally in assembly).
*/
xt_handler_table_entry
_xt_interrupt_table[XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS];
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xt_ints_on
*
* Description:
* Enables a set of interrupts.
*
* Input Parameters:
* mask - Bit mask of interrupts to be enabled.
*
* Returned Value:
* None.
*
****************************************************************************/
void xt_ints_on(unsigned int mask)
{
uint32_t intenable;
__asm__ __volatile__("rsr %0, intenable" : "=r"(intenable));
intenable |= mask;
__asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable));
}
/****************************************************************************
* Name: xt_ints_off
*
* Description:
* Disables a set of interrupts.
*
* Input Parameters:
* mask - Bit mask of interrupts to be disabled.
*
* Returned Value:
* None.
*
****************************************************************************/
void xt_ints_off(unsigned int mask)
{
uint32_t intenable;
__asm__ __volatile__("rsr %0, intenable" : "=r"(intenable));
intenable &= ~mask;
__asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable));
}
/****************************************************************************
* Name: esp_xtensa_intr_init
*
* Description:
* Initialize the interrupt handler table by setting all handlers to the
* default unhandled interrupt handler (provided by HAL's xtensa_intr.c).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_xtensa_intr_init(void)
{
int i;
for (i = 0; i < (XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS); i++)
{
/* Calling xt_set_interrupt_handler with f=NULL sets the handler
* to xt_unhandled_interrupt (defined in HAL's xtensa_intr.c)
*/
xt_set_interrupt_handler(i, NULL, (void *)(uintptr_t)i);
}
}
arch/xtensa/src/esp32/Kconfig
+19 -32
View File
@@ -196,9 +196,13 @@ config ESP32_XTAL_26MHz
endchoice # On-board Crystal Frequency
config ESP32_RT_TIMER
bool "Real-time Timer"
bool "Real-Time Timer"
default n
select ESP32_TIMER0
select ESPRESSIF_HR_TIMER
---help---
Deprecated: Use ESPRESSIF_HR_TIMER instead.
This option is kept for backward compatibility and automatically
selects the common ESPRESSIF_HR_TIMER configuration.
config ESP32_RUN_IRAM
bool "Run from IRAM"
@@ -336,7 +340,7 @@ config ESP32_I2S0
bool "I2S 0"
default n
select ARCH_DMA
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select ESPRESSIF_I2S0
if ESP32_I2S0
@@ -466,7 +470,7 @@ config ESP32_I2S1
bool "I2S 1"
default n
select ARCH_DMA
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select ESPRESSIF_I2S1
if ESP32_I2S1
@@ -618,7 +622,7 @@ config ESP32_SPI2
bool "SPI 2"
default n
select ESP32_SPI
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select SPI
select ESPRESSIF_SPI_PERIPH
@@ -626,7 +630,7 @@ config ESP32_SPI3
bool "SPI 3"
default n
select ESP32_SPI
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select SPI
select ESPRESSIF_SPI_PERIPH
@@ -829,12 +833,16 @@ menu "Interrupt Configuration"
config ESP32_IRAM_ISR_DEBUG
bool "Enable debugging of the IRAM-enabled interrupts"
default n
select ESPRESSIF_IRAM_ISR_DEBUG
---help---
This option enables keeping track of the IRAM-enabled interrupts by
registering its execution when non-IRAM interrupts are disabled. It
keeps track of the IRQ executed and register how many times since
boot it was executed.
This option is kept for backwards compatibility and automatically
selects CONFIG_ESPRESSIF_IRAM_ISR_DEBUG.
endmenu # Interrupt Configuration
menu "Memory Configuration"
@@ -893,9 +901,11 @@ endmenu # Memory Configuration
config ESP32_GPIO_IRQ
bool "GPIO pin interrupts"
select ESPRESSIF_GPIO_IRQ
default n
---help---
Enable support for interrupting GPIO pins
This is a deprecated Kconfig macro. Its kept for retrocompatibility only.
Use "CONFIG_ESPRESSIF_GPIO_IRQ" instead.
config ESP32_RTCIO_IRQ
bool "RTC IO interrupts"
@@ -2204,26 +2214,6 @@ endif
endmenu # PHY
menu "Real-Time Timer"
depends on ESP32_RT_TIMER
config ESP32_RT_TIMER_TASK_NAME
string "Timer task name"
default "rt_timer"
config ESP32_RT_TIMER_TASK_PRIORITY
int "Timer task priority"
default 223
---help---
Priority level of the RT Timer task.
Must be lower than the SCHED_HPWORKPRIORITY.
config ESP32_RT_TIMER_TASK_STACK_SIZE
int "Timer task stack size"
default 2048
endmenu # Real-Time Timer
if ESP32_TIMER
menu "Timer/counter Configuration"
@@ -2879,12 +2869,9 @@ endmenu # Application Image Configuration
config ESP32_AUTO_SLEEP
bool "Auto-sleep"
default n
select PM
select ESP32_RT_TIMER
select ESP32_TIMER0
select ESP32_TICKLESS
select ESPRESSIF_AUTO_SLEEP
---help---
Enable ESP32 Auto-sleep
This is a deprecated option. Use ESPRESSIF_AUTO_SLEEP instead.
config ESP32_TICKLESS
bool "Enable ESP32 tickless OS"
arch/xtensa/src/esp32/Make.defs
+7 -22
View File
@@ -32,9 +32,9 @@ endif
# Required ESP32 files (arch/xtensa/src/esp32)
CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c
CHIP_CSRCS = esp32_allocateheap.c
CHIP_CSRCS += esp32_systemreset.c esp32_resetcause.c
CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_rtc_gpio.c
CHIP_CSRCS += esp32_region.c esp32_rtc_gpio.c
CHIP_CSRCS += esp32_user.c esp32_libc_stubs.c
CHIP_CSRCS += esp32_dma.c
@@ -55,13 +55,6 @@ else
CHIP_CSRCS += esp32_timerisr.c
endif
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp32_pminitialize.c
endif
CHIP_CSRCS += esp32_pm.c
endif
ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y)
CHIP_CSRCS += esp32_imm.c
endif
@@ -164,10 +157,6 @@ ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y)
CHIP_CSRCS += esp32_textheap.c
endif
ifeq ($(CONFIG_ESP32_RT_TIMER),y)
CHIP_CSRCS += esp32_rt_timer.c
endif
ifeq ($(CONFIG_ESP32_TOUCH),y)
CHIP_CSRCS += esp32_touch.c
endif
@@ -184,13 +173,6 @@ ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y)
CHIP_CSRCS += esp32_crypto.c
endif
ifeq ($(CONFIG_ESP32_RTC),y)
CHIP_CSRCS += esp32_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_ESP32_OPENETH),y)
CHIP_CSRCS += esp_openeth.c
endif
@@ -212,7 +194,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = b9472bd56b916cced7447e25c2b2e1390d7e0d90
ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -252,13 +234,16 @@ chip/$(ESP_HAL_3RDPARTY_REPO):
$(Q) echo "Cloning Espressif HAL for 3rd Party Platforms"
$(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO)
ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true
$(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}"
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION)
endif
# Silent preprocessor warnings
CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion
CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations
# Enable strict volatile bitfield access
arch/xtensa/src/esp32/chip.h
+3 -3
View File
@@ -32,7 +32,7 @@
#if defined(CONFIG_ESP32_OPENETH) && !defined(__ASSEMBLY__)
#include "hardware/esp32_soc.h"
#include "esp32_irq.h"
#include "esp_irq.h"
#endif
/****************************************************************************
@@ -41,9 +41,9 @@
#if defined(CONFIG_ESP32_OPENETH)
#define OPENETH_PERIPH_MAC ESP32_PERIPH_EMAC
#define OPENETH_CPUINT_LEVEL ESP32_CPUINT_LEVEL
#define OPENETH_CPUINT_LEVEL ESP_IRQ_TRIGGER_LEVEL
#define OPENETH_IRQ_MAC ESP32_IRQ_EMAC
#define OPENETH_SETUP_IRQ esp32_setup_irq
#define OPENETH_SETUP_IRQ esp_setup_irq
#define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM
#endif
arch/xtensa/src/esp32/esp32_ble_adapter.c
+80 -126
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_clockconfig.c
-218
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_clockconfig.h
-82
View File
@@ -1,82 +0,0 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "esp_private/esp_clk.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_update_cpu_freq(uint32_t ticks_per_us);
/****************************************************************************
* Name: esp32_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
* Current frequency can be XTAL or PLL.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_set_cpu_freq(int cpu_freq_mhz);
/****************************************************************************
* Name: esp32_clockconfig
*
* Description:
* Called to initialize the ESP32. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32_clockconfig(void);
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */
arch/xtensa/src/esp32/esp32_cpustart.c
+20 -27
View File
@@ -38,12 +38,13 @@
#include "xtensa.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
#include "esp32_region.h"
#include "esp32_irq.h"
#include "espressif/esp_irq.h"
#include "esp32_smp.h"
#include "esp32_gpio.h"
#include "esp32_start.h"
#include "espressif/esp_gpio.h"
/****************************************************************************
* Private Data
@@ -63,21 +64,24 @@ extern void ets_set_appcpu_boot_addr(uint32_t start);
/****************************************************************************
* Name: xtensa_attach_fromcpu0_interrupt
*
* Description:
* Attach the inter-CPU interrupt for CPU1 to receive from CPU0.
* This is called during early CPU1 boot.
*
****************************************************************************/
static inline void xtensa_attach_fromcpu0_interrupt(void)
static inline void IRAM_ATTR xtensa_attach_fromcpu0_interrupt(void)
{
int cpuint;
/* Connect all CPU peripheral source to allocated CPU interrupt */
cpuint = esp32_setup_irq(1, ESP32_PERIPH_CPU_CPU0, 1, ESP32_CPUINT_LEVEL);
cpuint = esp_setup_irq(ESP32_PERIPH_CPU_CPU0, 1,
ESP_IRQ_TRIGGER_LEVEL, esp32_fromcpu0_interrupt,
NULL);
DEBUGASSERT(cpuint >= 0);
/* Attach the inter-CPU interrupt. */
irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_fromcpu0_interrupt, NULL);
/* Enable the inter 0 CPU interrupts. */
up_enable_irq(ESP32_IRQ_CPU_CPU0);
@@ -126,10 +130,6 @@ void IRAM_ATTR xtensa_appcpu_start(void)
sched_note_cpu_started(tcb);
#endif
/* Signal to the PRO CPU that the APP CPU has started. */
g_appcpu_started = true;
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
@@ -140,30 +140,18 @@ void IRAM_ATTR xtensa_appcpu_start(void)
/* Initialize CPU interrupts */
esp32_cpuint_initialize();
/* Attach and enable internal interrupts */
esp_cpuint_initialize();
/* Attach and enable the inter-CPU interrupt */
xtensa_attach_fromcpu0_interrupt();
/* Enable the software interrupt */
up_enable_irq(XTENSA_IRQ_SWINT);
/* Dump registers so that we can see what is going to happen on return */
#if 0
up_dump_register(tcb->xcp.regs);
#endif
#ifdef CONFIG_ESP32_GPIO_IRQ
/* Initialize GPIO interrupt support */
esp32_gpioirqinitialize(1);
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And Enable interrupts */
@@ -174,6 +162,12 @@ void IRAM_ATTR xtensa_appcpu_start(void)
xtensa_set_cpenable(CONFIG_XTENSA_CP_INITSET);
#endif
sys_startup_fn();
/* Signal to the PRO CPU that the APP CPU has started. */
g_appcpu_started = true;
/* Then switch contexts. This instantiates the exception context of the
* tcb at the head of the assigned task list. In this case, this should
* be the CPUs NULL task.
@@ -275,4 +269,3 @@ int up_cpu_start(int cpu)
return OK;
}
arch/xtensa/src/esp32/esp32_emac.c
+23 -30
View File
@@ -55,13 +55,12 @@
#endif
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32_gpio_sigmap.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_emac.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include <arch/board/board.h>
@@ -514,25 +513,25 @@ static int emac_read_mac(uint8_t *mac)
static void emac_init_gpio(void)
{
esp32_configgpio(EMAC_TXEN_PIN, OUTPUT_FUNCTION_6);
esp32_configgpio(EMAC_TXDO_PIN, OUTPUT_FUNCTION_6);
esp32_configgpio(EMAC_TXD1_PIN, OUTPUT_FUNCTION_6);
esp_configgpio(EMAC_TXEN_PIN, OUTPUT_FUNCTION_6);
esp_configgpio(EMAC_TXDO_PIN, OUTPUT_FUNCTION_6);
esp_configgpio(EMAC_TXD1_PIN, OUTPUT_FUNCTION_6);
esp32_configgpio(EMAC_RXDO_PIN, INPUT_FUNCTION_6);
esp32_configgpio(EMAC_RXD1_PIN, INPUT_FUNCTION_6);
esp32_configgpio(EMAC_RXDV_PIN, INPUT_FUNCTION_6);
esp_configgpio(EMAC_RXDO_PIN, INPUT_FUNCTION_6);
esp_configgpio(EMAC_RXD1_PIN, INPUT_FUNCTION_6);
esp_configgpio(EMAC_RXDV_PIN, INPUT_FUNCTION_6);
esp32_configgpio(EMAC_ICLK_PIN, INPUT_FUNCTION_6);
esp_configgpio(EMAC_ICLK_PIN, INPUT_FUNCTION_6);
esp32_configgpio(EMAC_MDC_PIN, OUTPUT | FUNCTION_3);
esp32_gpio_matrix_out(EMAC_MDC_PIN, EMAC_MDC_O_IDX, 0, 0);
esp_configgpio(EMAC_MDC_PIN, OUTPUT | FUNCTION_3);
esp_gpio_matrix_out(EMAC_MDC_PIN, EMAC_MDC_O_IDX, 0, 0);
esp32_configgpio(EMAC_MDIO_PIN, OUTPUT | INPUT | FUNCTION_3);
esp32_gpio_matrix_out(EMAC_MDIO_PIN, EMAC_MDO_O_IDX, 0, 0);
esp32_gpio_matrix_in(EMAC_MDIO_PIN, EMAC_MDI_I_IDX, 0);
esp_configgpio(EMAC_MDIO_PIN, OUTPUT | INPUT | FUNCTION_3);
esp_gpio_matrix_out(EMAC_MDIO_PIN, EMAC_MDO_O_IDX, 0, 0);
esp_gpio_matrix_in(EMAC_MDIO_PIN, EMAC_MDI_I_IDX, 0);
#ifdef CONFIG_ESP32_ETH_ENABLE_PHY_RSTPIN
esp32_configgpio(EMAC_PHYRST_PIN, OUTPUT | PULLUP);
esp_configgpio(EMAC_PHYRST_PIN, OUTPUT | PULLUP);
#endif
}
@@ -564,9 +563,9 @@ static int emac_config(void)
/* Hardware reset PHY chip */
esp32_gpiowrite(EMAC_PHYRST_PIN, false);
esp_gpiowrite(EMAC_PHYRST_PIN, false);
up_udelay(50);
esp32_gpiowrite(EMAC_PHYRST_PIN, true);
esp_gpiowrite(EMAC_PHYRST_PIN, true);
#endif
/* Open hardware clock */
@@ -2047,8 +2046,11 @@ int esp32_emac_init(void)
memset(priv, 0, sizeof(struct esp32_emac_s));
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, ESP32_PERIPH_EMAC,
1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(ESP32_PERIPH_EMAC,
1,
ESP_IRQ_TRIGGER_LEVEL,
emac_interrupt,
priv);
if (priv->cpuint < 0)
{
nerr("ERROR: Failed alloc interrupt\n");
@@ -2057,15 +2059,6 @@ int esp32_emac_init(void)
goto error;
}
ret = irq_attach(ESP32_IRQ_EMAC, emac_interrupt, priv);
if (ret != 0)
{
nerr("ERROR: Failed attach interrupt\n");
ret = -ENOMEM;
goto errout_with_attachirq;
}
/* Initialize the driver structure */
priv->dev.d_ifup = emac_ifup; /* I/F up (new IP address) callback */
@@ -2098,7 +2091,7 @@ int esp32_emac_init(void)
return 0;
errout_with_attachirq:
esp32_teardown_irq(priv->cpu, ESP32_PERIPH_EMAC, priv->cpuint);
esp_teardown_irq(ESP32_PERIPH_EMAC, priv->cpuint);
error:
return ret;
arch/xtensa/src/esp32/esp32_freerun.c
-1
View File
@@ -36,7 +36,6 @@
#include <nuttx/clock.h>
#include <nuttx/spinlock.h>
#include "esp32_clockconfig.h"
#include "esp32_freerun.h"
#ifdef CONFIG_ESP32_FREERUN
arch/xtensa/src/esp32/esp32_gpio.c
-625
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_gpio.h
-273
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_i2c.c
+30 -40
View File
@@ -47,8 +47,8 @@
#include <arch/board/board.h>
#include "esp32_i2c.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "xtensa.h"
#include "hardware/esp32_gpio_sigmap.h"
@@ -648,22 +648,19 @@ static void esp32_i2c_init(struct esp32_i2c_priv_s *priv)
{
const struct esp32_i2c_config_s *config = priv->config;
esp32_gpiowrite(config->scl_pin, 1);
esp32_gpiowrite(config->sda_pin, 1);
esp_gpiowrite(config->scl_pin, 1);
esp_gpiowrite(config->sda_pin, 1);
esp32_configgpio(config->scl_pin, INPUT |
esp_configgpio(config->scl_pin, INPUT | OPEN_DRAIN | FUNCTION_3);
esp_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0);
esp_gpio_matrix_in(config->scl_pin, config->scl_insig, 0);
esp_configgpio(config->sda_pin, INPUT |
OUTPUT |
OPEN_DRAIN |
FUNCTION_3);
esp32_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0);
esp32_gpio_matrix_in(config->scl_pin, config->scl_insig, 0);
esp32_configgpio(config->sda_pin, INPUT |
OUTPUT |
OPEN_DRAIN |
FUNCTION_3);
esp32_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0);
esp32_gpio_matrix_in(config->sda_pin, config->sda_insig, 0);
esp_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0);
esp_gpio_matrix_in(config->sda_pin, config->sda_insig, 0);
modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, config->clk_bit);
modifyreg32(DPORT_PERIP_RST_EN_REG, config->rst_bit, 0);
@@ -1008,19 +1005,19 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv)
/* Use GPIO configuration to un-wedge the bus */
esp32_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN);
esp32_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp32_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN);
esp32_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN);
esp_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN);
esp_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0);
/* Set SDA to high */
esp32_gpiowrite(config->sda_pin, 1);
esp_gpiowrite(config->sda_pin, 1);
/* Clock the bus until any slaves currently driving it let it go. */
clock_count = 0;
while (!esp32_gpioread(config->sda_pin))
while (!esp_gpioread(config->sda_pin))
{
/* Give up if we have tried too hard */
@@ -1036,7 +1033,7 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv)
*/
stretch_count = 0;
while (!esp32_gpioread(config->scl_pin))
while (!esp_gpioread(config->scl_pin))
{
/* Give up if we have tried too hard */
@@ -1051,12 +1048,12 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv)
/* Drive SCL low */
esp32_gpiowrite(config->scl_pin, 0);
esp_gpiowrite(config->scl_pin, 0);
up_udelay(10);
/* Drive SCL high again */
esp32_gpiowrite(config->scl_pin, 1);
esp_gpiowrite(config->scl_pin, 1);
up_udelay(10);
}
@@ -1064,13 +1061,13 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv)
* state machines.
*/
esp32_gpiowrite(config->sda_pin, 0);
esp_gpiowrite(config->sda_pin, 0);
up_udelay(10);
esp32_gpiowrite(config->scl_pin, 0);
esp_gpiowrite(config->scl_pin, 0);
up_udelay(10);
esp32_gpiowrite(config->scl_pin, 1);
esp_gpiowrite(config->scl_pin, 1);
up_udelay(10);
esp32_gpiowrite(config->sda_pin, 1);
esp_gpiowrite(config->sda_pin, 1);
up_udelay(10);
ret = OK;
@@ -1501,8 +1498,11 @@ struct i2c_master_s *esp32_i2cbus_initialize(int port)
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, config->periph,
1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(config->periph,
1,
ESP_IRQ_TRIGGER_LEVEL,
esp32_i2c_irq,
priv);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type */
@@ -1513,16 +1513,6 @@ struct i2c_master_s *esp32_i2cbus_initialize(int port)
return NULL;
}
ret = irq_attach(config->irq, esp32_i2c_irq, priv);
if (ret != OK)
{
esp32_teardown_irq(priv->cpu, config->periph, priv->cpuint);
priv->refs--;
nxmutex_unlock(&priv->lock);
return NULL;
}
up_enable_irq(config->irq);
#endif
@@ -1560,7 +1550,7 @@ int esp32_i2cbus_uninitialize(struct i2c_master_s *dev)
#ifndef CONFIG_I2C_POLLED
up_disable_irq(priv->config->irq);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
esp_teardown_irq(priv->config->periph, priv->cpuint);
#endif
esp32_i2c_deinit(priv);
arch/xtensa/src/esp32/esp32_i2s.c
+38 -45
View File
@@ -52,8 +52,8 @@
#include <arch/board/board.h>
#include "esp32_i2s.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp32_dma.h"
#include "xtensa.h"
@@ -1467,9 +1467,9 @@ static void i2s_configure(struct esp32_i2s_s *priv)
if (priv->config->dout_pin != I2S_GPIO_UNUSED)
{
esp32_gpiowrite(priv->config->dout_pin, 1);
esp32_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(priv->config->dout_pin,
esp_gpiowrite(priv->config->dout_pin, 1);
esp_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(priv->config->dout_pin,
priv->config->dout_outsig, 0, 0);
}
@@ -1477,8 +1477,8 @@ static void i2s_configure(struct esp32_i2s_s *priv)
if (priv->config->din_pin != I2S_GPIO_UNUSED)
{
esp32_configgpio(priv->config->din_pin, INPUT_FUNCTION_3);
esp32_gpio_matrix_in(priv->config->din_pin,
esp_configgpio(priv->config->din_pin, INPUT_FUNCTION_3);
esp_gpio_matrix_in(priv->config->din_pin,
priv->config->din_insig, 0);
}
@@ -1488,14 +1488,14 @@ static void i2s_configure(struct esp32_i2s_s *priv)
{
/* For "tx + slave" mode, select TX signal index for ws and bck */
esp32_gpiowrite(priv->config->ws_pin, 1);
esp32_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3);
esp32_gpio_matrix_in(priv->config->ws_pin,
esp_gpiowrite(priv->config->ws_pin, 1);
esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3);
esp_gpio_matrix_in(priv->config->ws_pin,
priv->config->ws_out_insig, 0);
esp32_gpiowrite(priv->config->bclk_pin, 1);
esp32_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3);
esp32_gpio_matrix_in(priv->config->bclk_pin,
esp_gpiowrite(priv->config->bclk_pin, 1);
esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3);
esp_gpio_matrix_in(priv->config->bclk_pin,
priv->config->bclk_out_insig, 0);
}
else
@@ -1504,14 +1504,14 @@ static void i2s_configure(struct esp32_i2s_s *priv)
* index for ws and bck.
*/
esp32_gpiowrite(priv->config->ws_pin, 1);
esp32_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3);
esp32_gpio_matrix_in(priv->config->ws_pin,
esp_gpiowrite(priv->config->ws_pin, 1);
esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3);
esp_gpio_matrix_in(priv->config->ws_pin,
priv->config->ws_in_insig, 0);
esp32_gpiowrite(priv->config->bclk_pin, 1);
esp32_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3);
esp32_gpio_matrix_in(priv->config->bclk_pin,
esp_gpiowrite(priv->config->bclk_pin, 1);
esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3);
esp_gpio_matrix_in(priv->config->bclk_pin,
priv->config->bclk_in_insig, 0);
}
}
@@ -1528,8 +1528,8 @@ static void i2s_configure(struct esp32_i2s_s *priv)
i2sinfo("Configuring GPIO%" PRIu8 " to output master clock\n",
priv->config->mclk_pin);
esp32_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2);
esp32_gpio_matrix_out(priv->config->mclk_pin,
esp_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2);
esp_gpio_matrix_out(priv->config->mclk_pin,
SIG_GPIO_OUT_IDX, 0, 0);
if (priv->config->mclk_pin == 0)
@@ -1553,14 +1553,14 @@ static void i2s_configure(struct esp32_i2s_s *priv)
{
/* For "rx + master" mode, select RX signal index for ws and bck */
esp32_gpiowrite(priv->config->ws_pin, 1);
esp32_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(priv->config->ws_pin,
esp_gpiowrite(priv->config->ws_pin, 1);
esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(priv->config->ws_pin,
priv->config->ws_in_outsig, 0, 0);
esp32_gpiowrite(priv->config->bclk_pin, 1);
esp32_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(priv->config->bclk_pin,
esp_gpiowrite(priv->config->bclk_pin, 1);
esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(priv->config->bclk_pin,
priv->config->bclk_in_outsig, 0, 0);
}
else
@@ -1569,14 +1569,14 @@ static void i2s_configure(struct esp32_i2s_s *priv)
* index for ws and bck.
*/
esp32_gpiowrite(priv->config->ws_pin, 1);
esp32_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(priv->config->ws_pin,
esp_gpiowrite(priv->config->ws_pin, 1);
esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(priv->config->ws_pin,
priv->config->ws_out_outsig, 0, 0);
esp32_gpiowrite(priv->config->bclk_pin, 1);
esp32_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(priv->config->bclk_pin,
esp_gpiowrite(priv->config->bclk_pin, 1);
esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(priv->config->bclk_pin,
priv->config->bclk_out_outsig, 0, 0);
}
}
@@ -3004,24 +3004,17 @@ static int i2s_dma_setup(struct esp32_i2s_s *priv)
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(priv->config->periph,
1,
ESP_IRQ_TRIGGER_LEVEL,
i2s_interrupt,
priv);
if (priv->cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
return priv->cpuint;
}
ret = irq_attach(priv->config->irq, i2s_interrupt, priv);
if (ret != OK)
{
i2serr("Couldn't attach IRQ to handler.\n");
esp32_teardown_irq(priv->cpu,
priv->config->periph,
priv->cpuint);
return ret;
}
return OK;
}
arch/xtensa/src/esp32/esp32_idle.c
+20 -57
View File
@@ -35,17 +35,22 @@
#include <nuttx/power/pm.h>
#include <arch/board/board.h>
#include "esp32_pm.h"
#include "espressif/esp_pm.h"
#include "xtensa.h"
#ifdef CONFIG_ESP32_RT_TIMER
#include "esp32_rt_timer.h"
#ifdef CONFIG_ESPRESSIF_HR_TIMER
#include "esp_hr_timer.h"
#endif
#ifdef CONFIG_SCHED_TICKLESS
#include "esp32_tickless.h"
#endif
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
#include "esp_private/pm_impl.h"
#include "platform/os.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -113,58 +118,11 @@ static spinlock_t g_esp32_idle_lock = SP_UNLOCKED;
#ifdef CONFIG_PM
static void esp32_idlepm(void)
{
irqstate_t flags;
#ifdef CONFIG_ESP32_AUTO_SLEEP
flags = spin_lock_irqsave(&g_esp32_idle_lock);
if (esp32_pm_lockstatus() == 0)
{
uint64_t os_start_us;
uint64_t os_end_us;
uint64_t os_step_us;
uint64_t hw_start_us;
uint64_t hw_end_us;
uint64_t hw_step_us;
uint64_t rtc_diff_us;
struct timespec ts;
uint64_t os_idle_us = up_get_idletime();
uint64_t hw_idle_us = rt_timer_get_alarm();
uint64_t sleep_us = MIN(os_idle_us, hw_idle_us);
if (sleep_us > EXPECTED_IDLE_TIME_US)
{
sleep_us -= EARLY_WAKEUP_US;
esp32_sleep_enable_timer_wakeup(sleep_us);
up_timer_gettime(&ts);
os_start_us = (ts.tv_sec * USEC_PER_SEC +
ts.tv_nsec / NSEC_PER_USEC);
hw_start_us = rt_timer_time_us();
esp32_light_sleep_start(&rtc_diff_us);
hw_end_us = rt_timer_time_us();
up_timer_gettime(&ts);
os_end_us = (ts.tv_sec * USEC_PER_SEC +
ts.tv_nsec / NSEC_PER_USEC);
hw_step_us = rtc_diff_us - (hw_end_us - hw_start_us);
os_step_us = rtc_diff_us - (os_end_us - os_start_us);
DEBUGASSERT(hw_step_us > 0);
DEBUGASSERT(os_step_us > 0);
/* Adjust current RT timer by a certain value. */
rt_timer_calibration(hw_step_us);
/* Adjust system time by a certain value. */
up_step_idletime((uint32_t)os_step_us);
}
}
spin_unlock_irqrestore(&g_esp32_idle_lock, flags);
esp_os_application_sleep();
#else /* CONFIG_ESP32_AUTO_SLEEP */
static enum pm_state_e oldstate = PM_NORMAL;
irqstate_t flags;
enum pm_state_e newstate;
int ret;
int count;
@@ -226,8 +184,8 @@ static void esp32_idlepm(void)
{
/* Enter Force-sleep mode */
esp32_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
esp_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
}
break;
@@ -235,8 +193,8 @@ static void esp32_idlepm(void)
{
/* Enter Deep-sleep mode */
esp32_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
esp_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
}
default:
@@ -289,8 +247,13 @@ void up_idle(void)
*/
BEGIN_IDLE();
#if XCHAL_HAVE_INTERRUPTS
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
esp_pm_impl_idle_hook();
esp_pm_impl_waiti();
#else
# if XCHAL_HAVE_INTERRUPTS
__asm__ __volatile__ ("waiti 0");
# endif
#endif
END_IDLE();
arch/xtensa/src/esp32/esp32_irq.c
-1335
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_irq.h
-263
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_ledc.c
+4 -4
View File
@@ -31,8 +31,8 @@
#include <debug.h>
#include <errno.h>
#include "esp32_clockconfig.h"
#include "esp32_gpio.h"
#include "esp_clk.h"
#include "esp_gpio.h"
#include "esp32_ledc.h"
#include "xtensa.h"
@@ -576,8 +576,8 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev)
pwminfo("channel%d --> pin%d\n", priv->chans[i].num,
priv->chans[i].pin);
esp32_configgpio(priv->chans[i].pin, OUTPUT | PULLUP);
esp32_gpio_matrix_out(priv->chans[i].pin,
esp_configgpio(priv->chans[i].pin, OUTPUT | PULLUP);
esp_gpio_matrix_out(priv->chans[i].pin,
LEDC_LS_SIG_OUT0_IDX + priv->chans[i].num,
0, 0);
}
arch/xtensa/src/esp32/esp32_libc_stubs.c
+51
View File
@@ -35,6 +35,7 @@
#include <nuttx/signal.h>
#include <nuttx/mutex.h>
#include <nuttx/lib/lib.h>
#include <nuttx/sched.h>
#include "rom/esp32_libc_stubs.h"
@@ -165,6 +166,11 @@ void _raise_r(struct _reent *r)
void _lock_init(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
*lock = 0;
mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t));
@@ -176,6 +182,11 @@ void _lock_init(_lock_t *lock)
void _lock_init_recursive(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
*lock = 0;
rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t));
@@ -187,6 +198,11 @@ void _lock_init_recursive(_lock_t *lock)
void _lock_close(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
mutex_t *mutex = (mutex_t *)(*lock);
nxmutex_destroy(mutex);
@@ -196,6 +212,11 @@ void _lock_close(_lock_t *lock)
void _lock_close_recursive(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
rmutex_t *rmutex = (rmutex_t *)(*lock);
nxrmutex_destroy(rmutex);
@@ -205,6 +226,11 @@ void _lock_close_recursive(_lock_t *lock)
void _lock_acquire(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
if ((*lock) == 0)
{
mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t));
@@ -219,6 +245,11 @@ void _lock_acquire(_lock_t *lock)
void _lock_acquire_recursive(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
if ((*lock) == 0)
{
rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t));
@@ -233,6 +264,11 @@ void _lock_acquire_recursive(_lock_t *lock)
int _lock_try_acquire(_lock_t *lock)
{
if (sched_idletask())
{
return -EPERM;
}
if ((*lock) == 0)
{
mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t));
@@ -247,6 +283,11 @@ int _lock_try_acquire(_lock_t *lock)
int _lock_try_acquire_recursive(_lock_t *lock)
{
if (sched_idletask())
{
return -EPERM;
}
if ((*lock) == 0)
{
rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t));
@@ -261,6 +302,11 @@ int _lock_try_acquire_recursive(_lock_t *lock)
void _lock_release(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
mutex_t *mutex = (mutex_t *)(*lock);
nxmutex_unlock(mutex);
@@ -268,6 +314,11 @@ void _lock_release(_lock_t *lock)
void _lock_release_recursive(_lock_t *lock)
{
if (sched_idletask())
{
return;
}
rmutex_t *rmutex = (rmutex_t *)(*lock);
nxrmutex_unlock(rmutex);
arch/xtensa/src/esp32/esp32_oneshot.c
+1 -1
View File
@@ -37,8 +37,8 @@
#include "hardware/esp32_soc.h"
#include "esp_clk.h"
#include "esp32_tim.h"
#include "esp32_clockconfig.h"
#include "esp32_oneshot.h"
#ifdef CONFIG_ESP32_ONESHOT
arch/xtensa/src/esp32/esp32_pm.c
-1167
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_pm.h
-248
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_pminitialize.c
+1 -1
View File
@@ -26,7 +26,7 @@
#include <nuttx/power/pm.h>
#include "xtensa.h"
#include "esp32_pm.h"
#include "espressif/esp_pm.h"
#ifdef CONFIG_PM
arch/xtensa/src/esp32/esp32_psram.c
+44 -45
View File
@@ -32,19 +32,18 @@
#include <nuttx/signal.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp32_rtc.h"
#include "esp32_gpio.h"
#include "espressif/esp_rtc.h"
#include "esp_gpio.h"
#include "esp32_psram.h"
#include "hardware/esp32_spi.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_iomux.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
#include "hardware/esp32_gpio_sigmap.h"
#include "rom/esp32_efuse.h"
#include "rom/esp32_spiflash.h"
#include "hardware/esp32_efuse.h"
#ifdef CONFIG_ESP32_SPIRAM
@@ -1144,12 +1143,12 @@ psram_2t_mode_enable(psram_spi_num_t spi_num)
*/
GPIO_OUTPUT_SET(CONFIG_D0WD_PSRAM_CS_IO, 1);
esp32_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
esp_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
esp32_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
esp32_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
esp_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
esp_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
esp_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
esp_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
uint32_t w_data_2t[4] =
{
@@ -1166,12 +1165,12 @@ psram_2t_mode_enable(psram_spi_num_t spi_num)
psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
psram_cmd_end(spi_num);
esp32_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
esp32_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
esp_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
esp_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
esp_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
esp_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
esp32_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
esp_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
/* setp4: send cmd 0x5f
* send one more bit clock after send cmd
@@ -1403,16 +1402,16 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io,
* version.
*/
esp32_gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
esp32_gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
esp32_gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
esp32_gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
esp32_gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
esp32_gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
esp_gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
esp_gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
esp_gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
esp_gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
esp_gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
esp_gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
esp_gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
esp_gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
esp_gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
esp_gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
/* select pin function gpio */
@@ -1421,23 +1420,23 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io,
{
/* flash clock signal should come from IO MUX. */
esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_2);
esp_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_2);
}
else
{
/* flash clock signal should come from GPIO matrix. */
esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_3);
esp_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_3);
}
esp32_configgpio(psram_io->flash_cs_io, OUTPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_cs_io, OUTPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_clk_io, OUTPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_spiq_sd0_io, OUTPUT | INPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_spid_sd1_io, OUTPUT | INPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_spihd_sd2_io,
esp_configgpio(psram_io->flash_cs_io, OUTPUT | FUNCTION_3);
esp_configgpio(psram_io->psram_cs_io, OUTPUT | FUNCTION_3);
esp_configgpio(psram_io->psram_clk_io, OUTPUT | FUNCTION_3);
esp_configgpio(psram_io->psram_spiq_sd0_io, OUTPUT | INPUT | FUNCTION_3);
esp_configgpio(psram_io->psram_spid_sd1_io, OUTPUT | INPUT | FUNCTION_3);
esp_configgpio(psram_io->psram_spihd_sd2_io,
OUTPUT | INPUT | FUNCTION_3);
esp32_configgpio(psram_io->psram_spiwp_sd3_io,
esp_configgpio(psram_io->psram_spiwp_sd3_io,
OUTPUT | INPUT | FUNCTION_3);
#if 0
@@ -1630,7 +1629,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */
switch (mode)
{
case PSRAM_CACHE_F80M_S80M:
esp32_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
esp_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
break;
case PSRAM_CACHE_F80M_S40M:
case PSRAM_CACHE_F40M_S40M:
@@ -1649,21 +1648,21 @@ psram_enable(int mode, int vaddrmode) /* psram init */
*/
minfo("clk_mode == PSRAM_CLK_MODE_DCLK\n");
esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_28,
esp_gpio_matrix_out(PSRAM_INTERNAL_IO_28,
SPICLK_OUT_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_INTERNAL_IO_28,
esp_gpio_matrix_in(PSRAM_INTERNAL_IO_28,
SIG_IN_FUNC224_IDX, 0);
esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_29,
esp_gpio_matrix_out(PSRAM_INTERNAL_IO_29,
SIG_IN_FUNC224_IDX, 0, 0);
esp32_gpio_matrix_in(PSRAM_INTERNAL_IO_29,
esp_gpio_matrix_in(PSRAM_INTERNAL_IO_29,
SIG_IN_FUNC225_IDX, 0);
esp32_gpio_matrix_out(psram_io.psram_clk_io,
esp_gpio_matrix_out(psram_io.psram_clk_io,
SIG_IN_FUNC225_IDX, 0, 0);
}
else
{
minfo("clk_io == OUT_IDX\n");
esp32_gpio_matrix_out(psram_io.psram_clk_io,
esp_gpio_matrix_out(psram_io.psram_clk_io,
SPICLK_OUT_IDX, 0, 0);
}
break;
@@ -1706,7 +1705,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */
* ourselves
*/
esp32_gpio_matrix_out(psram_io.psram_clk_io,
esp_gpio_matrix_out(psram_io.psram_clk_io,
PSRAM_CLK_SIGNAL, 0, 0);
/* use spi3 clock,but use spi1 data/cs wires
@@ -1737,9 +1736,9 @@ psram_enable(int mode, int vaddrmode) /* psram init */
*/
s_clk_mode = PSRAM_CLK_MODE_NORM;
esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
esp32_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
esp_gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
esp_gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
esp_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
}
/* Update cs timing according to psram driving method. */
arch/xtensa/src/esp32/esp32_qencoder.c
+8 -8
View File
@@ -38,8 +38,8 @@
#include <arch/board/board.h>
#include "chip.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "xtensa.h"
#include "hardware/esp32_soc.h"
@@ -608,19 +608,19 @@ static int esp32_setup(struct qe_lowerhalf_s *lower)
/* Configure GPIO pins as Input with Pull-Up enabled */
esp32_configgpio(priv->config->ch0_gpio, INPUT_FUNCTION_3 | PULLUP);
esp32_configgpio(priv->config->ch1_gpio, INPUT_FUNCTION_3 | PULLUP);
esp_configgpio(priv->config->ch0_gpio, INPUT_FUNCTION_3 | PULLUP);
esp_configgpio(priv->config->ch1_gpio, INPUT_FUNCTION_3 | PULLUP);
/* Connect Channel A (ch0_gpio) and Channel B (ch1_gpio) crossed for X4 */
esp32_gpio_matrix_in(priv->config->ch0_gpio,
esp_gpio_matrix_in(priv->config->ch0_gpio,
priv->config->ch0_pulse_sig, 0);
esp32_gpio_matrix_in(priv->config->ch1_gpio,
esp_gpio_matrix_in(priv->config->ch1_gpio,
priv->config->ch0_ctrl_sig, 0);
esp32_gpio_matrix_in(priv->config->ch1_gpio,
esp_gpio_matrix_in(priv->config->ch1_gpio,
priv->config->ch1_pulse_sig, 0);
esp32_gpio_matrix_in(priv->config->ch0_gpio,
esp_gpio_matrix_in(priv->config->ch0_gpio,
priv->config->ch1_ctrl_sig, 0);
/* Clear the Reset bit to enable the Pulse Counter */
arch/xtensa/src/esp32/esp32_resetcause.c
+1 -1
View File
@@ -30,7 +30,7 @@
#include <nuttx/board.h>
#include "xtensa.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
#include "esp32_resetcause.h"
arch/xtensa/src/esp32/esp32_rng.c
+1 -2
View File
@@ -40,9 +40,8 @@
#include <arch/xtensa/core_macros.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/wdev_reg.h"
#include "esp32_clockconfig.h"
#include "esp_random.h"
arch/xtensa/src/esp32/esp32_rt_timer.c
-768
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rt_timer.h
-244
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rtc.c
-2277
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rtc.h
-713
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rtc_gpio.c
+115 -15
View File
@@ -34,7 +34,7 @@
#include <nuttx/arch.h>
#include "xtensa.h"
#include "esp32_irq.h"
#include "espressif/esp_irq.h"
#include "esp32_rtc_gpio.h"
#include "hardware/esp32_pinmap.h"
#include "hardware/esp32_rtc_io.h"
@@ -57,6 +57,14 @@ enum rtcio_lh_out_mode_e
RTCIO_OUTPUT_OD = 0x1, /* RTCIO output mode is open-drain. */
};
/* Structure to store RTC GPIO interrupt handlers */
struct rtcio_handler_s
{
xcpt_t handler; /* User interrupt handler */
void *arg; /* Argument for handler */
};
/****************************************************************************
* Private Data
****************************************************************************/
@@ -64,6 +72,7 @@ enum rtcio_lh_out_mode_e
#ifdef CONFIG_ESP32_RTCIO_IRQ
static int g_rtcio_cpuint;
static uint32_t last_status;
static struct rtcio_handler_s g_rtcio_handlers[ESP32_NIRQ_RTCIO_PERIPH];
#endif
static const uint32_t rtc_gpio_to_addr[] =
@@ -119,6 +128,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num)
*
* Input Parameters:
* irq - The IRQ number;
* context - The interrupt context;
* reg_status - Pointer to a copy of the interrupt status register.
*
* Returned Value:
@@ -127,7 +137,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num)
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
static void rtcio_dispatch(int irq, uint32_t *reg_status)
static void rtcio_dispatch(int irq, void *context, uint32_t *reg_status)
{
uint32_t status = *reg_status;
uint32_t mask;
@@ -142,11 +152,14 @@ static void rtcio_dispatch(int irq, uint32_t *reg_status)
mask = (UINT32_C(1) << i);
if ((status & mask) != 0)
{
/* Yes... perform the second level dispatch. The IRQ context will
* contain the contents of the status register.
*/
/* Call the registered handler if one exists */
irq_dispatch(irq + i, (void *)reg_status);
if (g_rtcio_handlers[i].handler != NULL)
{
g_rtcio_handlers[i].handler(irq,
(void *)reg_status,
g_rtcio_handlers[i].arg);
}
/* Clear the bit in the status so that we might execute this loop
* sooner.
@@ -184,7 +197,7 @@ static int rtcio_interrupt(int irq, void *context, void *arg)
/* Dispatch pending interrupts in the RTC status register */
rtcio_dispatch(ESP32_FIRST_RTCIOIRQ_PERIPH, &last_status);
rtcio_dispatch(irq, context, &last_status);
return OK;
}
@@ -327,7 +340,7 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr)
}
/****************************************************************************
* Name: esp32_rtcioirqinitialize
* Name: esp_rtcioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
@@ -336,18 +349,27 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr)
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
void esp32_rtcioirqinitialize(void)
void esp_rtcioirqinitialize(void)
{
/* Setup the RTCIO interrupt. */
int i;
int cpu = this_cpu();
g_rtcio_cpuint = esp32_setup_irq(cpu, ESP32_PERIPH_RTC_CORE,
1, ESP32_CPUINT_LEVEL);
/* Initialize handler array */
for (i = 0; i < ESP32_NIRQ_RTCIO_PERIPH; i++)
{
g_rtcio_handlers[i].handler = NULL;
g_rtcio_handlers[i].arg = NULL;
}
/* Setup the RTCIO interrupt with handler. */
g_rtcio_cpuint = esp_setup_irq(ESP32_PERIPH_RTC_CORE,
1, ESP_IRQ_TRIGGER_LEVEL,
rtcio_interrupt, NULL);
DEBUGASSERT(g_rtcio_cpuint >= 0);
/* Attach and enable the interrupt handler */
/* Enable the interrupt */
DEBUGVERIFY(irq_attach(ESP32_IRQ_RTC_CORE, rtcio_interrupt, NULL));
up_enable_irq(ESP32_IRQ_RTC_CORE);
}
#endif
@@ -417,3 +439,81 @@ void esp32_rtcioirqdisable(int irq)
up_enable_irq(ESP32_IRQ_RTC_CORE);
}
#endif
/****************************************************************************
* Name: esp32_rtcioirqattach
*
* Description:
* Attach an interrupt handler to a specified RTC IRQ
*
* Input Parameters:
* irq - RTC IRQ number to attach the handler to
* handler - Interrupt handler function
* arg - Argument to pass to the handler
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
int esp32_rtcioirqattach(int irq, xcpt_t handler, void *arg)
{
int bit;
DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_PERIPH &&
irq <= ESP32_LAST_RTCIOIRQ_PERIPH);
/* Convert the IRQ number to the corresponding bit */
bit = irq - ESP32_FIRST_RTCIOIRQ_PERIPH;
DEBUGASSERT(bit >= 0 && bit < ESP32_NIRQ_RTCIO_PERIPH);
/* Store the handler and argument */
g_rtcio_handlers[bit].handler = handler;
g_rtcio_handlers[bit].arg = arg;
return OK;
}
#endif
/****************************************************************************
* Name: esp32_rtcioirqdetach
*
* Description:
* Detach an interrupt handler from a specified RTC IRQ
*
* Input Parameters:
* irq - RTC IRQ number to detach the handler from
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
int esp32_rtcioirqdetach(int irq)
{
int bit;
DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_PERIPH &&
irq <= ESP32_LAST_RTCIOIRQ_PERIPH);
/* Convert the IRQ number to the corresponding bit */
bit = irq - ESP32_FIRST_RTCIOIRQ_PERIPH;
DEBUGASSERT(bit >= 0 && bit < ESP32_NIRQ_RTCIO_PERIPH);
/* Clear the handler and argument */
g_rtcio_handlers[bit].handler = NULL;
g_rtcio_handlers[bit].arg = NULL;
return OK;
}
#endif
arch/xtensa/src/esp32/esp32_rtc_gpio.h
+47 -49
View File
@@ -25,9 +25,8 @@
* Included Files
****************************************************************************/
#include "hardware/esp32_gpio.h"
#include "hardware/esp32_rtc_io.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
/****************************************************************************
* Pre-processor Definitions
@@ -163,50 +162,6 @@ typedef uint16_t rtcio_pinattr_t;
* Public Data
****************************************************************************/
static const int g_gpio_to_rtcio_map[GPIO_PIN_COUNT + 1] =
{
RTCIO_GPIO0_CHANNEL, /* GPIO0 */
-1, /* GPIO1 not supported */
RTCIO_GPIO2_CHANNEL, /* GPIO2 */
-1, /* GPIO3 not supported */
RTCIO_GPIO4_CHANNEL, /* GPIO4 */
-1, /* GPIO5 not supported */
-1, /* GPIO6 not supported */
-1, /* GPIO7 not supported */
-1, /* GPIO8 not supported */
-1, /* GPIO9 not supported */
-1, /* GPIO10 not supported */
-1, /* GPIO11 not supported */
RTCIO_GPIO12_CHANNEL, /* GPIO12 */
RTCIO_GPIO13_CHANNEL, /* GPIO13 */
RTCIO_GPIO14_CHANNEL, /* GPIO14 */
RTCIO_GPIO15_CHANNEL, /* GPIO15 */
-1, /* GPIO16 not supported */
-1, /* GPIO17 not supported */
-1, /* GPIO18 not supported */
-1, /* GPIO19 not supported */
-1, /* GPIO20 not supported */
-1, /* GPIO21 not supported */
-1, /* GPIO22 not supported */
-1, /* GPIO23 not supported */
-1, /* GPIO24 not supported */
RTCIO_GPIO25_CHANNEL, /* GPIO25 */
RTCIO_GPIO26_CHANNEL, /* GPIO26 */
RTCIO_GPIO27_CHANNEL, /* GPIO27 */
-1, /* GPIO28 not supported */
-1, /* GPIO29 not supported */
-1, /* GPIO30 not supported */
-1, /* GPIO31 not supported */
RTCIO_GPIO32_CHANNEL, /* GPIO32 */
RTCIO_GPIO33_CHANNEL, /* GPIO33 */
RTCIO_GPIO34_CHANNEL, /* GPIO34 */
RTCIO_GPIO35_CHANNEL, /* GPIO35 */
RTCIO_GPIO36_CHANNEL, /* GPIO36 */
RTCIO_GPIO37_CHANNEL, /* GPIO37 */
RTCIO_GPIO38_CHANNEL, /* GPIO38 */
RTCIO_GPIO39_CHANNEL /* GPIO39 */
};
static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] =
{
/* REG
@@ -542,7 +497,7 @@ static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] =
int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr);
/****************************************************************************
* Name: esp32_rtcioirqinitialize
* Name: esp_rtcioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
@@ -551,9 +506,9 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr);
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
void esp32_rtcioirqinitialize(void);
void esp_rtcioirqinitialize(void);
#else
# define esp32_rtcioirqinitialize()
# define esp_rtcioirqinitialize()
#endif
/****************************************************************************
@@ -584,4 +539,47 @@ void esp32_rtcioirqdisable(int irq);
# define esp32_rtcioirqdisable(irq)
#endif
/****************************************************************************
* Name: esp32_rtcioirqattach
*
* Description:
* Attach an interrupt handler to a specified RTC IRQ
*
* Input Parameters:
* irq - RTC IRQ number to attach the handler to
* handler - Interrupt handler function
* arg - Argument to pass to the handler
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
int esp32_rtcioirqattach(int irq, xcpt_t handler, void *arg);
#else
# define esp32_rtcioirqattach(irq, handler, arg) (-ENOSYS)
#endif
/****************************************************************************
* Name: esp32_rtcioirqdetach
*
* Description:
* Detach an interrupt handler from a specified RTC IRQ
*
* Input Parameters:
* irq - RTC IRQ number to detach the handler from
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_RTCIO_IRQ
int esp32_rtcioirqdetach(int irq);
#else
# define esp32_rtcioirqdetach(irq) (-ENOSYS)
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_GPIO_H */
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c
-559
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_serial.c
+38 -52
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_sha.c
+13 -2
View File
@@ -38,8 +38,10 @@
#include "xtensa.h"
#include "hal/sha_ll.h"
#include "hal/sha_hal.h"
#include "periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp32_sha.h"
@@ -384,7 +386,17 @@ int esp32_sha_init(void)
{
if (!g_sha_inited)
{
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC()
{
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
#if SOC_SHA_CRYPTO_DMA
crypto_dma_ll_enable_bus_clock(true);
crypto_dma_ll_reset_register();
#endif
}
g_sha_inited = true;
}
else
@@ -396,4 +408,3 @@ int esp32_sha_init(void)
}
#endif
arch/xtensa/src/esp32/esp32_spi.c
+31 -40
View File
@@ -47,8 +47,8 @@
#include <arch/board/board.h>
#include "esp32_spi.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp32_dma.h"
#include "xtensa.h"
@@ -562,7 +562,7 @@ static void esp32_spi_select(struct spi_dev_s *dev,
#ifdef CONFIG_ESP32_SPI_SWCS
struct esp32_spi_priv_s *priv = (struct esp32_spi_priv_s *)dev;
esp32_gpiowrite(priv->config->cs_pin, !selected);
esp_gpiowrite(priv->config->cs_pin, !selected);
#endif
spiinfo("devid: %08" PRIx32 " CS: %s\n",
@@ -1344,66 +1344,66 @@ static void esp32_spi_init(struct spi_dev_s *dev)
const struct esp32_spi_config_s *config = priv->config;
uint32_t regval;
esp32_gpiowrite(config->cs_pin, 1);
esp32_gpiowrite(config->clk_pin, 1);
esp_gpiowrite(config->cs_pin, 1);
esp_gpiowrite(config->clk_pin, 1);
if (config->flags & ESP32_SPI_IO_W)
{
esp32_gpiowrite(config->mosi_pin, 1);
esp_gpiowrite(config->mosi_pin, 1);
}
if (config->flags & ESP32_SPI_IO_R)
{
esp32_gpiowrite(config->miso_pin, 1);
esp_gpiowrite(config->miso_pin, 1);
}
#ifdef CONFIG_ESP32_SPI_SWCS
esp32_configgpio(config->cs_pin, OUTPUT);
esp32_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->cs_pin, OUTPUT);
esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
#endif
if (esp32_spi_iomux(priv))
{
#ifndef CONFIG_ESP32_SPI_SWCS
esp32_configgpio(config->cs_pin, OUTPUT_FUNCTION_2);
esp32_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_2);
esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0);
#endif
esp32_configgpio(config->clk_pin, OUTPUT_FUNCTION_2);
esp32_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_2);
esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0);
if (config->flags & ESP32_SPI_IO_W)
{
esp32_configgpio(config->mosi_pin, OUTPUT_FUNCTION_2);
esp32_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_2);
esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0);
}
if (config->flags & ESP32_SPI_IO_R)
{
esp32_configgpio(config->miso_pin, INPUT_FUNCTION_2 | PULLUP);
esp32_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0);
esp_configgpio(config->miso_pin, INPUT_FUNCTION_2 | PULLUP);
esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0);
}
}
else
{
#ifndef CONFIG_ESP32_SPI_SWCS
esp32_configgpio(config->cs_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0);
esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0);
#endif
esp32_configgpio(config->clk_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0);
esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0);
if (config->flags & ESP32_SPI_IO_W)
{
esp32_configgpio(config->mosi_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0);
esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0);
}
if (config->flags & ESP32_SPI_IO_R)
{
esp32_configgpio(config->miso_pin, INPUT_FUNCTION_3 | PULLUP);
esp32_gpio_matrix_in(config->miso_pin, config->miso_insig, 0);
esp_configgpio(config->miso_pin, INPUT_FUNCTION_3 | PULLUP);
esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0);
}
}
@@ -1552,24 +1552,17 @@ struct spi_dev_s *esp32_spibus_initialize(int port)
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(priv->config->periph,
1,
ESP_IRQ_TRIGGER_LEVEL,
esp32_spi_interrupt,
priv);
if (priv->cpuint < 0)
{
nxmutex_unlock(&priv->lock);
return NULL;
}
ret = irq_attach(priv->config->irq, esp32_spi_interrupt, priv);
if (ret != OK)
{
esp32_teardown_irq(priv->cpu,
priv->config->periph,
priv->cpuint);
nxmutex_unlock(&priv->lock);
return NULL;
}
up_enable_irq(priv->config->irq);
}
@@ -1615,9 +1608,7 @@ int esp32_spibus_uninitialize(struct spi_dev_s *dev)
if (priv->config->use_dma)
{
up_disable_irq(priv->config->irq);
esp32_teardown_irq(priv->cpu,
priv->config->periph,
priv->cpuint);
esp_teardown_irq(priv->config->periph, priv->cpuint);
}
esp32_spi_deinit(dev);
arch/xtensa/src/esp32/esp32_spi_slave.c
+43 -42
View File
@@ -49,8 +49,8 @@
#include <arch/board/board.h>
#include "esp32_spi.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp32_dma.h"
#include "xtensa.h"
@@ -874,7 +874,7 @@ static int esp32_spislv_interrupt(int irq, void *context, void *arg)
}
#endif
if (priv->process == true && esp32_gpioread(priv->config->cs_pin))
if (priv->process == true && esp_gpioread(priv->config->cs_pin))
{
priv->process = false;
SPIS_DEV_SELECT(priv->dev, false);
@@ -905,61 +905,61 @@ static void esp32_spislv_initialize(struct spi_slave_ctrlr_s *ctrlr)
const struct esp32_spislv_config_s *config = priv->config;
uint32_t regval;
esp32_gpiowrite(config->cs_pin, 1);
esp32_gpiowrite(config->clk_pin, 1);
esp_gpiowrite(config->cs_pin, 1);
esp_gpiowrite(config->clk_pin, 1);
if (config->flags & ESP32_SPI_IO_R)
{
esp32_gpiowrite(config->mosi_pin, 1);
esp_gpiowrite(config->mosi_pin, 1);
}
#ifdef ESP32_SPI_SLAVE_HAS_TX
if (config->flags & ESP32_SPI_IO_W)
{
esp32_gpiowrite(config->miso_pin, 1);
esp_gpiowrite(config->miso_pin, 1);
}
#endif
if (esp32_spi_iomux(priv))
{
esp32_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP);
esp32_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP);
esp_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP);
esp_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP);
#ifdef ESP32_SPI_SLAVE_HAS_TX
if (config->flags & ESP32_SPI_IO_W)
{
esp32_configgpio(config->miso_pin, OUTPUT_FUNCTION_2);
esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_2);
}
#endif
if (config->flags & ESP32_SPI_IO_R)
{
esp32_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP);
esp_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP);
}
}
else
{
esp32_configgpio(config->cs_pin, INPUT_FUNCTION_3 | PULLUP);
esp32_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0);
esp32_gpio_matrix_in(config->cs_pin, config->cs_insig, 0);
esp_configgpio(config->cs_pin, INPUT_FUNCTION_3 | PULLUP);
esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0);
esp_gpio_matrix_in(config->cs_pin, config->cs_insig, 0);
esp32_configgpio(config->clk_pin, INPUT_FUNCTION_3 | PULLUP);
esp32_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0);
esp32_gpio_matrix_in(config->clk_pin, config->clk_insig, 0);
esp_configgpio(config->clk_pin, INPUT_FUNCTION_3 | PULLUP);
esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0);
esp_gpio_matrix_in(config->clk_pin, config->clk_insig, 0);
if (config->flags & ESP32_SPI_IO_R)
{
esp32_configgpio(config->mosi_pin, INPUT_FUNCTION_3 | PULLUP);
esp32_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0);
esp32_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
esp_configgpio(config->mosi_pin, INPUT_FUNCTION_3 | PULLUP);
esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0);
esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0);
}
#ifdef ESP32_SPI_SLAVE_HAS_TX
if (config->flags & ESP32_SPI_IO_W)
{
esp32_configgpio(config->miso_pin, OUTPUT_FUNCTION_3);
esp32_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
esp32_gpio_matrix_in(config->miso_pin, config->miso_insig, 0);
esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_3);
esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0);
esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0);
}
#endif
}
@@ -1027,7 +1027,7 @@ static void esp32_spislv_initialize(struct spi_slave_ctrlr_s *ctrlr)
esp32_spi_set_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M);
esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M);
esp32_gpioirqenable(ESP32_PIN2IRQ(config->cs_pin), RISING);
esp_gpioirqenable(ESP32_PIN2IRQ(config->cs_pin), RISING);
esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_TRANS_DONE_M);
}
@@ -1050,7 +1050,7 @@ static void esp32_spislv_deinit(struct spi_slave_ctrlr_s *ctrlr)
{
struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr;
esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin));
esp_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin));
esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M);
if (priv->dma_chan)
@@ -1163,7 +1163,7 @@ static void esp32_spislv_unbind(struct spi_slave_ctrlr_s *ctrlr)
up_disable_irq(priv->config->irq);
esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin));
esp_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin));
esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M);
if (priv->dma_chan)
{
@@ -1400,25 +1400,26 @@ struct spi_slave_ctrlr_s *esp32_spislv_ctrlr_initialize(int port)
priv->dma_chan = 0;
}
DEBUGVERIFY(irq_attach(ESP32_PIN2IRQ(priv->config->cs_pin),
esp32_io_interrupt,
priv));
/* Attach IRQ for CS pin interrupt */
ret = esp_gpio_irq(priv->config->cs_pin,
esp32_io_interrupt,
priv);
if (ret < 0)
{
spierr("esp_gpio_irq() failed: %d\n", ret);
spin_unlock_irqrestore(&priv->lock, flags);
return NULL;
}
/* Set up to receive peripheral interrupts on the current CPU */
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph,
1, ESP32_CPUINT_LEVEL);
ret = irq_attach(priv->config->irq, esp32_spislv_interrupt, priv);
if (ret != OK)
{
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
spin_unlock_irqrestore(&priv->lock, flags);
return NULL;
}
priv->cpuint = esp_setup_irq(priv->config->periph,
1,
ESP_IRQ_TRIGGER_LEVEL,
esp32_spislv_interrupt,
priv);
priv->refs++;
@@ -1462,7 +1463,7 @@ int esp32_spislv_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr)
}
up_disable_irq(priv->config->irq);
esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
esp_teardown_irq(priv->config->periph, priv->cpuint);
esp32_spislv_deinit(ctrlr);
spin_unlock_irqrestore(&priv->lock, flags);
arch/xtensa/src/esp32/esp32_spicache.c
-1
View File
@@ -34,7 +34,6 @@
#include <errno.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32_soc.h"
#include "hardware/esp32_spi.h"
arch/xtensa/src/esp32/esp32_spicache.h
-2
View File
@@ -31,8 +31,6 @@
#include <stdint.h>
#include <nuttx/mtd/mtd.h>
#include "xtensa_attr.h"
#ifndef __ASSEMBLY__
#undef EXTERN
arch/xtensa/src/esp32/esp32_spiflash.c
+5 -7
View File
@@ -45,20 +45,18 @@
#include "sched/sched.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "rom/esp32_spiflash.h"
#include "hardware/esp32_soc.h"
#include "hardware/esp32_spi.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_efuse.h"
#include "esp32_spicache.h"
#ifdef CONFIG_ESP32_SPIRAM
#include "esp32_spiram.h"
#endif
#include "esp32_irq.h"
#include "esp_irq.h"
#include "esp32_spiflash.h"
@@ -509,7 +507,7 @@ void esp32_spiflash_opstart(void)
nxsched_set_priority(tcb, saved_priority);
esp32_irq_noniram_disable();
esp_intr_noniram_disable();
spi_disable_cache(cpu);
#ifdef CONFIG_SMP
@@ -548,7 +546,7 @@ void esp32_spiflash_opdone(void)
g_flash_op_complete = true;
esp32_irq_noniram_enable();
esp_intr_noniram_enable();
sched_unlock();
@@ -2509,7 +2507,7 @@ static int spi_flash_op_block_task(int argc, char *argv[])
sched_lock();
esp32_irq_noniram_disable();
esp_intr_noniram_disable();
/* g_flash_op_complete flag is cleared on *this* CPU, otherwise the
* other CPU may reset the flag back to false before this task has a
@@ -2532,7 +2530,7 @@ static int spi_flash_op_block_task(int argc, char *argv[])
/* Restore interrupts that aren't located in IRAM */
esp32_irq_noniram_enable();
esp_intr_noniram_enable();
sched_unlock();
}
arch/xtensa/src/esp32/esp32_spiflash.h
-2
View File
@@ -31,8 +31,6 @@
#include <stdint.h>
#include <nuttx/mtd/mtd.h>
#include "xtensa_attr.h"
#ifndef __ASSEMBLY__
#undef EXTERN
arch/xtensa/src/esp32/esp32_spiram.c
+1 -1
View File
@@ -39,7 +39,7 @@
#include "esp32_spiram.h"
#include "esp32_psram.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32_soc.h"
#include "hardware/esp32_dport.h"
arch/xtensa/src/esp32/esp32_spiram.h
+1 -1
View File
@@ -28,7 +28,7 @@
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "xtensa_attr.h"
#include "esp_attr.h"
/****************************************************************************
* Pre-processor Definitions
arch/xtensa/src/esp32/esp32_start.c
+144 -9
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_start.h
+20
View File
@@ -33,6 +33,26 @@
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: sys_startup_fn
*
* Description:
* Execute the system layer startup function for the current CPU core.
* This function calls the appropriate startup function from the per-CPU
* startup function array (g_startup_fn) based on the current core ID.
* The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the
* g_startup_fn array, and invokes the corresponding startup function.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void sys_startup_fn(void);
/****************************************************************************
* Name: esp32_board_initialize
*
arch/xtensa/src/esp32/esp32_systemreset.c
+1 -1
View File
@@ -30,7 +30,7 @@
#include <nuttx/board.h>
#include "xtensa.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
#include "esp32_systemreset.h"
/****************************************************************************
arch/xtensa/src/esp32/esp32_tickless.c
+9 -3
View File
@@ -61,8 +61,9 @@
#include <arch/board/board.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "xtensa_counter.h"
#include "esp_irq.h"
#include "esp_attr.h"
#ifdef CONFIG_SCHED_TICKLESS
@@ -494,11 +495,16 @@ void up_timer_initialize(void)
/* Attach the timer interrupt */
irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)up_timer_expire, NULL);
esp_setup_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE,
ESP_IRQ_PRIORITY_1,
0,
up_timer_expire,
NULL);
/* Enable the timer 0 CPU interrupt. */
up_enable_irq(XTENSA_IRQ_TIMER0);
up_enable_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE +
ETS_INTERNAL_INTR_SOURCE_OFF);
}
/****************************************************************************
arch/xtensa/src/esp32/esp32_tim.c
+7 -15
View File
@@ -33,7 +33,7 @@
#include "hardware/esp32_tim.h"
#include "esp32_irq.h"
#include "espressif/esp_irq.h"
#include "esp32_tim.h"
@@ -530,8 +530,8 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler,
*/
up_disable_irq(tim->irq);
esp32_teardown_irq(tim->core, tim->periph, tim->cpuint);
irq_detach(tim->irq);
esp_teardown_irq(tim->periph, tim->cpuint);
tim->cpuint = -ENOMEM;
tim->core = -ENODEV;
}
@@ -551,8 +551,10 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler,
/* Set up to receive peripheral interrupts on the current CPU */
tim->core = this_cpu();
tim->cpuint = esp32_setup_irq(tim->core, tim->periph,
tim->priority, ESP32_CPUINT_LEVEL);
tim->cpuint = esp_setup_irq(tim->periph,
tim->priority,
ESP_IRQ_TRIGGER_LEVEL,
handler, arg);
if (tim->cpuint < 0)
{
tmrerr("ERROR: No CPU Interrupt available");
@@ -560,16 +562,6 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler,
goto errout;
}
/* Associate an IRQ Number (from the timer) to an ISR */
ret = irq_attach(tim->irq, handler, arg);
if (ret != OK)
{
esp32_teardown_irq(tim->core, tim->periph, tim->cpuint);
tmrerr("ERROR: Failed to associate an IRQ Number");
goto errout;
}
/* Enable the CPU Interrupt that is linked to the timer */
up_enable_irq(tim->irq);
arch/xtensa/src/esp32/esp32_tim_lowerhalf.c
+1 -1
View File
@@ -39,7 +39,7 @@
#include "hardware/esp32_soc.h"
#include "esp32_clockconfig.h"
#include "esp_clk.h"
#include "esp32_tim.h"
/****************************************************************************
arch/xtensa/src/esp32/esp32_timerisr.c
+9 -3
View File
@@ -35,6 +35,7 @@
#include "clock/clock.h"
#include "xtensa_counter.h"
#include "xtensa.h"
#include "esp_irq.h"
/****************************************************************************
* Private data
@@ -65,7 +66,7 @@ static uint32_t g_tick_divisor;
*
****************************************************************************/
static int esp32_timerisr(int irq, uint32_t *regs, void *arg)
static int esp32_timerisr(int irq, void *regs, void *arg)
{
uint32_t divisor;
uint32_t compare;
@@ -131,9 +132,14 @@ void up_timer_initialize(void)
/* Attach the timer interrupt */
irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr, NULL);
esp_setup_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE,
ESP_IRQ_PRIORITY_1,
0,
esp32_timerisr,
NULL);
/* Enable the timer 0 CPU interrupt. */
up_enable_irq(XTENSA_IRQ_TIMER0);
up_enable_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE +
ETS_INTERNAL_INTR_SOURCE_OFF);
}
arch/xtensa/src/esp32/esp32_touch.c
+170 -31
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_touch.h
+46
View File
@@ -26,6 +26,7 @@
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <stdint.h>
#include <stdbool.h>
@@ -207,6 +208,51 @@ void esp32_touchirqdisable(int irq);
# define esp32_touchirqdisable(irq)
#endif
/****************************************************************************
* Name: esp32_touchirqattach
*
* Description:
* Attach an interrupt handler to a specified touch pad IRQ.
*
* Input Parameters:
* irq - Touch pad IRQ number to attach the handler to
* handler - Interrupt handler function
* arg - Argument to pass to the handler
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_TOUCH_IRQ
int esp32_touchirqattach(int irq, xcpt_t handler, void *arg);
#else
# define esp32_touchirqattach(irq, handler, arg) -EINVAL
#endif
/****************************************************************************
* Name: esp32_touchirqdetach
*
* Description:
* Detach the interrupt handler for the specified touch pad IRQ and
* disable the interrupt.
*
* Input Parameters:
* irq - Touch pad IRQ number to detach.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_ESP32_TOUCH_IRQ
int esp32_touchirqdetach(int irq);
#else
# define esp32_touchirqdetach(irq) (-EINVAL)
#endif
/****************************************************************************
* Name: esp32_touchregisterreleasecb
*
arch/xtensa/src/esp32/esp32_touch_lowerhalf.h
+2 -2
View File
@@ -33,11 +33,11 @@
#include "xtensa.h"
#include "hardware/esp32_rtc_io.h"
#include "hardware/esp32_rtccntl.h"
#include "soc/rtc_cntl_reg.h"
#include "hardware/esp32_touch.h"
#include "hardware/esp32_sens.h"
#include "esp32_rt_timer.h"
#include "esp_hr_timer.h"
#include "esp32_rtc_gpio.h"
/****************************************************************************
arch/xtensa/src/esp32/esp32_twai.c
+13 -26
View File
@@ -41,10 +41,10 @@
#include "xtensa.h"
#include "esp32_gpio.h"
#include "esp_gpio.h"
#include "esp32_twai.h"
#include "esp32_irq.h"
#include "esp32_clockconfig.h"
#include "esp_irq.h"
#include "esp_clk.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_gpio_sigmap.h"
@@ -476,8 +476,11 @@ static int esp32twai_setup(struct can_dev_s *dev)
}
priv->cpu = this_cpu();
priv->cpuint = esp32_setup_irq(priv->cpu, priv->periph,
1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(priv->periph,
1,
ESP_IRQ_TRIGGER_LEVEL,
esp32twai_interrupt,
dev);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type. */
@@ -488,18 +491,6 @@ static int esp32twai_setup(struct can_dev_s *dev)
return ret;
}
ret = irq_attach(priv->irq, esp32twai_interrupt, dev);
if (ret != OK)
{
/* Failed to attach IRQ, so CPU interrupt must be freed. */
esp32_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
priv->cpuint = -ENOMEM;
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
/* Enable the CPU interrupt that is linked to the TWAI device. */
up_enable_irq(priv->irq);
@@ -538,13 +529,9 @@ static void esp32twai_shutdown(struct can_dev_s *dev)
up_disable_irq(priv->irq);
/* Dissociate the IRQ from the ISR */
irq_detach(priv->irq);
/* Free cpu interrupt that is attached to this peripheral */
esp32_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
esp_teardown_irq(priv->periph, priv->cpuint);
priv->cpuint = -ENOMEM;
}
}
@@ -1235,11 +1222,11 @@ struct can_dev_s *esp32_twaiinitialize(int port)
/* Configure CAN GPIO pins */
esp32_gpio_matrix_out(CONFIG_ESP32_TWAI0_TXPIN, TWAI_TX_IDX, 0, 0);
esp32_configgpio(CONFIG_ESP32_TWAI0_TXPIN, OUTPUT_FUNCTION_1);
esp_gpio_matrix_out(CONFIG_ESP32_TWAI0_TXPIN, TWAI_TX_IDX, 0, 0);
esp_configgpio(CONFIG_ESP32_TWAI0_TXPIN, OUTPUT_FUNCTION_1);
esp32_configgpio(CONFIG_ESP32_TWAI0_RXPIN, INPUT_FUNCTION_1);
esp32_gpio_matrix_in(CONFIG_ESP32_TWAI0_RXPIN, TWAI_RX_IDX, 0);
esp_configgpio(CONFIG_ESP32_TWAI0_RXPIN, INPUT_FUNCTION_1);
esp_gpio_matrix_in(CONFIG_ESP32_TWAI0_RXPIN, TWAI_RX_IDX, 0);
spin_unlock_irqrestore(&g_twai0priv.lock, flags);
}

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