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Documentation/sam4cmp-db: port README.txt to rst

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This commit is contained in:
Piyush Patle
2026-04-01 03:39:43 +05:30
committed by Matteo Golin
parent 4d970d4a70
commit c118b9c8a7
3 changed files with 27 additions and 30 deletions
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Documentation/platforms/arm/sam34/boards/sam4cmp-db/README.txt
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README
^^^^^^
README for NuttX port to the SAM4CMP-DB board.
http://www.atmel.com/tools/SAM4CMP-DB.aspx
The board is intended to test NuttX SMP features for dual Cortex-M4.
Settings
^^^^^^^^
1. Both CPUs are running at 92.160MHz with PLLB.
2. Serial console can be used via on-board USB-UART (115200/8/N/1)
3. Interrupt handlers such as timer and UART are handled on CPU0
4. Both CPUs share internal SRAM0 (128KB)
5. SRAM1 is used to boot CPU1.
6. Cache controllers are disabled because of no snooping features.
Status
^^^^^^
Currently SMP freature works on the board but is not stable.
1. "nsh> sleep 1 &" works without crash.
2. "nsh> smp " sometimes works but some assertions might happen.
3. "nsh> ostest " causes deadlocks during the test.
Documentation/platforms/arm/sam34/boards/sam4cmp-db/index.rst
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@@ -2,5 +2,27 @@
sam4cmp-db sam4cmp-db
========== ==========
.. include:: README.txt README for the NuttX port to the SAM4CMP-DB board.
:literal:
The `SAM4CMP-DB <http://www.atmel.com/tools/SAM4CMP-DB.aspx>`_ board is used
to exercise NuttX SMP support for dual Cortex-M4 systems.
Settings
========
1. Both CPUs run at 92.160 MHz using PLLB.
2. The serial console is available via the on-board USB-to-UART interface at
115200 8N1.
3. Interrupt handlers such as the timer and UART run on CPU0.
4. Both CPUs share internal SRAM0 (128 KB).
5. SRAM1 is used to boot CPU1.
6. Cache controllers are disabled because the device has no snooping support.
Status
======
The SMP feature works on the board, but it is not yet stable.
1. ``nsh> sleep 1 &`` works without crashing.
2. ``nsh> smp`` sometimes works, but assertions may occur.
3. ``nsh> ostest`` causes deadlocks during the test.
Documentation/platforms/arm/sam34/index.rst
+3 -3
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@@ -90,9 +90,9 @@ was contributed in part by Max Neklyudov.
to NuttX by Masayuki Ishikawa in NuttX-7.19. The SAM4CM is a dual-CPU to NuttX by Masayuki Ishikawa in NuttX-7.19. The SAM4CM is a dual-CPU
part and SMP was included for the ARMv7-M and SAM3/4 families. The part and SMP was included for the ARMv7-M and SAM3/4 families. The
SAM4CMP-DB board support includes an NSH configuration that operates in SAM4CMP-DB board support includes an NSH configuration that operates in
an SMP configuration. Refer to the NuttX board an SMP configuration. Refer to the
`README <https://github.com/apache/nuttx/blob/master/Documentation/platforms/arm/sam34/boards/sam4cmp-db/README.txt>`__ :doc:`board documentation <boards/sam4cmp-db/index>` for further
file for further information. information.
Microchip SAM4E Microchip SAM4E
--------------- ---------------