Add SPWM example to test STM32L4 PWM driver low level operations

Author: Alan Carvalho de Assis <acassis@gmail.com>

    Run nxstyle again .c file and fix error message

Author: Daniel P. Carvalho <danieloak@gmail.com>

    Add SPWM example to test STM32L4 PWM driver low level operations.

    Fix BUGs.

boards/arm/stm32l4/nucleo-l432kc/Kconfig

@@ -107,4 +107,38 @@ endchoice
 
 endmenu
 
+menuconfig NUCLEOL432KC_SPWM
+	bool "Sinusoidal PWM generator example"
+	default n
+
+if NUCLEOL432KC_SPWM
+
+choice
+	prompt "Sinusoidal PWM source"
+	default NUCLEOL432KC_SPWM_USE_TIM1
+
+config NUCLEOL432KC_SPWM_USE_TIM1
+	bool "Use TIM1 as PWM source"
+
+endchoice
+
+config NUCLEOL432KC_SPWM_PWM_FREQ
+	int "PWM frequency in Hz"
+	default 100000
+
+config NUCLEOL432KC_SPWM_SAMPLES
+	int "Sine samples"
+	default 100
+
+config NUCLEOL432KC_SPWM_FREQ
+	int "Waveform frequency in Hz"
+	default 60
+
+config NUCLEOL432KC_SPWM_PHASE_NUM
+	int "Number of phases"
+	default 1
+	range 1 4 if NUCLEOL432KC_SPWM_USE_TIM1
+
+endif
+
 endif # ARCH_BOARD_NUCLEO_L432KC

boards/arm/stm32l4/nucleo-l432kc/README.txt

@@ -535,3 +535,14 @@ Configurations
        Pin 33 PA10 USART1_TX    some RS-232 converters
        Pin 20 GND
        Pin 8  U5V
+
+  spwm
+  ----
+
+    Configures the sinusoidal PWM (SPWM) example which presents a simple use case
+    of the STM32L4 PWM lower-half driver without generic upper-half PWM logic.
+
+    It uses TIM1 to generate PWM and TIM6 to change waveform samples
+
+    At the moment, the waveform parameters are hardcoded, but it should be easy to
+    modify this example and make it more functional.

boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h

@@ -68,7 +68,8 @@
  * synced MSI.
  *
  *   System Clock source           : PLL (HSI)
- *   SYSCLK(Hz)                    : 80000000      Determined by PLL configuration
+ *   SYSCLK(Hz)                    : 80000000      Determined by PLL
+ *                                                 configuration
  *   HCLK(Hz)                      : 80000000     (STM32L4_RCC_CFGR_HPRE)
  *                                                (Max 80 MHz)
  *   AHB Prescaler                 : 1            (STM32L4_RCC_CFGR_HPRE)
@@ -233,9 +234,9 @@
 /* 'main' PLL config; we use this to generate our system clock via the R
  *  output.  We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
  *
- * XXX NOTE:  currently the main PLL is implicitly turned on and is implicitly
- * the system clock; this should be configurable since not all applications may
- * want things done this way.
+ * XXX NOTE:  currently the main PLL is implicitly turned on and is
+ * implicitly the system clock; this should be configurable since not all
+ * applications may want things done this way.
  */
 
 #define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(10)
@@ -495,6 +496,8 @@
 #define STM32L4_APB1_TIM2_CLKIN   (STM32L4_PCLK1_FREQUENCY)
 #define STM32L4_APB1_TIM6_CLKIN   (STM32L4_PCLK1_FREQUENCY)
 #define STM32L4_APB1_TIM7_CLKIN   (STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
 
 /* Configure the APB2 prescaler */
 
@@ -507,8 +510,8 @@
 
 #endif
 
-/* The timer clock frequencies are automatically defined by hardware.
- * If the APB prescaler equals 1, the timer clock frequencies are set to the same
+/* The timer clock frequencies are automatically defined by hardware. If the
+ * APB prescaler equals 1, the timer clock frequencies are set to the same
  * frequency as that of the APB domain. Otherwise they are set to twice.
  * Note: TIM1,15,16 are on APB2, others on APB1
  */

boards/arm/stm32l4/nucleo-l432kc/src/Makefile

@@ -92,4 +92,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
 CSRCS += stm32_appinit.c
 endif
 
+ifeq ($(CONFIG_NUCLEOL432KC_SPWM),y)
+CSRCS += stm32_spwm.c
+endif
+
 include $(TOPDIR)/boards/Board.mk