mirror of
https://github.com/apache/nuttx.git
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SAMA5 NAND: More stuff
This commit is contained in:
Gregory Nutt
+100
-68
@@ -3042,27 +3042,35 @@ config SAMA5_EBICS0_NAND
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endchoice # CS0 Memory Type
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if SAMA5_EBICS0_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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config SAMA5_EBICS0_HWECC
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bool "NAND H/W ECC support"
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default n
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choice
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prompt "NAND ECC type"
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default SAMA5_EBICS0_ECCNONE
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depends on SAMA5_EBICS0_NAND
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config SAMA5_EBICS0_ECCNONE
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bool "No ECC"
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---help---
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Only raw transfers to/from NAND are supported
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config SAMA5_EBICS0_SWECC
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bool "Software ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_SWECC
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---help---
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ECC is performed by higher level software logic
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config SAMA5_EBICS0_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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---help---
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Enable hardware assisted support for ECC calculations
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if SAMA5_EBICS0_HWECC
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choice
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prompt "H/W ECC method"
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default SAMA5_EBICS0_PMECC
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config SAMA5_EBICS0_CHIPECC
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bool "Embedded chip ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_EMBEDDEDECC
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---help---
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Some NAND devices have internal, embedded ECC function.
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config SAMA5_EBICS0_PMECC
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bool "PMECC"
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config SAMA5_EBICS0_HSIAO
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bool "HSIAO ECC"
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endchoice # H/W ECC method
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endif # SAMA5_EBICS0_HWECC
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endif # SAMA5_EBICS0_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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endchoice # NAND ECC type
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endif # SAMA5_EBICS0
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config SAMA5_EBICS1
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@@ -3115,27 +3123,35 @@ config SAMA5_EBICS1_NAND
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endchoice # CS1 Memory Type
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if SAMA5_EBICS1_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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config SAMA5_EBICS1_HWECC
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bool "NAND H/W ECC support"
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default n
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choice
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prompt "NAND ECC type"
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default SAMA5_EBICS1_ECCNONE
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depends on SAMA5_EBICS1_NAND
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config SAMA5_EBICS1_ECCNONE
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bool "No ECC"
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---help---
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Only raw transfers to/from NAND are supported
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config SAMA5_EBICS1_SWECC
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bool "Software ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_SWECC
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---help---
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ECC is performed by higher level software logic
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config SAMA5_EBICS1_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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---help---
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Enable hardware assisted support for ECC calculations
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if SAMA5_EBICS1_HWECC
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choice
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prompt "H/W ECC method"
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default SAMA5_EBICS1_PMECC
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config SAMA5_EBICS1_CHIPECC
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bool "Embedded chip ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_EMBEDDEDECC
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---help---
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Some NAND devices have internal, embedded ECC function.
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config SAMA5_EBICS1_PMECC
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bool "PMECC"
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config SAMA5_EBICS1_HSIAO
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bool "HSIAO ECC"
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endchoice # H/W ECC method
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endif # SAMA5_EBICS1_HWECC
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endif # SAMA5_EBICS1_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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endchoice # NAND ECC type
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endif # SAMA5_EBICS1
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config SAMA5_EBICS2
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@@ -3188,27 +3204,35 @@ config SAMA5_EBICS2_NAND
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endchoice # CS2 Memory Type
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if SAMA5_EBICS2_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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config SAMA5_EBICS2_HWECC
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bool "NAND H/W ECC support"
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default n
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choice
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prompt "NAND ECC type"
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default SAMA5_EBICS2_ECCNONE
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depends on SAMA5_EBICS2_NAND
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config SAMA5_EBICS2_ECCNONE
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bool "No ECC"
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---help---
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Only raw transfers to/from NAND are supported
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config SAMA5_EBICS2_SWECC
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bool "Software ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_SWECC
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---help---
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ECC is performed by higher level software logic
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config SAMA5_EBICS2_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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---help---
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Enable hardware assisted support for ECC calculations
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if SAMA5_EBICS2_HWECC
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choice
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prompt "H/W ECC method"
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default SAMA5_EBICS2_PMECC
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config SAMA5_EBICS2_CHIPECC
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bool "Embedded chip ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_EMBEDDEDECC
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---help---
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Some NAND devices have internal, embedded ECC function.
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config SAMA5_EBICS2_PMECC
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bool "PMECC"
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config SAMA5_EBICS2_HSIAO
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bool "HSIAO ECC"
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endchoice # H/W ECC method
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endif # SAMA5_EBICS2_HWECC
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endif # SAMA5_EBICS2_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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endchoice # NAND ECC type
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endif # SAMA5_EBICS2
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config SAMA5_EBICS3
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@@ -3261,27 +3285,35 @@ config SAMA5_EBICS3_NAND
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endchoice # CS3 Memory Type
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if SAMA5_EBICS3_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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config SAMA5_EBICS3_HWECC
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bool "NAND H/W ECC support"
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default n
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choice
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prompt "NAND ECC type"
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default SAMA5_EBICS3_ECCNONE
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depends on SAMA5_EBICS3_NAND
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config SAMA5_EBICS3_ECCNONE
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bool "No ECC"
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---help---
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Only raw transfers to/from NAND are supported
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config SAMA5_EBICS3_SWECC
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bool "Software ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_SWECC
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---help---
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ECC is performed by higher level software logic
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config SAMA5_EBICS3_PMECC
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bool "NAND H/W PMECC Support"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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---help---
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Enable hardware assisted support for ECC calculations
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if SAMA5_EBICS3_HWECC
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choice
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prompt "H/W ECC method"
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default SAMA5_EBICS3_PMECC
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config SAMA5_EBICS3_CHIPECC
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bool "Embedded chip ECC"
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depends on MTD_NAND_BLOCKCHECK && MTD_NAND_EMBEDDEDECC
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---help---
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Some NAND devices have internal, embedded ECC function.
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config SAMA5_EBICS3_PMECC
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bool "PMECC"
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config SAMA5_EBICS3_HSIAO
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bool "HSIAO ECC"
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endchoice # H/W ECC method
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endif # SAMA5_EBICS3_HWECC
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endif # SAMA5_EBICS3_NAND && MTD_NAND_BLOCKCHECK && MTD_NAND_HWECC
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endchoice # NAND ECC type
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endif # SAMA5_EBICS3
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if SAMA5_EBICS0_NAND || SAMA5_EBICS1_NAND || SAMA5_EBICS2_NAND || SAMA5_EBICS3_NAND
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@@ -228,16 +228,16 @@ endif
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endif
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ifeq ($(CONFIG_SAMA5_EBICS0_NAND),y)
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CHIP_CSRCS += sam_nand.c
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CHIP_CSRCS += sam_nand.c sam_pmecc.c
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else
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ifeq ($(CONFIG_SAMA5_EBICS1_NAND),y)
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CHIP_CSRCS += sam_nand.c
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CHIP_CSRCS += sam_nand.c sam_pmecc.c
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else
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ifeq ($(CONFIG_SAMA5_EBICS2_NAND),y)
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CHIP_CSRCS += sam_nand.c
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CHIP_CSRCS += sam_nand.c sam_pmecc.c
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else
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ifeq ($(CONFIG_SAMA5_EBICS3_NAND),y)
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CHIP_CSRCS += sam_nand.c
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CHIP_CSRCS += sam_nand.c sam_pmecc.c
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endif
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endif
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endif
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+192
-140
File diff suppressed because it is too large
Load Diff
+113
-38
@@ -41,6 +41,7 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/mtd/nand_config.h>
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#include <stdint.h>
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#include <stdbool.h>
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@@ -49,6 +50,7 @@
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#include <nuttx/mtd/nand_raw.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "chip/sam_hsmc.h"
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@@ -58,39 +60,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Block checking and H/W ECC support must be enabled for HSIAO ECC */
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#if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(MTD_NAND_HWECC)
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# undef CONFIG_SAMA5_EBICS0_HSIAO
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# undef CONFIG_SAMA5_EBICS1_HSIAO
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# undef CONFIG_SAMA5_EBICS2_HSIAO
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# undef CONFIG_SAMA5_EBICS3_HSIAO
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#endif
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/* Disable HSIAO support for any banks not enabled or configured for NAND */
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#if !defined(SAMA5_EBICS0) || !defined(SAMA5_EBICS0_NAND)
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# undef CONFIG_SAMA5_EBICS0_HSIAO
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#endif
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#if !defined(SAMA5_EBICS1) || !defined(SAMA5_EBICS1_NAND)
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# undef CONFIG_SAMA5_EBICS1_HSIAO
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#endif
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#if !defined(SAMA5_EBICS2) || !defined(SAMA5_EBICS2_NAND)
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# undef CONFIG_SAMA5_EBICS2_HSIAO
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#endif
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#if !defined(SAMA5_EBICS3) || !defined(SAMA5_EBICS3_NAND)
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# undef CONFIG_SAMA5_EBICS3_HSIAO
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#endif
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#undef NAND_HAVE_HSIAO
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#if defined(CONFIG_SAMA5_EBICS0_HSIAO) || defined(CONFIG_SAMA5_EBICS1_HSIAO) || \
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defined(CONFIG_SAMA5_EBICS2_HSIAO) || defined(CONFIG_SAMA5_EBICS3_HSIAO)
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# define NAND_HAVE_HSIAO
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#endif
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#ifndef CONFIG_SAMA5_DMAC1
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# warning CONFIG_SAMA5_DMAC1 should be enabled for DMA transfers
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#endif
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@@ -100,12 +69,120 @@
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*
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* NANDECC_CHIPECC ECC is performed internal to chip
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* NANDECC_PMECC Programmable Multibit Error Correcting Code (PMECC)
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* NANDECC_HSIAO HSIAO ECC
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*/
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#define NANDECC_CHIPECC (NANDECC_HWECC + 0)
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#define NANDECC_PMECC (NANDECC_HWECC + 1)
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#define NANDECC_HSIAO (NANDECC_HWECC + 2)
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/* Per NAND bank ECC selections */
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#if defined(CONFIG_SAMA5_EBICS0_NAND)
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# if defined(CONFIG_SAMA5_EBICS0_ECCNONE)
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# define SAMA5_EBICS0_ECCTYPE NANDECC_NONE
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# elif defined(CONFIG_SAMA5_EBICS0_SWECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_SWECC)
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# error CONFIG_SAMA5_EBICS0_SWECC is an invalid selection
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# endif
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# define SAMA5_EBICS0_ECCTYPE NANDECC_SWECC
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# elif defined(CONFIG_SAMA5_EBICS0_PMECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_HWECC)
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# error CONFIG_SAMA5_EBICS0_PMECC is an invalid selection
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# endif
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# define SAMA5_EBICS0_ECCTYPE NANDECC_PMECC
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# elif defined(CONFIG_SAMA5_EBICS0_CHIPECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_EMBEDDEDECC)
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# error CONFIG_SAMA5_EBICS0_CHIPECC is an invalid selection
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# endif
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# define SAMA5_EBICS0_ECCTYPE NANDECC_CHIPECC
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# else
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# error "No ECC type specified for CS0"
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# endif
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#endif /* CONFIG_SAMA5_EBICS0_NAND */
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#if defined(CONFIG_SAMA5_EBICS1_NAND)
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# if defined(CONFIG_SAMA5_EBICS1_ECCNONE)
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# define SAMA5_EBICS1_ECCTYPE NANDECC_NONE
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# elif defined(CONFIG_SAMA5_EBICS1_SWECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_SWECC)
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# error CONFIG_SAMA5_EBICS1_SWECC is an invalid selection
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# endif
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# define SAMA5_EBICS1_ECCTYPE NANDECC_SWECC
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# elif defined(CONFIG_SAMA5_EBICS1_PMECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_HWECC)
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# error CONFIG_SAMA5_EBICS1_PMECC is an invalid selection
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# endif
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# define SAMA5_EBICS1_ECCTYPE NANDECC_PMECC
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# elif defined(CONFIG_SAMA5_EBICS1_CHIPECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_EMBEDDEDECC)
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# error CONFIG_SAMA5_EBICS1_CHIPECC is an invalid selection
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# endif
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# define SAMA5_EBICS1_ECCTYPE NANDECC_CHIPECC
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# else
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# error "No ECC type specified for CS1"
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# endif
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#endif /* CONFIG_SAMA5_EBICS1_NAND */
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#if defined(CONFIG_SAMA5_EBICS2_NAND)
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# if defined(CONFIG_SAMA5_EBICS2_ECCNONE)
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# define SAMA5_EBICS2_ECCTYPE NANDECC_NONE
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# elif defined(CONFIG_SAMA5_EBICS2_SWECC
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_SWECC)
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# error CONFIG_SAMA5_EBICS2_SWECC is an invalid selection
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# endif
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# define SAMA5_EBICS2_ECCTYPE NANDECC_SWECC
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# elif defined(CONFIG_SAMA5_EBICS2_PMECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_HWECC)
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# error CONFIG_SAMA5_EBICS2_PMECC is an invalid selection
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# endif
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# define SAMA5_EBICS2_ECCTYPE NANDECC_PMECC
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# elif defined(CONFIG_SAMA5_EBICS2_CHIPECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_EMBEDDEDECC)
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# error CONFIG_SAMA5_EBICS2_CHIPECC is an invalid selection
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# endif
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# define SAMA5_EBICS2_ECCTYPE NANDECC_CHIPECC
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# else
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# error "No ECC type specified for CS2"
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# endif
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#endif /* CONFIG_SAMA5_EBICS2_NAND */
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#if defined(CONFIG_SAMA5_EBICS3_NAND)
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# if defined(CONFIG_SAMA5_EBICS3_ECCNONE)
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# define SAMA5_EBICS3_ECCTYPE NANDECC_NONE
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# elif defined(CONFIG_SAMA5_EBICS3_SWECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_SWECC)
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# error CONFIG_SAMA5_EBICS3_SWECC is an invalid selection
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# endif
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# define SAMA5_EBICS3_ECCTYPE NANDECC_SWECC
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# elif defined(CONFIG_SAMA5_EBICS3_PMECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_HWECC)
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# error CONFIG_SAMA5_EBICS3_PMECC is an invalid selection
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# endif
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# define SAMA5_EBICS3_ECCTYPE NANDECC_PMECC
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# elif defined(CONFIG_SAMA5_EBICS3_CHIPECC)
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# if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_EMBEDDEDECC)
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# error CONFIG_SAMA5_EBICS3_CHIPECC is an invalid selection
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# endif
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# define SAMA5_EBICS3_ECCTYPE NANDECC_CHIPECC
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# else
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# error "No ECC type specified for CS3"
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# endif
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#endif /* CONFIG_SAMA5_EBICS3_NAND */
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/****************************************************************************
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* Public Types
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@@ -122,9 +199,7 @@ struct sam_nandcs_s
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/* Static configuration */
|
||||
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uint8_t cs :2; /* Chip select number (0..3) */
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||||
uint8_t nfcsram :1; /* True: Use NFC SRAM */
|
||||
uint8_t dmaxfr :1; /* True: Use DMA transfers */
|
||||
uint8_t cs; /* Chip select number (0..3) */
|
||||
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||||
/* Dynamic state */
|
||||
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||||
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||||
@@ -0,0 +1,274 @@
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/****************************************************************************
|
||||
* arch/arm/src/sama5/sam_pmecc.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
* SAMA5D3 Series Data Sheet
|
||||
* Atmel NoOS sample code.
|
||||
*
|
||||
* The Atmel sample code has a BSD compatibile license that requires this
|
||||
* copyright notice:
|
||||
*
|
||||
* Copyright (c) 2012, Atmel Corporation
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the names NuttX nor Atmel nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/mtd/nand_config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include "sam_pmecc.h"
|
||||
#include "sam_nand.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define BCH_ERR2 0 /* 2 errors */
|
||||
#define BCH_ERR4 1 /* 4 errors */
|
||||
#define BCH_ERR8 2 /* 8 errors */
|
||||
#define BCH_ERR12 3 /* 12 errors */
|
||||
#define BCH_ERR24 4 /* 24 errors */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/* PMECC state data */
|
||||
|
||||
struct sam_pmecc_s
|
||||
{
|
||||
uint8_t nsectors : 4; /* Number of sectors in data */
|
||||
uint8_t bcherr : 3; /* BCH_ERR correctability code */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
/* PMECC state data */
|
||||
|
||||
static struct sam_pmecc_s g_pmecc;
|
||||
|
||||
/* Maps BCH_ERR correctability register value to number of errors per sector */
|
||||
|
||||
static const uint8_t g_correctability[5] = {2, 4, 8, 12, 24};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pmecc_bcherr512
|
||||
*
|
||||
* Description:
|
||||
* Get the correctabity that could be achieved using a 512 byte sector
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pmecc_bcherr512(uint8_t nsectors, uint16_t sparesize)
|
||||
{
|
||||
/* 39-bytes per 512 byte sector are required correctability of 24 errors */
|
||||
|
||||
if (sparesize <= 39 * ((unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR24;
|
||||
}
|
||||
|
||||
/* 20-bytes per 512 byte sector are required correctability of 12 errors */
|
||||
|
||||
else if (sparesize <= (20 * (unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR12;
|
||||
}
|
||||
|
||||
/* 13-bytes per 512 byte sector are required correctability of 8 errors */
|
||||
|
||||
else if (sparesize <= (13 * (unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR8;
|
||||
}
|
||||
|
||||
/* 7-bytes per 512 byte sector are required correctability of 4 errors */
|
||||
|
||||
else if (sparesize <= (7 *(unsigned int) nsectors))
|
||||
{
|
||||
return BCH_ERR4;
|
||||
}
|
||||
|
||||
/* 4-bytes per 512 byte sector are required correctability of 2 errors */
|
||||
|
||||
else if (sparesize <= (4 *(unsigned int) nsectors))
|
||||
{
|
||||
return BCH_ERR2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pmecc_bcherr512
|
||||
*
|
||||
* Description:
|
||||
* Get the correctabity that could be achieved using a 512 byte sector
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pmecc_bcherr1k(uint8_t nsectors, uint16_t sparesize)
|
||||
{
|
||||
/* 42-bytes per 1024 byte sector are required correctability of 24 errors */
|
||||
|
||||
if (sparesize <= 42 * ((unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR24;
|
||||
}
|
||||
|
||||
/* 21-bytes per 1024 byte sector are required correctability of 12 errors */
|
||||
|
||||
else if (sparesize <= (20 * (unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR12;
|
||||
}
|
||||
|
||||
/* 14-bytes per 1024 byte sector are required correctability of 8 errors */
|
||||
|
||||
else if (sparesize <= (13 * (unsigned int)nsectors))
|
||||
{
|
||||
return BCH_ERR8;
|
||||
}
|
||||
|
||||
/* 7-bytes per 1024 byte sector are required correctability of 4 errors */
|
||||
|
||||
else if (sparesize <= (7 *(unsigned int) nsectors))
|
||||
{
|
||||
return BCH_ERR4;
|
||||
}
|
||||
|
||||
/* 4-bytes per 1024 byte sector are required correctability of 2 errors */
|
||||
|
||||
else if (sparesize <= (4 *(unsigned int) nsectors))
|
||||
{
|
||||
return BCH_ERR2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pmecc_pagelayout
|
||||
*
|
||||
* Description:
|
||||
* Given the data size and the spare size, determine the optimal sector
|
||||
* size and correctability.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void pmecc_pagelayout(uint16_t datasize, uint16_t sparesize,
|
||||
uint16_t offset)
|
||||
{
|
||||
uint16_t correctability512;
|
||||
uint16_t correctability1K;
|
||||
uint8_t nsectors512;
|
||||
uint8_t nsectors1k;
|
||||
uint8_t bcherr512;
|
||||
uint8_t bcherr1k;
|
||||
|
||||
/* Decrease the spare size by the offset */
|
||||
|
||||
sparesize -= offset;
|
||||
|
||||
/* Try for 512 byte sectors */
|
||||
|
||||
DEBUGASSERT((datasize & 0xfffffe00) == 0 && datasize >= 512);
|
||||
|
||||
nsectors512 = (datasize >> 9);
|
||||
bcherr512 = pmecc_bcherr512(nsectors512, sparesize);
|
||||
|
||||
/* Try for 1024 byte sectors */
|
||||
|
||||
if ((datasize & 0xfffffc00) == 0)
|
||||
{
|
||||
nsectors1k = (datasize >> 9);
|
||||
bcherr1k = pmecc_bcherr1k(nsectors1k, sparesize);
|
||||
}
|
||||
else
|
||||
{
|
||||
nsectors1k = 0;
|
||||
bcherr1k = 0;
|
||||
}
|
||||
|
||||
/* Now pick the best (most likely 1024) */
|
||||
|
||||
DEBUGASSERT(bcherr512 > 0 || bcherr1k > 0);
|
||||
if (bcherr1k == 0)
|
||||
{
|
||||
g_pmecc.nsectors = nsectors512;
|
||||
g_pmecc.bcherr = bcherr512;
|
||||
}
|
||||
else
|
||||
{
|
||||
correctability512 = nsectors512 * g_correctability[bcherr512];
|
||||
correctability1K = nsectors1k * g_correctability[bcherr1k];
|
||||
if (correctability512 >= correctability1K)
|
||||
{
|
||||
g_pmecc.nsectors = nsectors512;
|
||||
g_pmecc.bcherr = bcherr512;
|
||||
}
|
||||
else
|
||||
{
|
||||
g_pmecc.nsectors = nsectors1k;
|
||||
g_pmecc.bcherr = bcherr1k;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pmecc_configure
|
||||
*
|
||||
* Description:
|
||||
* Configure the PMECC for use by this CS
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@@ -55,7 +55,7 @@
|
||||
/* Configuration ************************************************************/
|
||||
/* Block checking and H/W ECC support must be enabled for PMECC */
|
||||
|
||||
#if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(MTD_NAND_HWECC)
|
||||
#if !defined(CONFIG_MTD_NAND_BLOCKCHECK) || !defined(CONFIG_MTD_NAND_HWECC)
|
||||
# undef CONFIG_SAMA5_EBICS0_PMECC
|
||||
# undef CONFIG_SAMA5_EBICS1_PMECC
|
||||
# undef CONFIG_SAMA5_EBICS2_PMECC
|
||||
@@ -64,19 +64,19 @@
|
||||
|
||||
/* Disable PMECC support for any banks not enabled or configured for NAND */
|
||||
|
||||
#if !defined(SAMA5_EBICS0) || !defined(SAMA5_EBICS0_NAND)
|
||||
#if !defined(CONFIG_SAMA5_EBICS0) || !defined(CONFIG_SAMA5_EBICS0_NAND)
|
||||
# undef CONFIG_SAMA5_EBICS0_PMECC
|
||||
#endif
|
||||
|
||||
#if !defined(SAMA5_EBICS1) || !defined(SAMA5_EBICS1_NAND)
|
||||
#if !defined(CONFIG_SAMA5_EBICS1) || !defined(CONFIG_SAMA5_EBICS1_NAND)
|
||||
# undef CONFIG_SAMA5_EBICS1_PMECC
|
||||
#endif
|
||||
|
||||
#if !defined(SAMA5_EBICS2) || !defined(SAMA5_EBICS2_NAND)
|
||||
#if !defined(CONFIG_SAMA5_EBICS2) || !defined(CONFIG_SAMA5_EBICS2_NAND)
|
||||
# undef CONFIG_SAMA5_EBICS2_PMECC
|
||||
#endif
|
||||
|
||||
#if !defined(SAMA5_EBICS3) || !defined(SAMA5_EBICS3_NAND)
|
||||
#if !defined(CONFIG_SAMA5_EBICS3) || !defined(CONFIG_SAMA5_EBICS3_NAND)
|
||||
# undef CONFIG_SAMA5_EBICS3_PMECC
|
||||
#endif
|
||||
|
||||
@@ -88,40 +88,40 @@
|
||||
#ifdef CONFIG_SAMA5_EBICS0_PMECC
|
||||
# undef NAND_HAVE_PMECC
|
||||
# define NAND_HAVE_PMECC 1
|
||||
# define NAND_HAVE_EBIS0_PMECC 1
|
||||
# define NAND_HAVE_EBICS0_PMECC 1
|
||||
#else
|
||||
# define NAND_HAVE_EBIS0_PMECC 0
|
||||
# define NAND_HAVE_EBICS0_PMECC 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS1_PMECC
|
||||
# undef NAND_HAVE_PMECC
|
||||
# define NAND_HAVE_PMECC 1
|
||||
# define NAND_HAVE_EBIS1_PMECC 1
|
||||
# define NAND_HAVE_EBICS1_PMECC 1
|
||||
#else
|
||||
# define NAND_HAVE_EBIS1_PMECC 0
|
||||
# define NAND_HAVE_EBICS1_PMECC 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS2_PMECC
|
||||
# undef NAND_HAVE_PMECC
|
||||
# define NAND_HAVE_PMECC 1
|
||||
# define NAND_HAVE_EBIS2_PMECC 1
|
||||
# define NAND_HAVE_EBICS2_PMECC 1
|
||||
#else
|
||||
# define NAND_HAVE_EBIS2_PMECC 0
|
||||
# define NAND_HAVE_EBICS2_PMECC 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_EBICS3_PMECC
|
||||
# undef NAND_HAVE_PMECC
|
||||
# define NAND_HAVE_PMECC 1
|
||||
# define NAND_HAVE_EBIS3_PMECC 1
|
||||
# define NAND_HAVE_EBICS3_PMECC 1
|
||||
#else
|
||||
# define NAND_HAVE_EBIS3_PMECC 0
|
||||
# define NAND_HAVE_EBICS3_PMECC 0
|
||||
#endif
|
||||
|
||||
/* Count the number of banks using PMECC */
|
||||
|
||||
#define NAND_NPMECC_BANKS \
|
||||
(NAND_HAVE_EBIS0_PMECC + NAND_HAVE_EBIS1_PMECC + \
|
||||
NAND_HAVE_EBIS2_PMECC + NAND_HAVE_EBIS3_PMECC
|
||||
(NAND_HAVE_EBICS0_PMECC + NAND_HAVE_EBICS1_PMECC + \
|
||||
NAND_HAVE_EBICS2_PMECC + NAND_HAVE_EBICS3_PMECC)
|
||||
|
||||
/* Compile this logic only if there is at least one CS configure for NAND
|
||||
* and with PMECC support enabled.
|
||||
|
||||
@@ -249,6 +249,7 @@ struct nand_raw_s
|
||||
uintptr_t cmdaddr; /* NAND command address base */
|
||||
uintptr_t addraddr; /* NAND address address base */
|
||||
uintptr_t dataaddr; /* NAND data address */
|
||||
uint8_t ecctype; /* See NANDECC_* definitions */
|
||||
|
||||
/* NAND operations */
|
||||
|
||||
@@ -268,12 +269,10 @@ struct nand_raw_s
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_NAND_BLOCKCHECK
|
||||
/* ECC */
|
||||
/* ECC working buffers*/
|
||||
|
||||
uint8_t ecctype; /* See enum nand_ecc_e */
|
||||
uint8_t spare[CONFIG_MTD_NAND_MAXPAGESPARESIZE];
|
||||
uint8_t ecc[CONFIG_MTD_NAND_MAXSPAREECCBYTES];
|
||||
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user