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arch/arm/stm32n6: Add STM32N6 chip support.

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Introduce minimal chip support for the STMicro STM32N6 family
(Cortex-M55, ARMv8.1-M with TrustZone and FPU), sufficient to bring
up an NSH console over USART1.

Scope (deliberately minimal first drop):

  - Chip selector ARCH_CHIP_STM32N6 wired into arch/arm/Kconfig and
    chip-name mapping ("stm32n6").
  - Sub-Kconfig under arch/arm/src/stm32n6 with the STM32N657X0 chip
    selector and a single user-selectable USART (USART1).
  - Boot path: stm32_start with a naked dispatcher that clears the
    boot-ROM MSPLIM/PSPLIM stack limits before any compiler-emitted
    prologue, then runs vector relocation and SRAM-only heap init.
    The chip runs entirely in the Secure state; SAU is left in its
    reset configuration.
  - PLL1-based clock tree fed from HSI64 targeting 200 MHz CPU, with
    USART1 kernel-clock routed to HSI for a predictable BRR that is
    independent of any later clock change.
  - Low-level USART driver with full serial framework support.
    stm32_serial.c is adapted from arch/arm/src/stm32h5/stm32_serial.c
    (sibling ARMv8-M Mainline port with the same USART IP), stripped
    of DMA-RX, LPUART, the per-USART2..5 plumbing, RS-485 driver-enable,
    TIOCSINVERT/SWAP and HALFDUPLEX paths.
  - SysTick system timer.
  - GPIO, PWR and RCC helpers.

TrustZone, MPU, I/D-cache and Helium (MVE) are left disabled to
minimise bring-up surface; these will be added in follow-up patches
alongside the drivers that need them.

Signed-off-by: ImBonkers <samuelnlinden@pm.me>
This commit is contained in:
ImBonkers
2026-05-18 14:50:29 -03:00
committed by Alan C. Assis
parent 4df80e1928
commit be30590504
33 changed files with 6656 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/Kconfig
+17
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@@ -582,6 +582,19 @@ config ARCH_CHIP_STM32H5
---help---
STMicro STM32 H5 architectures (ARM Cortex-M33).
config ARCH_CHIP_STM32N6
bool "STMicro STM32 N6"
select ARCH_CORTEXM55
select ARCH_HAVE_FPU
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_TRUSTZONE
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
---help---
STMicro STM32N6 architectures (ARM Cortex-M55).
config ARCH_CHIP_STM32L5
bool "STMicro STM32 L5"
select ARCH_CORTEXM33
@@ -1194,6 +1207,7 @@ config ARCH_CHIP
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
default "stm32h5" if ARCH_CHIP_STM32H5
default "stm32n6" if ARCH_CHIP_STM32N6
default "stm32l5" if ARCH_CHIP_STM32L5
default "stm32u5" if ARCH_CHIP_STM32U5
default "stm32wb" if ARCH_CHIP_STM32WB
@@ -1704,6 +1718,9 @@ endif
if ARCH_CHIP_STM32H5
source "arch/arm/src/stm32h5/Kconfig"
endif
if ARCH_CHIP_STM32N6
source "arch/arm/src/stm32n6/Kconfig"
endif
if ARCH_CHIP_STM32L5
source "arch/arm/src/stm32l5/Kconfig"
endif
arch/arm/include/stm32n6/chip.h
+69
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@@ -0,0 +1,69 @@
/****************************************************************************
* arch/arm/include/stm32n6/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32N6_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* Memory sizes - STM32N6 has no internal flash. Code runs from the
* on-chip AXI SRAM (loaded by the debugger in DEV mode, or by an FSBL
* from external XSPI flash in normal boot).
*
* AXI SRAM layout (from CMSIS stm32n657xx.h):
* AXISRAM1: 0x34000000 1 MB
* AXISRAM2: 0x34100000 1 MB
* AXISRAM3: 0x34200000 448 KB
* AXISRAM4: 0x34270000 448 KB
* AXISRAM5: 0x342E0000 448 KB
* AXISRAM6: 0x34350000 448 KB
* CACHEAXIRAM: 0x343C0000 256 KB
* -------------------------------------------
* Total: 4 MB (end = 0x34400000)
*
* VENCRAM (128 KB at 0x34400000) is excluded -- reserved for video encoder.
* Each bank requires its RCC MEMENR clock enable bit to be set.
*/
#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */
#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */
#define STM32N6_NUSART (1) /* USART1 */
/* NVIC priority levels *****************************************************/
/* 16 Programmable interrupt levels (4-bit priority) */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32N6_CHIP_H */
arch/arm/include/stm32n6/irq.h
+97
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@@ -0,0 +1,97 @@
/****************************************************************************
* arch/arm/include/stm32n6/irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32N6_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32N6_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are
* chip-specific
*/
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#include <arch/stm32n6/stm32n6xx_irq.h>
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32N6_IRQ_H */
arch/arm/include/stm32n6/stm32n6xx_irq.h
+239
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arch/arm/src/stm32n6/CMakeLists.txt
+52
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@@ -0,0 +1,52 @@
# ##############################################################################
# arch/arm/src/stm32n6/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS)
# Required STM32N6 files
list(
APPEND
SRCS
stm32_gpio.c
stm32_irq.c
stm32_lowputc.c
stm32_rcc.c
stm32_start.c
stm32_pwr.c
stm32_timerisr.c)
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle.c)
endif()
if(CONFIG_STM32N6_USART)
list(APPEND SRCS stm32_serial.c)
endif()
# Chip-specific RCC
if(CONFIG_STM32N6_STM32N6XXXX)
list(APPEND SRCS stm32n6xx_rcc.c)
endif()
target_sources(arch PRIVATE ${SRCS})
arch/arm/src/stm32n6/Kconfig
+109
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@@ -0,0 +1,109 @@
# arch/arm/src/stm32n6/Kconfig
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
if ARCH_CHIP_STM32N6
comment "STM32N6 Configuration Options"
config STM32N6_STM32N6XXXX
bool
default y
choice
prompt "STM32 N6 Chip Selection"
default ARCH_CHIP_STM32N657X0
depends on ARCH_CHIP_STM32N6
config ARCH_CHIP_STM32N657X0
bool "STM32N657X0"
select STM32N6_STM32N6XXXX
endchoice
menu "STM32N6 Peripheral Selection"
config STM32N6_USART1
bool "USART1"
default n
select STM32N6_USART
select USART1_SERIALDRIVER
select STM32N6_USART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config STM32N6_USART1_SERIALDRIVER
bool
default n
config STM32N6_USART
bool
if STM32N6_USART
config STM32N6_SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
depends on STM32N6_USART1
default n
---help---
NuttX per default reorders the serial ports (/dev/ttySx) so that the
console is always on /dev/ttyS0. If more than one UART is in use this
can, however, have the side-effect that all port mappings
(hardware USART1 -> /dev/ttyS0) change if the console is moved to
another UART. This option disables that reordering so port names
stay stable when the console is moved.
config STM32N6_FLOWCONTROL_BROKEN
bool "Use Software UART RTS flow control"
default n
---help---
Enable this option to use software RTS flow control rather than
the hardware RTS line. Useful in cases where the silicon RTS
behaviour does not match the application's needs.
config STM32N6_SERIALBRK_BSDCOMPAT
bool "Use GPIO to send Break"
default n
---help---
Enable this option to send break by reconfiguring TX as a GPIO
held low for the requested duration, matching BSD-compatible
semantics.
config STM32N6_PM_SERIAL_ACTIVITY
int "PM serial activity"
default 10
---help---
PM activity reported to power management logic on every serial
interrupt.
endif # STM32N6_USART
if USART1_SERIALDRIVER
config USART1_UNCONFIG_RX_ON_CLOSE
bool "Unconfigure USART1 RX pin on close"
default n
config USART1_UNCONFIG_TX_ON_CLOSE
bool "Unconfigure USART1 TX pin on close"
default n
endif # USART1_SERIALDRIVER
endmenu
endif # ARCH_CHIP_STM32N6
arch/arm/src/stm32n6/Make.defs
+47
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@@ -0,0 +1,47 @@
##############################################################################
# arch/arm/src/stm32n6/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
# The start-up, "head", file. Only common vectors are supported so there
# isn't one.
HEAD_ASRC =
# Common ARM and Cortex-M55 files (ARMv8-M base)
include armv8-m/Make.defs
# Required STM32N6 files
CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c
CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle.c
endif
ifeq ($(CONFIG_STM32N6_USART),y)
CHIP_CSRCS += stm32_serial.c
endif
# Chip-specific RCC
CHIP_CSRCS += stm32n6xx_rcc.c
arch/arm/src/stm32n6/chip.h
+57
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@@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/src/stm32n6/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_CHIP_H
#define __ARCH_ARM_SRC_STM32N6_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware
* files should then include this file for the proper setup.
*/
#include <arch/irq.h>
#include <arch/stm32n6/chip.h>
#include "hardware/stm32n6xxx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If the common ARMv8-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/stm32n6/chip.h header file.
*/
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
/* Cache line sizes for Cortex-M55 (32 bytes). */
#define ARMV8M_ICACHE_LINESIZE 32
#define ARMV8M_DCACHE_LINESIZE 32
#endif /* __ARCH_ARM_SRC_STM32N6_CHIP_H */
arch/arm/src/stm32n6/hardware/stm32n6xxx_gpio.h
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arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h
+173
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@@ -0,0 +1,173 @@
/****************************************************************************
* arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_MEMORYMAP_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* STM32N6XXX Address Blocks ************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x34000000 /* 0x34000000: SRAM (no internal flash) */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M55 block */
#define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == 0x30000000)
/* SRAM Addresses ***********************************************************/
#define STM32_SRAM1_BASE 0x34000000 /* SRAM1 base */
#define STM32_SRAM2_BASE 0x34100000 /* SRAM2 base */
/* External Memory **********************************************************/
#define STM32_XSPI1_BANK 0x90000000 /* XSPI1 memory-mapped region */
#define STM32_XSPI2_BANK 0x70000000 /* XSPI2 memory-mapped region */
/* Peripheral Base Addresses ************************************************
*
* Each peripheral is physically aliased twice: a Non-Secure alias at
* 0x4xxxxxxx and a Secure alias at 0x5xxxxxxx (RM0486 section 3.5.1).
* The same hardware register is reached through either alias.
*
* In DEV boot mode the CPU runs in Secure state with SAU disabled and
* SAU_CTRL.ALLNS=0, so the SAU unilaterally marks every address as
* Secure regardless of which alias is used; both aliases therefore work
* for register access from this port.
*
* We pick the Secure aliases consistently to match the register listings
* in the Reference Manual and to leave the Non-Secure aliases free for a
* future Non-Secure world.
*
* Secure alias = Non-Secure alias + 0x10000000
*/
#define STM32_APB1_BASE 0x50000000 /* APB1 (Secure) */
#define STM32_APB2_BASE 0x52000000 /* APB2 (Secure) */
#define STM32_APB4_BASE 0x56000000 /* APB4 (Secure) */
#define STM32_APB5_BASE 0x58000000 /* APB5 (Secure) - LTDC/DCMIPP/CSI2/GFXTIM/VENC */
#define STM32_AHB4_BASE 0x56020000 /* AHB4 (Secure) */
/* APB1 peripherals *********************************************************/
#define STM32_TIM2_BASE 0x50000000
#define STM32_TIM3_BASE 0x50000400
#define STM32_TIM4_BASE 0x50000800
#define STM32_TIM5_BASE 0x50000c00
#define STM32_TIM6_BASE 0x50001000
#define STM32_TIM7_BASE 0x50001400
#define STM32_LPTIM1_BASE 0x50002400
#define STM32_SPI2_BASE 0x50003800
#define STM32_SPI3_BASE 0x50003c00
#define STM32_USART2_BASE 0x50004400
#define STM32_USART3_BASE 0x50004800
#define STM32_UART4_BASE 0x50004c00
#define STM32_UART5_BASE 0x50005000
#define STM32_I2C1_BASE 0x50005400
#define STM32_I2C2_BASE 0x50005800
#define STM32_I2C3_BASE 0x50005c00
/* APB2 peripherals *********************************************************/
#define STM32_TIM1_BASE 0x52000000
#define STM32_TIM8_BASE 0x52000400
#define STM32_USART1_BASE 0x52001000
#define STM32_SPI1_BASE 0x52003000
#define STM32_SPI4_BASE 0x52003400
#define STM32_TIM15_BASE 0x52004000
#define STM32_TIM16_BASE 0x52004400
#define STM32_TIM17_BASE 0x52004800
#define STM32_SPI5_BASE 0x52005000
/* APB4 peripherals *********************************************************/
#define STM32_SPI6_BASE 0x56001400
#define STM32_I2C4_BASE 0x56001c00
#define STM32_LPTIM2_BASE 0x56002400
#define STM32_LPTIM3_BASE 0x56002800
#define STM32_LPTIM4_BASE 0x56002c00
#define STM32_LPTIM5_BASE 0x56003000
/* APB4 peripherals (RTC on APB4 + 0x4000) **********************************/
#define STM32_RTC_BASE 0x56004000
#define STM32_TAMP_BASE 0x56004400
#define STM32_IWDG_BASE 0x56004800
#define STM32_BSEC_BASE 0x56009000
#define STM32_DTS_BASE 0x5600a000
/* AHB4 peripherals *********************************************************/
#define STM32_GPIOA_BASE 0x56020000
#define STM32_GPIOB_BASE 0x56020400
#define STM32_GPIOC_BASE 0x56020800
#define STM32_GPIOD_BASE 0x56020c00
#define STM32_GPIOE_BASE 0x56021000
#define STM32_GPIOF_BASE 0x56021400
#define STM32_GPIOG_BASE 0x56021800
#define STM32_GPIOH_BASE 0x56021c00
#define STM32_GPION_BASE 0x56023400
#define STM32_GPIOO_BASE 0x56023800
#define STM32_GPIOP_BASE 0x56023c00
#define STM32_GPIOQ_BASE 0x56024000
#define STM32_CRC_BASE 0x56024c00
#define STM32_PWR_BASE 0x56024800
#define STM32_EXTI_BASE 0x56025000
#define STM32_RCC_BASE 0x56028000
/* AHB1 peripherals *********************************************************/
#define STM32_GPDMA1_BASE 0x50021000 /* GPDMA1 (AHB1, Secure) */
#define STM32_ADC1_BASE 0x50022000 /* ADC1 (AHB1, Secure) */
#define STM32_ADC2_BASE 0x50022100 /* ADC2 (AHB1, Secure) */
#define STM32_ADC12_COMMON_BASE 0x50022300 /* ADC1/2 common (AHB1, Secure) */
/* AHB3 peripherals *********************************************************/
#define STM32_RNG_BASE 0x54020000 /* RNG (AHB3, Secure) */
#define STM32_RIFSC_BASE 0x54024000 /* RIFSC (AHB3, Secure) */
/* AHB2 peripherals *********************************************************/
#define STM32_RAMCFG_BASE 0x52023000 /* RAMCFG (AHB2, Secure) */
/* AHB5 peripherals *********************************************************/
#define STM32_AHB5_BASE 0x58020000 /* AHB5 (Secure) */
#define STM32_HPDMA1_BASE 0x58020000 /* HPDMA1 (AHB5, Secure) */
#define STM32_XSPI2_BASE 0x5802A000 /* XSPI2 controller (AHB5, Secure) */
#define STM32_XSPIM_BASE 0x5802B400 /* XSPIM IO Manager (AHB5, Secure) */
#define STM32_USB1_HS_PHYC_BASE 0x5803FC00 /* USB1 HS PHY controller (Secure) */
#define STM32_USB1_OTG_HS_BASE 0x58040000 /* USB1 OTG HS (Secure) */
#define STM32_USB2_OTG_HS_BASE 0x58080000 /* USB2 OTG HS (Secure) */
#define STM32_USB2_HS_PHYC_BASE 0x580C0000 /* USB2 HS PHY controller (Secure) */
/* SYSCFG *******************************************************************/
#define STM32_SYSCFG_BASE 0x56008000 /* SYSCFG (Secure) */
#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_MEMORYMAP_H */
arch/arm/src/stm32n6/hardware/stm32n6xxx_pinmap.h
+54
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/****************************************************************************
* arch/arm/src/stm32n6/hardware/stm32n6xxx_pinmap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PINMAP_H
#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if USART1_TX connects via PE5 on some board, then the following
* definition should appear in the board.h header file for that board:
*
* #define GPIO_USART1_TX GPIO_USART1_TX_1
*
* The driver will then automatically configure PE5 as the USART1 TX pin.
*/
/* USART1: PE5=TX (AF7), PE6=RX (AF7) - ST-Link Virtual COM Port */
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_SPEED_50MHZ | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN5)
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_SPEED_50MHZ | GPIO_PORTE | GPIO_PIN6)
#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PINMAP_H */
arch/arm/src/stm32n6/hardware/stm32n6xxx_pwr.h
+112
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/****************************************************************************
* arch/arm/src/stm32n6/hardware/stm32n6xxx_pwr.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PWR_H
#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
#define STM32_PWR_CR4_OFFSET 0x000c /* Power control register 4 */
#define STM32_PWR_VOSCR_OFFSET 0x0020 /* Voltage scaling control register */
#define STM32_PWR_BDCR1_OFFSET 0x0024 /* Backup domain control register 1 */
#define STM32_PWR_BDCR2_OFFSET 0x0028 /* Backup domain control register 2 */
#define STM32_PWR_DBPCR_OFFSET 0x002c /* Debug backup domain protection control register */
#define STM32_PWR_CPUCR_OFFSET 0x0030 /* CPU power control register */
#define STM32_PWR_SVMCR1_OFFSET 0x0034 /* Supply voltage monitoring control register 1 */
#define STM32_PWR_SVMCR2_OFFSET 0x0038 /* Supply voltage monitoring control register 2 */
#define STM32_PWR_SVMCR3_OFFSET 0x003c /* Supply voltage monitoring control register 3 */
#define STM32_PWR_PRIVCFGR_OFFSET 0x0104 /* Privilege configuration register */
#define STM32_PWR_SECCFGR_OFFSET 0x0100 /* Secure configuration register */
/* Register Addresses *******************************************************/
#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET)
#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET)
#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET)
#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET)
#define STM32_PWR_VOSCR (STM32_PWR_BASE + STM32_PWR_VOSCR_OFFSET)
#define STM32_PWR_BDCR1 (STM32_PWR_BASE + STM32_PWR_BDCR1_OFFSET)
#define STM32_PWR_BDCR2 (STM32_PWR_BASE + STM32_PWR_BDCR2_OFFSET)
#define STM32_PWR_DBPCR (STM32_PWR_BASE + STM32_PWR_DBPCR_OFFSET)
#define STM32_PWR_CPUCR (STM32_PWR_BASE + STM32_PWR_CPUCR_OFFSET)
#define STM32_PWR_SVMCR1 (STM32_PWR_BASE + STM32_PWR_SVMCR1_OFFSET)
#define STM32_PWR_SVMCR2 (STM32_PWR_BASE + STM32_PWR_SVMCR2_OFFSET)
#define STM32_PWR_SVMCR3 (STM32_PWR_BASE + STM32_PWR_SVMCR3_OFFSET)
#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET)
#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Debug Backup Domain Protection Control Register (PWR_DBPCR) */
#define PWR_DBPCR_DBP (1 << 0) /* Bit 0: Disable backup domain write protection */
/* Voltage Scaling Control Register (PWR_VOSCR)
*
* STM32N6 has a single-bit VOS field selecting between low (0) and high (1)
* voltage scaling. VOSRDY/ACTVOS status flags live in the same register.
*/
#define PWR_VOSCR_VOS (1 << 0) /* Bit 0: Voltage scaling 0=low, 1=high */
#define PWR_VOSCR_VOSRDY (1 << 1) /* Bit 1: VOS Ready */
#define PWR_VOSCR_ACTVOS (1 << 16) /* Bit 16: Active VOS (read-back) */
#define PWR_VOSCR_ACTVOSRDY (1 << 17) /* Bit 17: Active VOS ready */
/* CPU Power Control Register (PWR_CPUCR) */
#define PWR_CPUCR_PDDS (1 << 0) /* Bit 0: Power down deepsleep for CPU */
#define PWR_CPUCR_STOPF (1 << 8) /* Bit 8: STOP flag */
#define PWR_CPUCR_SBF (1 << 9) /* Bit 9: Standby flag */
#define PWR_CPUCR_SVOS_SHIFT (16) /* Bits 16-17: System voltage scaling in stop */
#define PWR_CPUCR_SVOS_MASK (3 << PWR_CPUCR_SVOS_SHIFT)
/* Supply Voltage Monitoring Control Register 1 (PWR_SVMCR1) - VddIO4 */
#define PWR_SVMCR1_VDDIO4SV (1 << 8) /* Bit 8: VddIO4 supply valid */
#define PWR_SVMCR1_VDDIO4VRSEL (1 << 16) /* Bit 16: VddIO4 high-speed low-voltage */
/* Supply Voltage Monitoring Control Register 2 (PWR_SVMCR2) - VddIO5 */
#define PWR_SVMCR2_VDDIO5SV (1 << 8) /* Bit 8: VddIO5 supply valid */
#define PWR_SVMCR2_VDDIO5VRSEL (1 << 16) /* Bit 16: VddIO5 high-speed low-voltage */
/* Supply Voltage Monitoring Control Register 3 (PWR_SVMCR3) - VddIO2/3 */
#define PWR_SVMCR3_VDDIO2SV (1 << 8) /* Bit 8: VddIO2 supply valid */
#define PWR_SVMCR3_VDDIO3SV (1 << 9) /* Bit 9: VddIO3 supply valid */
#define PWR_SVMCR3_VDDIO2VRSEL (1 << 16) /* Bit 16: VddIO2 high-speed low-voltage */
#define PWR_SVMCR3_VDDIO3VRSEL (1 << 17) /* Bit 17: VddIO3 high-speed low-voltage */
#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_PWR_H */
arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h
+288
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arch/arm/src/stm32n6/hardware/stm32n6xxx_syscfg.h
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/****************************************************************************
* arch/arm/src/stm32n6/hardware/stm32n6xxx_syscfg.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/stm32n6xxx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_SYSCFG_INITSVTORCR_OFFSET 0x010 /* Secure vector table base address register */
#define STM32_SYSCFG_VDDIO2CCCR_OFFSET 0x054 /* VDDIO2 compensation cell control register */
#define STM32_SYSCFG_VDDIO3CCCR_OFFSET 0x05c /* VDDIO3 compensation cell control register */
#define STM32_SYSCFG_VDDCCCR_OFFSET 0x064 /* VDD compensation cell control register */
/* Register Addresses *******************************************************/
#define STM32_SYSCFG_INITSVTORCR (STM32_SYSCFG_BASE + STM32_SYSCFG_INITSVTORCR_OFFSET)
#define STM32_SYSCFG_VDDIO2CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_VDDIO2CCCR_OFFSET)
#define STM32_SYSCFG_VDDIO3CCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_VDDIO3CCCR_OFFSET)
#define STM32_SYSCFG_VDDCCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_VDDCCCR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Compensation cell control register (VDDxCCCR / VDDIOxCCCR). The four
* banks (VDD, VDDIO2, VDDIO3, VDDIO4, VDDIO5) share an identical layout, so
* the port refers to them with a single set of CCCR_* macros.
*/
#define SYSCFG_CCCR_CS (1 << 9) /* Bit 9: Compensation code source select */
#define SYSCFG_CCCR_EN (1 << 8) /* Bit 8: Enable compensation cell */
#define SYSCFG_CCCR_RAPSRC_SHIFT (4) /* Bits 7-4: Manual PMOS compensation code */
#define SYSCFG_CCCR_RAPSRC_MASK (0xf << SYSCFG_CCCR_RAPSRC_SHIFT)
#define SYSCFG_CCCR_RANSRC_SHIFT (0) /* Bits 3-0: Manual NMOS compensation code */
#define SYSCFG_CCCR_RANSRC_MASK (0xf << SYSCFG_CCCR_RANSRC_SHIFT)
/* ES0620 I/O compensation mitigation: write 0x00000287 (EN=0, CS=1,
* RAPSRC=0x8, RANSRC=0x7) to VDDCCCR and every VDDIOxCCCR before
* enabling high-speed pads. This disables the cell and overrides the
* broken defaults (RAPSRC=0x7, RANSRC=0x8) that deform output edges.
*/
#define SYSCFG_CCCR_ES0620_MANUAL (SYSCFG_CCCR_CS | \
(8 << SYSCFG_CCCR_RAPSRC_SHIFT) | \
(7 << SYSCFG_CCCR_RANSRC_SHIFT))
#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32N6XXX_SYSCFG_H */
arch/arm/src/stm32n6/hardware/stm32n6xxx_uart.h
+252
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arch/arm/src/stm32n6/stm32.h
+46
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/****************************************************************************
* arch/arm/src/stm32n6/stm32.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_H
#define __ARCH_ARM_SRC_STM32N6_STM32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_lowputc.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_uart.h"
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_H */
arch/arm/src/stm32n6/stm32_gpio.c
+374
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arch/arm/src/stm32n6/stm32_gpio.h
+317
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arch/arm/src/stm32n6/stm32_idle.c
+86
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_idle.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "nvic.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* SLEEPDEEP is cleared once at boot in __start_c() so that WFI here
* enters plain SLEEP mode -- the system clock keeps running and SysTick
* continues to fire, waking the CPU on the next tick.
*/
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}
arch/arm/src/stm32n6/stm32_irq.c
+473
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arch/arm/src/stm32n6/stm32_lowputc.c
+257
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arch/arm/src/stm32n6/stm32_lowputc.h
+66
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_lowputc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32N6_STM32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization of serial console.
*
****************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_LOWPUTC_H */
arch/arm/src/stm32n6/stm32_pwr.c
+92
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_pwr.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include "stm32_pwr.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables write access to the backup domain (RTC registers, RTC backup
* data registers and backup SRAM).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32_pwr_enablebkp(bool writable)
{
uint32_t regval;
bool waswritable;
regval = getreg32(STM32_PWR_DBPCR);
waswritable = ((regval & PWR_DBPCR_DBP) != 0);
if (writable)
{
regval |= PWR_DBPCR_DBP;
}
else
{
regval &= ~PWR_DBPCR_DBP;
}
putreg32(regval, STM32_PWR_DBPCR);
return waswritable;
}
/****************************************************************************
* Name: stm32_pwr_enablevddio
*
* Description:
* Mark a set of I/O voltage domains as supply-valid in PWR SVMCR3 and
* optionally select their VRSEL (1.8 V) range. The board passes the
* bitmask of PWR_SVMCR3_* bits matching the GPIO ports it uses.
*
* Input Parameters:
* mask - OR of PWR_SVMCR3_VDDIOxSV and PWR_SVMCR3_VDDIOxVRSEL bits.
*
****************************************************************************/
void stm32_pwr_enablevddio(uint32_t mask)
{
modifyreg32(STM32_PWR_SVMCR3, 0, mask);
}
arch/arm/src/stm32n6/stm32_pwr.h
+92
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_pwr.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32N6_STM32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/stm32n6xxx_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables write access to the backup domain (RTC registers, RTC backup
* data registers and backup SRAM).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32_pwr_enablebkp(bool writable);
/****************************************************************************
* Name: stm32_pwr_enablevddio
*
* Description:
* Mark a set of I/O voltage domains as supply-valid in PWR SVMCR3.
* The board passes an OR of PWR_SVMCR3_VDDIOxSV (and optionally
* PWR_SVMCR3_VDDIOxVRSEL for the 1.8 V range) bits matching the GPIO
* ports it uses.
*
****************************************************************************/
void stm32_pwr_enablevddio(uint32_t mask);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_PWR_H */
arch/arm/src/stm32n6/stm32_rcc.c
+90
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_rcc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32_rcc.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Establish the clock tree from the values in board.h, then enable the
* peripheral clocks needed by the chip.
*
****************************************************************************/
void stm32_clockconfig(void)
{
stm32_stdclockconfig();
stm32_rcc_enableperipherals();
}
/****************************************************************************
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation: When re-awakening from deep-sleep modes, it is necessary to
* re-enable/re-start the PLL.
*
* This function performs a subset of the operations performed by
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
stm32_stdclockconfig();
}
#endif
arch/arm/src/stm32n6/stm32_rcc.h
+120
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/****************************************************************************
* arch/arm/src/stm32n6/stm32_rcc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32N6_STM32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "chip.h"
#include "hardware/stm32n6xxx_rcc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_clockconfig(void);
/****************************************************************************
* Name: stm32_stdclockconfig
*
* Description:
* The standard logic to configure the clocks based on settings in board.h.
* This function is chip type specific and implemented in stm32n6xx_rcc.c.
*
****************************************************************************/
void stm32_stdclockconfig(void);
/****************************************************************************
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation: When re-awakening from deep-sleep modes, it is necessary to
* re-enable/re-start the PLL
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void);
#endif
/****************************************************************************
* Name: stm32_rcc_enableperipherals
*
* Description:
* Enable all the chip peripherals according to configuration. This is
* chip type specific and thus implemented in stm32n6xx_rcc.c.
*
****************************************************************************/
void stm32_rcc_enableperipherals(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_RCC_H */
arch/arm/src/stm32n6/stm32_serial.c
+1772
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arch/arm/src/stm32n6/stm32_start.c
+267
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arch/arm/src/stm32n6/stm32_start.h
+47
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@@ -0,0 +1,47 @@
/****************************************************************************
* arch/arm/src/stm32n6/stm32_start.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_START_H
#define __ARCH_ARM_SRC_STM32N6_STM32_START_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_board_initialize
*
* Description:
* All STM32N6 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void stm32_board_initialize(void);
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_START_H */
arch/arm/src/stm32n6/stm32_timerisr.c
+116
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@@ -0,0 +1,116 @@
/****************************************************************************
* arch/arm/src/stm32n6/stm32_timerisr.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "chip.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 ms interval).
*
* SysTick is clocked from the processor clock when CLKSOURCE=1 (the
* configuration used here). The reload value must fit in 24 bits.
*/
#define SYSTICK_RELOAD ((STM32_CPUCLK_FREQUENCY / CLK_TCK) - 1)
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_timerisr
*
* Description:
* SysTick interrupt handler. Processes the system timer tick.
*
****************************************************************************/
static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
{
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize the system
* timer interrupt using SysTick clocked from the processor clock.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
/* Enable SysTick clocked from the processor clock with interrupts on */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
up_enable_irq(STM32_IRQ_SYSTICK);
}
arch/arm/src/stm32n6/stm32_uart.h
+96
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@@ -0,0 +1,96 @@
/****************************************************************************
* arch/arm/src/stm32n6/stm32_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32N6_STM32_UART_H
#define __ARCH_ARM_SRC_STM32N6_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#include "hardware/stm32n6xxx_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Sanity checks */
#if !defined(CONFIG_STM32N6_USART1)
# undef CONFIG_STM32N6_USART1_SERIALDRIVER
# undef CONFIG_STM32N6_USART1_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32N6_USART1)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32N6_USART1_SERIALDRIVER)
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
#define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32N6_STM32_UART_H */
arch/arm/src/stm32n6/stm32n6xx_rcc.c
+261
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tools/ci/testlist/arm-14.dat
+1
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@@ -1,4 +1,5 @@
/arm/stm32l*,CONFIG_ARM_TOOLCHAIN_GNU_EABI
/arm/stm32n*,CONFIG_ARM_TOOLCHAIN_GNU_EABI
/arm/stm32u*,CONFIG_ARM_TOOLCHAIN_GNU_EABI
/arm/stm32w*,CONFIG_ARM_TOOLCHAIN_GNU_EABI