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https://github.com/apache/nuttx.git
synced 2026-05-13 02:18:38 +08:00
xtensa/esp32s3: Support octal lines mode SPIRAM
This commit is contained in:
Dong Heng
Xiang Xiao
@@ -162,6 +162,38 @@ To test it, just run the ``oneshot`` example::
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Waiting...
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Finished
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psram_quad
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----------
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This config tests the PSRAM driver over SPIRAM interface in quad mode.
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You can use the mm command to test the PSRAM memory::
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nsh> mm
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mallinfo:
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Total space allocated from system = 8803232
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Number of non-inuse chunks = 2
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Largest non-inuse chunk = 8388592
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Total allocated space = 9672
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Total non-inuse space = 8793560
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(0)Allocating 5011 bytes
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......
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(31)Releasing memory at 0x3fc8c088 (size=24 bytes)
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mallinfo:
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Total space allocated from system = 8803232
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Number of non-inuse chunks = 2
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Largest non-inuse chunk = 8388592
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Total allocated space = 9672
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Total non-inuse space = 8793560
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TEST COMPLETE
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psram_octal
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-----------
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Similar to the ```psram_quad``` configuration but using the SPIRAM
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interface in octal mode.
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pwm
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---
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@@ -531,6 +531,7 @@ config ESP32S3_SPIRAM_SPEED_80M
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config ESP32S3_SPIRAM_SPEED_120M
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bool "120MHz clock speed"
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depends on ESP32S3_SPIRAM_MODE_QUAD
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endchoice # ESP32S3_SPIRAM_SPEED
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@@ -1017,6 +1018,9 @@ choice ESP32S3_FLASH_MODE
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config ESP32S3_FLASH_MODE_QOUT
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bool "Quad Output (QOUT)"
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config ESP32S3_FLASH_MODE_OCT
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bool "Octal"
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endchoice # ESP32S3_FLASH_MODE
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choice ESP32S3_FLASH_FREQ
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@@ -1039,6 +1043,25 @@ choice ESP32S3_FLASH_FREQ
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endchoice # ESP32S3_FLASH_FREQ
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config ESP32S3_FLASH_FREQ
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int
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default 120 if ESP32S3_FLASH_FREQ_120M
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default 80 if ESP32S3_FLASH_FREQ_80M
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default 40 if ESP32S3_FLASH_FREQ_40M
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default 20 if ESP32S3_FLASH_FREQ_20M
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choice ESP32S3_FLASH_SAMPLE_MODE
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prompt "Flash Sampling Mode"
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default ESP32S3_FLASH_SAMPLE_MODE_DTR if ESP32S3_FLASH_MODE_OCT
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default ESP32S3_FLASH_SAMPLE_MODE_STR if !ESP32S3_FLASH_MODE_OCT
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config ESP32S3_FLASH_SAMPLE_MODE_DTR
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depends on ESP32S3_FLASH_MODE_OCT
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bool "DTR Mode"
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config ESP32S3_FLASH_SAMPLE_MODE_STR
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bool "STR Mode"
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endchoice
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config ESP32S3_HAVE_OTA_PARTITION
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bool
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default n
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@@ -30,7 +30,7 @@ HEAD_CSRC = esp32s3_start.c
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CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c
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CHIP_CSRCS += esp32s3_systemreset.c esp32s3_user.c esp32s3_allocateheap.c
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CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c
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CHIP_CSRCS += esp32s3_rtc_gpio.c esp32s3_libc_stubs.c
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CHIP_CSRCS += esp32s3_rtc_gpio.c esp32s3_libc_stubs.c esp32s3_spi_timing.c
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# Configuration-dependent ESP32-S3 files
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@@ -118,7 +118,14 @@ endif
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ifeq ($(CONFIG_ESP32S3_SPIRAM),y)
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CHIP_CSRCS += esp32s3_spiram.c
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CHIP_CSRCS += esp32s3_psram.c
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ifeq ($(CONFIG_ESP32S3_SPIRAM_MODE_QUAD),y)
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CHIP_CSRCS += esp32s3_psram_quad.c
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endif
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ifeq ($(CONFIG_ESP32S3_SPIRAM_MODE_OCT),y)
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CHIP_CSRCS += esp32s3_psram_octal.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S3_TOUCH),y)
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@@ -38,6 +38,9 @@
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#include "xtensa.h"
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#include "hardware/esp32s3_rom_layout.h"
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#ifdef CONFIG_ESP32S3_SPIRAM
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# include "esp32s3_spiram.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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@@ -154,5 +157,14 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
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#if CONFIG_MM_REGIONS > 1
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void xtensa_add_region(void)
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{
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#ifdef CONFIG_ESP32S3_SPIRAM
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void *start;
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size_t size;
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start = (void *)esp_spiram_allocable_vaddr_start();
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size = (size_t)(esp_spiram_allocable_vaddr_end() -
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esp_spiram_allocable_vaddr_start());
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umm_addregion(start, size);
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#endif
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}
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#endif
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File diff suppressed because it is too large
Load Diff
+1
-1
@@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_psram.c
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* arch/xtensa/src/esp32s3/esp32s3_psram_quad.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@@ -0,0 +1,366 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_spi_timing.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/param.h>
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#include "xtensa.h"
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#include "esp32s3_gpio.h"
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#include "esp32s3_psram.h"
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#include "esp32s3_spi_timing.h"
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#include "hardware/esp32s3_spi_mem_reg.h"
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#include "hardware/esp32s3_iomux.h"
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#include "hardware/esp32s3_gpio.h"
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#include "hardware/esp32s3_gpio_sigmap.h"
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#include "rom/esp32s3_spiflash.h"
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#include "rom/esp32s3_opi_flash.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CORE_CLK_REG_SEL_80M 0
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#define CORE_CLK_REG_SEL_120M 1
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#define CORE_CLK_REG_SEL_160M 2
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#define CORE_CLK_REG_SEL_240M 3
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#if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR) || \
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defined(CONFIG_ESP32S3_SPIRAM_MODE_OCT)
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# define ESP32S3_SPI_TIMING_CORE_CLOCK_DIV 2
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#else
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# define ESP32S3_SPI_TIMING_CORE_CLOCK_DIV 1
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#endif
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#if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR)
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# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M)
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# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 160
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# elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
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# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 240
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# endif
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#elif defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_STR)
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# if defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
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# if ESP32S3_SPI_TIMING_CORE_CLOCK_DIV == 1
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# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 120
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# elif ESP32S3_SPI_TIMING_CORE_CLOCK_DIV == 2
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# define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 240
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# endif
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# endif
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#endif
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#if defined(CONFIG_ESP32S3_SPIRAM_MODE_OCT)
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# if defined(CONFIG_ESP32S3_SPIRAM_SPEED_80M)
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# define ESP32S3_SPI_TIMING_PSRAM_CORE_CLK 160
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# endif
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#elif defined(ESP32S3_SPI_TIMING_PSRAM_STR_MODE)
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# if defined(CONFIG_ESP32S3_SPIRAM_SPEED_120M)
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# if ESP32S3_SPI_TIMING_CORE_CLOCK_DIV == 1
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# define ESP32S3_SPI_TIMING_PSRAM_CORE_CLK 120
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# elif ESP32S3_SPI_TIMING_CORE_CLOCK_DIV == 2
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# define ESP32S3_SPI_TIMING_PSRAM_CORE_CLK 240
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# endif
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# endif
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#endif
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#if ESP32S3_SPI_TIMING_FLASH_TUNING
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# if ESP32S3_SPI_TIMING_PSRAM_TUNING
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# if ESP32S3_SPI_TIMING_FLASH_CORE_CLK != ESP32S3_SPI_TIMING_PSRAM_CORE_CLK
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# error "FLASH and PSRAM Mode configuration are not supported"
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# endif
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# define ESP32S3_SPI_TIMING_CORE_CLK ESP32S3_SPI_TIMING_FLASH_CORE_CLK
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# else
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# if ESP32S3_SPI_TIMING_FLASH_CORE_CLK % ESP32S3_SPI_TIMING_PSRAM_CLOCK != 0
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# error "FLASH and PSRAM Mode configuration are not supported"
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# endif
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# define ESP32S3_SPI_TIMING_CORE_CLK ESP32S3_SPI_TIMING_FLASH_CORE_CLK
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# endif
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#else
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# if ESP32S3_SPI_TIMING_PSRAM_TUNING
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# if ESP32S3_SPI_TIMING_PSRAM_CORE_CLK % ESP32S3_SPI_TIMING_FLASH_CLOCK != 0
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# error "FLASH and PSRAM Mode configuration are not supported"
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# endif
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# define ESP32S3_SPI_TIMING_CORE_CLK ESP32S3_SPI_TIMING_PSRAM_CORE_CLK
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# else
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# define ESP32S3_SPI_TIMING_CORE_CLK 80
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# endif
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#endif
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#define ESP32S3_CHECK_POWER_OF_2(n) ((((n) & ((~(n)) + 1))) == (n))
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#ifdef CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR
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# if ESP32S3_CHECK_POWER_OF_2(ESP32S3_SPI_TIMING_CORE_CLK / ESP32S3_SPI_TIMING_FLASH_CLOCK) == 0
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# error "FLASH and PSRAM Mode configuration are not supported"
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# endif
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#endif
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#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT
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# if ESP32S3_CHECK_POWER_OF_2(ESP32S3_SPI_TIMING_CORE_CLK / ESP32S3_SPI_TIMING_PSRAM_CLOCK) == 0
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# error "FLASH and PSRAM Mode configuration are not supported"
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# endif
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#endif
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#if ESP32S3_SPI_TIMING_CORE_CLK == 80
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# define DEFAULT_CORE_CLOCK CORE_CLOCK_80M
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# define DEFAULT_CORE_CLK_REG CORE_CLK_REG_SEL_80M
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#elif ESP32S3_SPI_TIMING_CORE_CLK == 120
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# define DEFAULT_CORE_CLOCK CORE_CLOCK_120M
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# define DEFAULT_CORE_CLK_REG CORE_CLK_REG_SEL_120M
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#elif ESP32S3_SPI_TIMING_CORE_CLK == 160
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# define DEFAULT_CORE_CLOCK CORE_CLOCK_160M
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# define DEFAULT_CORE_CLK_REG CORE_CLK_REG_SEL_160M
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#elif ESP32S3_SPI_TIMING_CORE_CLK == 240
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# define DEFAULT_CORE_CLOCK CORE_CLOCK_240M
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# define DEFAULT_CORE_CLK_REG CORE_CLK_REG_SEL_240M
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#else
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# error "SPI timing core clock is invalid"
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#endif
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#if defined(CONFIG_ESP32S3_FLASH_FREQ_20M)
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# define FLASH_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 20)
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#elif defined(CONFIG_ESP32S3_FLASH_FREQ_40M)
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# define FLASH_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 40)
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#elif defined(CONFIG_ESP32S3_FLASH_FREQ_80M)
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# define FLASH_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 80)
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#elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
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# define FLASH_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 120)
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#else
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# error "SPI timing flash clock is invalid"
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#endif
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#if defined(CONFIG_ESP32S3_SPIRAM_SPEED_40M)
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# define PSRAM_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 40)
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#elif defined(CONFIG_ESP32S3_SPIRAM_SPEED_80M)
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# define PSRAM_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 80)
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#elif defined(CONFIG_ESP32S3_SPIRAM_SPEED_120M)
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# define PSRAM_CLOCK_DIVIDER (ESP32S3_SPI_TIMING_CORE_CLK / 120)
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#else
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# define PSRAM_CLOCK_DIVIDER 0
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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enum core_clock_e
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{
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CORE_CLOCK_80M = 0,
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CORE_CLOCK_120M = 1,
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CORE_CLOCK_160M = 2,
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CORE_CLOCK_240M = 3
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: set_psram_clock
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*
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* Description:
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* Set PSRAM clock.
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*
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* Input Parameters:
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* spi_num - SPI port
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* freqdiv - SPI clock divideor
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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static void set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1)
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{
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
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}
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else
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{
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uint32_t freqbits = ((freqdiv - 1) << SPI_MEM_SCLKCNT_N_S) |
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((freqdiv / 2 - 1) << SPI_MEM_SCLKCNT_H_S) |
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((freqdiv - 1) << SPI_MEM_SCLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
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}
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}
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/****************************************************************************
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* Name: set_flash_clock
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*
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* Description:
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* Set flash clock.
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*
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* Input Parameters:
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* spi_num - SPI port
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* freqdiv - SPI clock divideor
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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static void IRAM_ATTR set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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DEBUGASSERT(freqdiv > 0);
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if (freqdiv == 1)
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{
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
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}
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else
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{
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uint32_t freqbits = ((freqdiv - 1) << SPI_MEM_CLKCNT_N_S) |
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((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S) |
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((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s3_spi_timing_set_pin_drive_strength
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*
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* Description:
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* Make SPI all GPIO strength to be 3 under default clock.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp32s3_spi_timing_set_pin_drive_strength(void)
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{
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const uint32_t regs[] =
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{
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IO_MUX_GPIO27_REG,
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IO_MUX_GPIO28_REG,
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IO_MUX_GPIO31_REG,
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IO_MUX_GPIO32_REG,
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IO_MUX_GPIO33_REG,
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IO_MUX_GPIO34_REG,
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IO_MUX_GPIO35_REG,
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IO_MUX_GPIO36_REG,
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IO_MUX_GPIO37_REG
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};
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/* Set default clock */
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SET_PERI_REG_MASK(SPI_MEM_DATE_REG(0), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, 3);
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REG_SET_FIELD(SPI_MEM_DATE_REG(0), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, 3);
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/* Set default mspi d0 ~ d7, dqs pin drive strength */
|
||||
|
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for (int i = 0; i < nitems(regs); i++)
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{
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PIN_SET_DRV(regs[i], 3);
|
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}
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||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spi_timing_set_mspi_high_speed
|
||||
*
|
||||
* Description:
|
||||
* Make MSPI work under the frequency as users set, may add certain
|
||||
* delays to MSPI RX direction to meet timing requirements.
|
||||
*
|
||||
* Input Parameters:
|
||||
* spi1 - Select whether to control SPI1
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void IRAM_ATTR esp32s3_spi_timing_set_mspi_high_speed(bool spi1)
|
||||
{
|
||||
uint32_t flash_div = FLASH_CLOCK_DIVIDER;
|
||||
uint32_t psram_div = PSRAM_CLOCK_DIVIDER;
|
||||
|
||||
/* Set SPI0 & 1 core clock */
|
||||
|
||||
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
|
||||
SPI_MEM_CORE_CLK_SEL,
|
||||
DEFAULT_CORE_CLK_REG);
|
||||
|
||||
set_flash_clock(0, flash_div);
|
||||
if (spi1)
|
||||
{
|
||||
set_flash_clock(1, flash_div);
|
||||
}
|
||||
|
||||
set_psram_clock(0, psram_div);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spi_timing_set_mspi_low_speed
|
||||
*
|
||||
* Description:
|
||||
* Make MSPI work under 20MHz and remove the timing tuning required delays.
|
||||
*
|
||||
* Input Parameters:
|
||||
* spi1 - Select whether to control SPI1
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void IRAM_ATTR esp32s3_spi_timing_set_mspi_low_speed(bool spi1)
|
||||
{
|
||||
/**
|
||||
* Here we are going to set the SPI1 frequency to be 20MHz,
|
||||
* so we need to set SPI1 din_num and din_mode regs.
|
||||
*
|
||||
* Because SPI0 and SPI1 share the din_num and din_mode regs,
|
||||
* but if we clear SPI1 din_num and din_mode to 0 and SPI0 flash
|
||||
* module clock is still in high freq, it may not work correctly.
|
||||
*
|
||||
* Therefore, we need to set both the SPI0 and SPI1 and related
|
||||
* timing tuning regs to be 20MHz.
|
||||
*/
|
||||
|
||||
/* Set SPIMEM core clock as 80MHz, and set SPI1 and SPI0 clock
|
||||
* to be 20MHz by setting clock division as 4
|
||||
*/
|
||||
|
||||
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(0),
|
||||
SPI_MEM_CORE_CLK_SEL,
|
||||
CORE_CLK_REG_SEL_80M);
|
||||
|
||||
set_flash_clock(0, 4);
|
||||
if (spi1)
|
||||
{
|
||||
/* After tuning, won't touch SPI1 again */
|
||||
|
||||
set_flash_clock(1, 4);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,170 @@
|
||||
/****************************************************************************
|
||||
* arch/xtensa/src/esp32s3/esp32s3_spi_timing.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPI_TIMING_H
|
||||
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPI_TIMING_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_ESP32S3_FLASH_FREQ_20M)
|
||||
# define ESP32S3_SPI_TIMING_FLASH_CLOCK 20
|
||||
#elif defined(CONFIG_ESP32S3_FLASH_FREQ_40M)
|
||||
# define ESP32S3_SPI_TIMING_FLASH_CLOCK 40
|
||||
#elif defined(CONFIG_ESP32S3_FLASH_FREQ_80M)
|
||||
# define ESP32S3_SPI_TIMING_FLASH_CLOCK 80
|
||||
#elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M)
|
||||
# define ESP32S3_SPI_TIMING_FLASH_CLOCK 120
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR)
|
||||
# if ESP32S3_SPI_TIMING_FLASH_CLOCK > 40
|
||||
# define ESP32S3_SPI_TIMING_FLASH_TUNING 1
|
||||
# else
|
||||
# define ESP32S3_SPI_TIMING_FLASH_TUNING 0
|
||||
# endif
|
||||
#elif defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_STR)
|
||||
# if ESP32S3_SPI_TIMING_FLASH_CLOCK > 80
|
||||
# define ESP32S3_SPI_TIMING_FLASH_TUNING 1
|
||||
# else
|
||||
# define ESP32S3_SPI_TIMING_FLASH_TUNING 0
|
||||
# endif
|
||||
#else
|
||||
# define ESP32S3_SPI_TIMING_FLASH_TUNING 0
|
||||
#endif
|
||||
|
||||
#if ESP32S3_SPI_TIMING_FLASH_TUNING
|
||||
# error "SPI flash tuning is not supported"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM)
|
||||
# if defined(CONFIG_ESP32S3_SPIRAM_SPEED_40M)
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_CLOCK 40
|
||||
# elif defined(CONFIG_ESP32S3_SPIRAM_SPEED_80M)
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_CLOCK 80
|
||||
# elif defined(CONFIG_ESP32S3_SPIRAM_SPEED_120M)
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_CLOCK 120
|
||||
# endif
|
||||
#else
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_CLOCK 10
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_MODE_OCT)
|
||||
# if ESP32S3_SPI_TIMING_PSRAM_CLOCK > 40
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 1
|
||||
# else
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 0
|
||||
# endif
|
||||
#elif defined(CONFIG_ESP32S3_SPIRAM_MODE_QUAD)
|
||||
# if ESP32S3_SPI_TIMING_PSRAM_CLOCK > 80
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 1
|
||||
# else
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 0
|
||||
# endif
|
||||
#else
|
||||
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 0
|
||||
#endif
|
||||
|
||||
#if ESP32S3_SPI_TIMING_PSRAM_TUNING
|
||||
# error "SPI PSRAM tuning is not supported"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spi_timing_set_mspi_low_speed
|
||||
*
|
||||
* Description:
|
||||
* Make MSPI work under 20MHz and remove the timing tuning required delays.
|
||||
*
|
||||
* Input Parameters:
|
||||
* spi1 - Select whether to control SPI1
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void esp32s3_spi_timing_set_mspi_low_speed(bool control_spi1);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spi_timing_set_mspi_high_speed
|
||||
*
|
||||
* Description:
|
||||
* Make MSPI work under the frequency as users set, may add certain
|
||||
* delays to MSPI RX direction to meet timing requirements.
|
||||
*
|
||||
* Input Parameters:
|
||||
* spi1 - Select whether to control SPI1
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void esp32s3_spi_timing_set_mspi_high_speed(bool control_spi1);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spi_timing_set_pin_drive_strength
|
||||
*
|
||||
* Description:
|
||||
* Make SPI all GPIO strength to be 3 under default clock.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void esp32s3_spi_timing_set_pin_drive_strength(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#undef EXTERN
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPI_H */
|
||||
@@ -186,7 +186,7 @@ bool esp_spiram_test(void)
|
||||
|
||||
if (errct < 4)
|
||||
{
|
||||
merr("SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p],
|
||||
merr("SPI SRAM error@%p:%08x/%08x \n", &spiram[p], spiram[p],
|
||||
p ^ 0xaaaaaaaa);
|
||||
}
|
||||
}
|
||||
@@ -380,4 +380,26 @@ uint8_t esp_spiram_get_cs_io(void)
|
||||
return psram_get_cs_io();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get allocable virtual start address
|
||||
*
|
||||
* @return Allocable virtual start address
|
||||
*/
|
||||
|
||||
uint32_t esp_spiram_allocable_vaddr_start(void)
|
||||
{
|
||||
return g_allocable_vaddr_start;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get allocable virtual end address
|
||||
*
|
||||
* @return Allocable virtual end address
|
||||
*/
|
||||
|
||||
uint32_t esp_spiram_allocable_vaddr_end(void)
|
||||
{
|
||||
return g_allocable_vaddr_end;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -199,6 +199,22 @@ int rodata_flash2spiram_offset(void);
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get allocable virtual start address
|
||||
*
|
||||
* @return Allocable virtual start address
|
||||
*/
|
||||
|
||||
uint32_t esp_spiram_allocable_vaddr_start(void);
|
||||
|
||||
/**
|
||||
* @brief Get allocable virtual end address
|
||||
*
|
||||
* @return Allocable virtual end address
|
||||
*/
|
||||
|
||||
uint32_t esp_spiram_allocable_vaddr_end(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -42,10 +42,13 @@
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
# include "esp32s3_userspace.h"
|
||||
#endif
|
||||
#include "esp32s3_spi_timing.h"
|
||||
#include "hardware/esp32s3_cache_memory.h"
|
||||
#include "hardware/esp32s3_system.h"
|
||||
#include "hardware/esp32s3_extmem.h"
|
||||
#include "rom/esp32s3_libc_stubs.h"
|
||||
#include "rom/esp32s3_spiflash.h"
|
||||
#include "rom/esp32s3_opi_flash.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -336,6 +339,12 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
|
||||
|
||||
showprogress('A');
|
||||
|
||||
#if defined(CONFIG_ESP32S3_FLASH_MODE_OCT) || \
|
||||
defined(CONFIG_ESP32S3_SPIRAM_MODE_OCT)
|
||||
esp_rom_opiflash_pin_config();
|
||||
esp32s3_spi_timing_set_pin_drive_strength();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ESP32S3_SPIRAM_BOOT_INIT)
|
||||
if (esp_spiram_init() != OK)
|
||||
{
|
||||
|
||||
@@ -416,8 +416,10 @@ extern "C"
|
||||
|
||||
/* Description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. */
|
||||
|
||||
#define SPI_MEM_FADDR_OCT (BIT(6)) #define SPI_MEM_FADDR_OCT_M (BIT(6))
|
||||
#define SPI_MEM_FADDR_OCT_V 0x1 #define SPI_MEM_FADDR_OCT_S 6
|
||||
#define SPI_MEM_FADDR_OCT (BIT(6))
|
||||
#define SPI_MEM_FADDR_OCT_M (BIT(6))
|
||||
#define SPI_MEM_FADDR_OCT_V 0x1
|
||||
#define SPI_MEM_FADDR_OCT_S 6
|
||||
|
||||
/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
|
||||
|
||||
@@ -96,7 +96,6 @@ typedef struct
|
||||
#define ESP_ROM_SPIFLASH_BP0 BIT2
|
||||
#define ESP_ROM_SPIFLASH_BP1 BIT3
|
||||
#define ESP_ROM_SPIFLASH_BP2 BIT4
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | ESP_ROM_SPIFLASH_BP1 | ESP_ROM_SPIFLASH_BP2)
|
||||
#define ESP_ROM_SPIFLASH_QE BIT9
|
||||
|
||||
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
|
||||
|
||||
@@ -55,19 +55,11 @@ extern "C"
|
||||
#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
|
||||
|
||||
#define SPI0_R_QIO_DUMMY_CYCLELEN 3
|
||||
#define SPI0_R_QIO_ADDR_BITSLEN 31
|
||||
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI0_R_DIO_DUMMY_CYCLELEN 1
|
||||
#define SPI0_R_DIO_ADDR_BITSLEN 27
|
||||
#define SPI0_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI0_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define SPI1_R_QIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_QIO_ADDR_BITSLEN 31
|
||||
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
|
||||
#define SPI1_R_QIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_DIO_ADDR_BITSLEN 31
|
||||
#define SPI1_R_DIO_ADDR_BITSLEN 23
|
||||
#define SPI1_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI1_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
@@ -89,8 +81,8 @@ extern "C"
|
||||
#define ESP_ROM_SPIFLASH_BP0 BIT2
|
||||
#define ESP_ROM_SPIFLASH_BP1 BIT3
|
||||
#define ESP_ROM_SPIFLASH_BP2 BIT4
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\
|
||||
ESP_ROM_SPIFLASH_BP1|\
|
||||
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | \
|
||||
ESP_ROM_SPIFLASH_BP1 | \
|
||||
ESP_ROM_SPIFLASH_BP2)
|
||||
#define ESP_ROM_SPIFLASH_QE BIT9
|
||||
|
||||
@@ -113,7 +105,12 @@ typedef enum
|
||||
ESP_ROM_SPIFLASH_DIO_MODE,
|
||||
ESP_ROM_SPIFLASH_DOUT_MODE,
|
||||
ESP_ROM_SPIFLASH_FASTRD_MODE,
|
||||
ESP_ROM_SPIFLASH_SLOWRD_MODE
|
||||
ESP_ROM_SPIFLASH_SLOWRD_MODE,
|
||||
ESP_ROM_SPIFLASH_OPI_STR_MODE,
|
||||
ESP_ROM_SPIFLASH_OPI_DTR_MODE,
|
||||
ESP_ROM_SPIFLASH_OOUT_MODE,
|
||||
ESP_ROM_SPIFLASH_OIO_STR_MODE,
|
||||
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
|
||||
} esp_rom_spiflash_read_mode_t;
|
||||
|
||||
typedef enum
|
||||
|
||||
@@ -0,0 +1,50 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_LEDS is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_ARCH="xtensa"
|
||||
CONFIG_ARCH_BOARD="esp32s3-devkit"
|
||||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
|
||||
CONFIG_ARCH_CHIP="esp32s3"
|
||||
CONFIG_ARCH_CHIP_ESP32S3=y
|
||||
CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_XTENSA=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_ESP32S3_FLASH_FREQ_80M=y
|
||||
CONFIG_ESP32S3_SPIRAM=y
|
||||
CONFIG_ESP32S3_SPIRAM_MODE_OCT=y
|
||||
CONFIG_ESP32S3_UART0=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TESTING_MM=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
@@ -0,0 +1,49 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_LEDS is not set
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
|
||||
CONFIG_ARCH="xtensa"
|
||||
CONFIG_ARCH_BOARD="esp32s3-devkit"
|
||||
CONFIG_ARCH_BOARD_COMMON=y
|
||||
CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y
|
||||
CONFIG_ARCH_CHIP="esp32s3"
|
||||
CONFIG_ARCH_CHIP_ESP32S3=y
|
||||
CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_XTENSA=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_ESP32S3_FLASH_FREQ_80M=y
|
||||
CONFIG_ESP32S3_SPIRAM=y
|
||||
CONFIG_ESP32S3_UART0=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TESTING_MM=y
|
||||
CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
Reference in New Issue
Block a user