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Merged nuttx/nuttx into master - debug and RTC updates

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neil H
2016-06-16 15:55:25 -07:00
parent 7c3cd82f13 4a34540e8f
commit bc67a9e9a4
2257 changed files with 60250 additions and 27525 deletions
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.gitignore
+33 -30
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@@ -1,30 +1,33 @@
.depend
Make.dep
*.o
*.a
*.d
*.i
*~
.swp
.*.swp
core
.gdbinit
cscope.out
/.config
/.config.old
/.version
/Make.defs
/setenv.sh
/setenv.bat
/nuttx
/nuttx.*
/nuttx-*
/_SAVED_APPS_config
/*.map
/*.elf
/*.srec
/*.bin
/*.ihx
/*.hex
/pcode
/tags
.depend
Make.dep
*.o
*.a
*.d
*.i
*~
.swp
.*.swp
core
.gdbinit
cscope.out
/.config
/.config.old
/.version
/Make.defs
/setenv.sh
/setenv.bat
/nuttx
/nuttx.*
/nuttx-*
/_SAVED_APPS_config
/*.map
/*.elf
/*.srec
/*.bin
/*.ihx
/*.hex
/pcode
/tags
/.settings/
/.cproject
/.project
ChangeLog
+166
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@@ -11879,3 +11879,169 @@
mcan_txempty(). From Frank Benkert (2016-06-01).
7.17 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
* drivers/mtd/flash_eraseall.c: Removed. This is no longer used
in the OS and is simply a wrapper around the MDIOC_BULKERASE
IOCTL command. It used to be called (only) from
apps/system/flash_eraseall, but that has been removed because it
violated the OS/application interface -- by calling flash_eraseall().
The old code can be found in the Obsoleted' repository (and a revised
version can be found at apps/fsutils/flash_eraseall) (2016-06-03).
* arch/arm/src/stm32: STM32 Timer Driver: Change calculation of per-
timer pre-scaler value. Add support for all timers (2016-6-03)
* drivers/lcd: Correct conditional compilation in ST7565 driver. From
Pierre-noel Bouteville (2016-6-03)
* arch/arm/src/stm32: Correct conditional compilation in STM32 timer
capture logic. From Pierre-noel Bouteville (2016-6-03)
* arch/arm/src/efm32: Fix EFM32 FLASH conditional compilation. From
Pierre-noel Bouteville (2016-6-03)
* arch/arm/src/lpc43xx: Fix errors in GPIO interrupt logic. From v01d
(phreakuencies) (2016-06-04)
* arch/arm/src/kl and lpc11xx: rename xyz_lowputc to up_putc. Remove
all references to up_lowputc, everywhere (2016-06-04).
* configs/stm32f103-minimum: Add minnsh configuration. From Alan
Carvalho de Assis (2016-06-04).
* arch/arm/src/stm32: Add the up_getc() function to STM32 in order to
support the minnsh configuration. From Alan Carvalho de Assis
(2016-06-04).
* include/sys/boardctl.h: Needs to be usable with C++ files (2016-06-05).
* tools/tesbuild.sh will now build NxWM configurations (2016-06-05).
* arch/arm/src/stm32: In PWM driver, just update duty if frequency is
not changed and PSM started. This removeis glitch or blinking when
only duty is frequently changed. From Pierre-noel Bouteville (2016-06-05).
* arch/arm/src/kinetis: Add a USB device controller driver. Derived from
the pic32mx usb driver, which uses the same usb controller. From kfazz
(2016-06).
* configs/teensy-3.x: Add USB support and a usbnsh configuration. From
kfazz (2016-06).
* arch/arm/src/stm32: Add support for the STM32F105R. From Konstantin
Berezenko (2016-06-06).
* include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
_sa_handler_t. They type void does not work with the IAR toolchain.
From Aleksandr Vyhovanec (2016-06-07).
* arch/arm/src/stm32f7 and include/stm32f7: Added STM32FF76xxx and
STM32FF7xx families. From David Sidrane (2016-06-08).
* Refactoring configs/nucleo-144 sub-directories to support additional
nucleo-144 board. Add support for the Nucleo-F767ZI board. From David
Sidrane (2016-06-08).
* arch/arm/src/kinetis: Add a USB device controller driver for kinetis.
Derived from pic32mx usb driver, which uses the same usb controller.
From kfazz (2016-06-06).
* configs/teensy-3.x: Add USB device support and usbnsh configuration.
From kfazz (2016-06-06.
* arch/arm/src/stm32: Add STM32F105R support. From Konstantin Berezenko
(2016-06-06).
* include/signal.h: Change type of SIG_IGN and related defines to
_sa_handler_t. From Aleksandr Vyhovanec (2016-06-07).
* configs/nucleo-144: Refactored configs/nucleo-144 sub-directories to
support additional nucleo-144 board. Add support for the Nucleo-F767ZI
board. From David Sidrane (2016-06-07).
* arch/arm/src/stm32f7: Add support for STM32FF76xxx and STM32FF7xx
families. From David Sidrane (2016-06-08).
* include/assert.h: Check if NDEBUG is defined. From Paul Alexander
Patience (2016-06-08).
* arch/arm/src/stm32: Fix STM32 DMA code and configuration for STM32F37X
chips. From Marten Svanfeldt (2016-06-08).
* drivers/mtd: Add a driver of IS25xP SPI flash devices. From Marten
Svanfeldt (2016-06-09).
* arch/arm/src/Kconfig and configs/teensy-3.x: Teensy clock fixes. The
High Gain bit in MCG_C1 was preventing teensy from booting except
after a programming session. The second change doesn't appear to
change any functionality, but complies with restrictions in the k20
family reference manual on FEI -> FBE clock transiions. From kfazz
(2016-06-09).
* configs/*/include/board.h: Fix timer input clock definitions. From
David Sidrane (2016-06-09).
* Networking: In both IPv6 and IPv4 incoming logic: (1) Should check
if the packet size is large enough before trying to access the packet
length in the IP header. (2) In the comparison between the IP length
and the full packet length, need to subtract the size of the link
layer header before making the comparison or we will get false
positives (i.e., the packet is really too small) (2016-06-09)
* drivers/mtd: Added driver of IS25xP SPI flash devices. Based on
sst25xx driver. From Marten Svanfeldt (2016-06-09).
* arch/arm/src/kinetis: Teensy clock fixes. The High Gain bit in
MCG_C1 was preventing teensy from booting except after a programming
session. The second change doesn't appear to change any functionality,
but complies with restrictions in the k20 family reference manual on
FEI -> FBE clock transiions. From kfazz (2016-06-09).
* arch/arm/src/stm32: Fix timer input clock definitions. From David
Sidrane (2016-06-09).
* configs/: All configurations that have both CONFIG_NSH_LIBRARY=y and
CONFIG_NET=y must now also have CONFIG_NSH_NETINIT=y (2016-06-09).
* arch/arm/src/kinetis: Kinetis pwm support, based on kl_pwm driver.
From kfazz (2016-06-09).
* net/: In both IPv6 and IPv4 incoming logic: (1) Should check if the
packet size is large enough before trying to access the packet length
in the IP header. (2) In the comparison between the IP length and the
full packet length, need to subtract the size of the link layer header
before making the comparison or we will get false positives (i.e., the
packet is really too small) (2016-06-09).
* arch/srm/src/stm32: Fix compilation errors in debug mode of
stm32_pwm.c. From Konstantin Berezenko (2016-06-09).
* arch/arm/src/kinetis: Support up to 8 channels per timer. From kfazz
(2016-06-09).
* lib/: crc16: fix error. From Paul Alexander Patience (2016-06-10).
* lib/: Add crc64 support. From Paul Alexander Patience (2016-06-10).
* arch/arm/src/kinetis: Added kl_dumpgpio functionality as
kinetis_pindump. From kfazz (2016-06-10).
* arch/arm/src/sam34: Fix some errors in AFEC header file. From
OrbitalFox (2016-06-10).
* arch/arm/include/stm32: Correct the can2 rx irq number for stm32f10xx
chips. From Konstantin Berezenko (2016-06-10).
* drivers/include/input: Button upper half driver: Add definitions
needed for compilation with the poll() interface is not disabled
(2016-06-11).
* Kconfig/, include/debug.h, and many other files: (1) Debug features
are now enabled separately from debug output. CONFIG_DEBUG is gone.
It is replaced with CONFIG_DEBUG_FEATURES. (2) The macros dbg() and
vdbg() have renamed as err() and info(), respectively. This also
applies to all of the variants as well, lldbg(), llvdbg(), XXdbg(),
XXvdbg(), XXlldbg(), and XXllvdbg(). (3) Add a new debug level,
warn() (and all variants vwarn(), llwarn(), etc.). (4) Debug
assertions can now be enabled separately from debug output. (5) You
can now enable subsystem/device driver debug output at different
output levels. For example, CONFIG_DEBUG_FS no longer enables file
system debug output. It enables general file system debug logic and
enables selection of CONFIG_DEBUG_FS_ERROR, CONFIG_DEBUG_FS_WARN,
and CONFIG_DEBUG_FS_INFO (2016-06-12).
* strtoul() and strtoull(): Fix errno settings required by function
definition. Resolved Bitbucket Issue #1. From Sebastien Lorquet
(2016-06-13)
* arch/arm/src/stm32f7: Add SPI driver. DMA not yet supported. From
David Sidrane (2016-06-14).
* configs/nucleo-144: Add test for STM32 F7 SPI. From David Sidrane
(2016-06-14).
* alert(): New debug macro: alert(). This is high priority,
unconditional output and is used to simplify and stanardize crash
error reporting(2016-06-14).
* arch/arm/src/tiva: Bug Fix in tiva_serial.c - UART5, UART6 and UART7
were not being configured as TTYS0 for printing over serial console.
From Shirshak Sengupta (2016-06-14).
* SAMV7: SPI: SPI-Freq. 40MHz; VARSELECT; hw-features
This change adds the following improvements:
- Increase the allowed SPI-Frequency from 20 to 40 MHz.
- Correct and rename the "VARSELECT" option
This option was included in the code as "CONFIG_SPI_VARSELECT" but
nowhere defined in a Kconfig file. The change renames it to
"CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation
according the datasheet of Atmel. In short, this option switches
the processor from "fixed peripheral selection" (single device) to
"variable peripheral selection" (multiple devices on the bus).
- Add a new Function to the interface to control the timing and delays
of the chip according the ChipSelect lines. This function can
control the delay between the assertion of the ChipSelect and the
first bit, between the last bit and the de-assertion of the
ChipSelect and between two ChipSelects. This is needed to tune the
transfer according the specification of the connected devices.
- Add three "hw-features" for the SAMV7, which controls the behavior
of the ChipSelect:
- force CS inactive after transfer: this forces a (short)
de-assertion of the CS after a transfer, even if more data is
available in time
- force CS active after transfer: this forces the CS to stay active
after a transfer, even if the chip runs out of data.
Btw.: this is a prerequisit to make the LASTXFER bit working at all.
- escape LASTXFER: this suppresses the LASTXFER bit at the end of the
next transfer. The "escape"-Flag is reset automatically.
From Frank Benkert (2016-06-14)
Documentation/NuttXCCodingStandard.html
+6 -6
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@@ -162,10 +162,10 @@
Pre-processor Definitions
</li>
<li>
Private Types
Private Types (definitions)
</li>
<li>
Private Function Prototypes
Private Function Prototypes (declarations)
</li>
<li>
Private Data (definitions)
@@ -191,7 +191,7 @@
Pre-processor Definitions
</li>
<li>
Public Types
Public Types (definitions)
</li>
<li>
Public Data (declarations)
@@ -212,12 +212,12 @@
</p>
<p>
<a name="idempotence"><b>Header File Idempotence</b></a>.
C header file must protect against multipleinclusion through the use of macros that &quot;guard&quot; against multiple definitions if the header file is included multiple times.
C header file must protect against multiple inclusion through the use of macros that &quot;guard&quot; against multiple definitions if the header file is included multiple times.
</p>
<ul>
<li>
<p>
Each header file must contain the following pre-processor commands near the beginning of the header file: Between the file header and the &quot;Included Files&quot; block comment.
Each header file must contain the following pre-processor conditional logic near the beginning of the header file: Between the file header and the &quot;Included Files&quot; block comment.
For example,
</p>
<ul><pre>
@@ -248,7 +248,7 @@
<p>
<b>Deoxygen Information</b>.
NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags.
NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.
</p>
<p>
Documentation/NuttxPortingGuide.html
+1 -1
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@@ -802,7 +802,7 @@
<p>
Definitions in the <code>Make.defs</code> file probably depend on some of the
settings in the .<code>config</code> file. For example, the <code>CFLAGS</code> will most likely be
different if <code>CONFIG_DEBUG=y</code>.
different if <code>CONFIG_DEBUG_FEATURES=y</code>.
</p>
<p>
The included <code>tools/Config.mk</code> file contains additional definitions that may
Documentation/UsbTrace.html
+2 -2
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@@ -125,7 +125,7 @@
</p>
<ul>
<li><code>CONFIG_USBDEV_TRACE</code>, or</li>
<li><code>CONFIG_DEBUG and CONFIG_DEBUG_USB</code></li>
<li><code>CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_USB</code></li>
</ul>
<p><b>Log Data Sink</b>.
The logged data itself may go to either (1) an internal circular buffer, or (2) may be provided on the console.
@@ -137,7 +137,7 @@
Here is an example of USB trace output using <code>apps/examples/usbserial</code> for an LPC1768 platform with the following NuttX configuration settings:
</p>
<ul>
<li><code>CONFIG_DEBUG</code>, <code>CONFIG_DEBUG_VERBOSE</code>, <code>CONFIG_USB</code>
<li><code>CONFIG_DEBUG_FEATURES</code>, <code>CONFIG_DEBUG_INFO</code>, <code>CONFIG_USB</code>
<li><code>CONFIG_EXAMPLES_USBSERIAL_TRACEINIT</code>, <code>CONFIG_EXAMPLES_USBSERIAL_TRACECLASS</code>,
<code>CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS</code>, <code>CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER</code>,
<code>CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS</code>
Kconfig
+869 -85
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File diff suppressed because it is too large Load Diff
README.txt
+11 -7
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@@ -960,10 +960,13 @@ Native Windows Build
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
be performed in a Windows console window. Here is a better terminal than the
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
http://code.google.com/p/conemu-maximus5/
https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
Build Tools. The build still relies on some Unix-like commands. I use
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
using the 'Download all' selection. Individual packages can be download
instead if you know what you are doing and want a faster download (No, I
can't tell you which packages you should or should not download).
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
@@ -971,12 +974,13 @@ Native Windows Build
This capability should still be considered a work in progress because:
(1) It has not been verified on all targets and tools, and
(2) it still lacks some of the creature-comforts of the more mature environments.
(1) It has not been verified on all targets and tools, and
(2) it still lacks some of the creature-comforts of the more mature
environments.
There is an alternative to the setenv.sh script available for the Windows
native environment: tools/configure.bat. See tools/README.txt for additional
information.
There is an alternative to the setenv.sh script available for the Windows
native environment: tools/configure.bat. See tools/README.txt for additional
information.
Installing GNUWin32
-------------------
ReleaseNotes
+2 -1
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@@ -5303,7 +5303,8 @@ Additional new features and extended functionality:
can be re-enabled if needed via configuration option.
- NXFFS: Make the start up scan of the media a configuration option.
It just takes to long and is not really necessary! Those rare cases
where the scan was helpful can be fixed using flash_eraseall().
where the scan was helpful can be fixed using MDIOC_BULKERASE IOCTL
command.
* General Drivers:
TODO
+15 -2
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@@ -1,4 +1,4 @@
NuttX TODO List (Last updated May 28, 2016)
NuttX TODO List (Last updated June 6, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -23,7 +23,7 @@ nuttx/:
(11) Libraries (libc/, libm/)
(11) File system/Generic drivers (fs/, drivers/)
(8) Graphics subsystem (graphics/)
(1) Build system / Toolchains
(2) Build system / Toolchains
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
@@ -1601,6 +1601,19 @@ o Build system
Status: Open
Priority: Low.
Title: NATIVE WINDOWS BUILD BROKEN
Description: The way that apps/ no generates Kmenu files depends on changes added
to apps/tools/mkkconfig.sh. Similar changes need to be made to
apps/tools/mkkconfig.bat to restore the Windows Native build.
UPDATE: The mkkconfig.bat script has been updated and appears to work.
A native build has still not been attempted and there could likely be
issues the carriage returns in Kconfig files. There are also some
issues the interpreters/ficl and bas directories during 'make menuconfig'
that still need to be investigated.
Status: Open
Priority: Low, since I am not aware of anyone using the Windows Native build.
But, of course, very high if you want to use it.
o Other drivers (drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^
arch/arm/Kconfig
+1 -1
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@@ -588,7 +588,7 @@ config ARCH_ROMPGTABLE
config DEBUG_HARDFAULT
bool "Verbose Hard-Fault Debug"
default n
depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
depends on DEBUG_FEATURES && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
---help---
Enables verbose debug output when a hard fault is occurs. This verbose
output is sometimes helpful when debugging difficult hard fault problems,
arch/arm/include/efm32/irq.h
+1 -1
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@@ -60,7 +60,7 @@
/* Processor Exceptions (vectors 0-15) */
#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define EFM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/kinetis/irq.h
+1 -1
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@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/kl/irq.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KL_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/lpc11xx/irq.h
+1 -1
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@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/lpc17xx/irq.h
+1 -1
View File
@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/lpc43xx/irq.h
+1 -1
View File
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC43_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/nuc1xx/irq.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define NUC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/sam34/irq.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/samdl/irq.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/samv7/irq.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/stm32/chip.h
+38 -1
View File
@@ -903,6 +903,43 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -2430,7 +2467,7 @@
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
defined(CONFIG_ARCH_CHIP_STM32F469B) || \
defined(CONFIG_ARCH_CHIP_STM32F469N)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# endif
arch/arm/include/stm32/irq.h
+1 -1
View File
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/stm32/stm32f10xxx_irq.h
+1 -1
View File
@@ -199,7 +199,7 @@
# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */
# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */
# define STM32_IRQ_CAN2RX0 (70) /* 64: CAN2 RX0 interrupts */
# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */
# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
arch/arm/include/stm32f7/chip.h
+235 -62
View File
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/stm32f7/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -45,99 +45,272 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
* STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
*
* ----------- ---------------- ----- -------- ------------ --------
* PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
* ----------- ---------------- ----- -------- ------------ --------
* STM32F745Vx LQFP100 82 4/3 16 No
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
* STM32F745Bx LQFP208 168 6/3 24 No
* STM32F745Nx TFBGA216 68 6/3 24 No
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
* SPI ADC LCD
* PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
* STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
*
* STM32F746Vx LQFP100 82 4/3 16 Yes
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
* STM32F746Bx LQFP208 168 6/3 24 Yes
* STM32F746Nx TFBGA216 168 6/3 24 Yes
* STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
* STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
*
* STM32F756Vx LQFP100 82 4/3 16 Yes
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
* STM32F756Bx LQFP208 168 6/3 24 Yes
* STM32F756Nx TFBGA216 168 6/3 24 Yes
* ----------- ---------------- ----- -------- ------------ --------
* STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
* STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
* STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
*
* STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
*
* STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
*
* STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
*
* STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
* STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
*
* STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
*
* STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
*
* STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
*
* STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
* STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
* ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
*
* Parts STM32F74xxE have 512Kb of FLASH
* Parts STM32F74xxG have 1024Kb of FLASH
* Parts STM32F74xxI have 2048Kb of FLASH
*
* The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
* with CONFIG_STM32F7_FLASH_OVERRIDE_x
*
* The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
* selection.
*/
#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
defined(CONFIG_ARCH_CHIP_STM32F756)
#if defined(CONFIG_ARCH_CHIP_STM32F745)
# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
#elif defined(CONFIG_ARCH_CHIP_STM32F746)
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
defined(CONFIG_ARCH_CHIP_STM32F765II) || \
defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
defined(CONFIG_ARCH_CHIP_STM32F767II) || \
defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
defined(CONFIG_ARCH_CHIP_STM32F769II) || \
defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
defined(CONFIG_ARCH_CHIP_STM32F777II) || \
defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
defined(CONFIG_ARCH_CHIP_STM32F779II) || \
defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
defined(CONFIG_ARCH_CHIP_STM32F779AI)
#else
# error STM32 F7 chip not identified
#endif
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
/* Size SRAM */
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
# else
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# else
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# else
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# else
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#else
# error STM32 F7 chip Family not identified
#endif
/* Common to all Family members */
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32F7_NI2C 4 /* I2C1-4 */
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
# define STM32F7_NCAN 2 /* CAN1-2 */
# define STM32F7_NSAI 2 /* SAI1-2 */
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
# define STM32F7_NSDMMC 1 /* SDMMC interface */
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
# define STM32F7_NDMA 2 /* DMA1-2 */
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32F7_NCRC 1 /* CRC */
/* TBD FPU Configuration */
#if defined(CONFIG_ARCH_HAVE_FPU)
#else
# error STM32 F7 chip not identified
#endif
#if defined(CONFIG_ARCH_HAVE_DPFPU)
#else
#endif
/* Diversification based on Family and package */
#if defined(CONFIG_STM32F7_HAVE_FSMC)
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
#else
# define STM32F7_NFSMC 0 /* No FSMC memory controller */
#endif
#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
#if defined(CONFIG_STM32F7_HAVE_RNG)
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
#else
# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
#endif
#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
#else
# define STM32F7_NSPI 4 /* SPI1-4 V series */
#endif
#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
#else
# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
#endif
#if defined(CONFIG_STM32F7_HAVE_CAN3)
# define STM32F7_NCAN 3 /* CAN1-3 */
#else
# define STM32F7_NCAN 2 /* CAN1-2 */
#endif
#if defined(CONFIG_STM32F7_HAVE_DCMI)
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
#endif
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
#else
# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
#endif
#if defined (CONFIG_STM32F7_HAVE_LTDC)
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#else
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
#endif
#if defined(CONFIG_STM32F7_HAVE_DMA2D)
# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
#else
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
#endif
#if defined(CONFIG_STM32F7_HAVE_JPEG)
#define STM32F7_NJPEG 1 /* One JPEG Converter */
#else
#define STM32F7_NJPEG 0 /* No JPEG Converter */
#endif
#if defined(CONFIG_STM32F7_HAVE_CRYP)
#define STM32F7_NCRYP 1 /* One CRYP engine */
#else
#define STM32F7_NCRYP 0 /* No CRYP engine */
#endif
#if defined(CONFIG_STM32F7_HAVE_HASH)
#define STM32F7_NHASH 1 /* One HASH engine */
#else
#define STM32F7_NHASH 0 /* No HASH engine */
#endif
#if defined(CONFIG_STM32F7_HAVE_DFSDM)
#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
#else
#define STM32F7_NDFSDM 0 /* No Digital filters */
#endif
/* NVIC priority levels *************************************************************/
arch/arm/include/stm32f7/irq.h
+3 -1
View File
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
@@ -78,6 +78,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
# include <arch/stm32f7/stm32f76xx77xx_irq.h>
#else
# error "Unsupported STM32 F7 chip"
#endif
arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
+215
View File
@@ -0,0 +1,215 @@
/****************************************************************************************************
* arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
#define NR_INTERRUPTS 110
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
arch/arm/include/stm32l4/irq.h
+1 -1
View File
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/include/tiva/irq.h
+1 -1
View File
@@ -162,7 +162,7 @@
/* Processor Exceptions (vectors 0-15) */
#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
arch/arm/src/a1x/a1x_irq.c
+34 -32
View File
@@ -77,7 +77,7 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ)
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
@@ -85,40 +85,42 @@ static void a1x_dumpintc(const char *msg, int irq)
/* Dump some relevant ARMv7 register contents */
flags = enter_critical_section();
lldbg("ARMv7 (%s, irq=%d):\n", msg, irq);
lldbg(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
irqinfo("ARMv7 (%s, irq=%d):\n", msg, irq);
irqinfo(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
/* Dump all of the (readable) INTC register contents */
lldbg("INTC (%s, irq=%d):\n", msg, irq);
lldbg(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
lldbg(" IRQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
getreg32(A1X_INTC_IRQ_PEND2));
lldbg(" FIQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
getreg32(A1X_INTC_FIQ_PEND2));
lldbg(" SEL: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
getreg32(A1X_INTC_IRQ_SEL2));
lldbg(" EN: %08x %08x %08x\n",
getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
getreg32(A1X_INTC_EN2));
lldbg(" MASK: %08x %08x %08x\n",
getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
getreg32(A1X_INTC_MASK2));
lldbg(" RESP: %08x %08x %08x\n",
getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
getreg32(A1X_INTC_RESP2));
lldbg(" FF: %08x %08x %08x\n",
getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
getreg32(A1X_INTC_FF2));
lldbg(" PRIO: %08x %08x %08x %08x %08x\n",
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
irqinfo("INTC (%s, irq=%d):\n", msg, irq);
irqinfo(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
irqinfo(" IRQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
getreg32(A1X_INTC_IRQ_PEND2));
irqinfo(" FIQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
getreg32(A1X_INTC_FIQ_PEND2));
irqinfo(" SEL: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
getreg32(A1X_INTC_IRQ_SEL2));
irqinfo(" EN: %08x %08x %08x\n",
getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
getreg32(A1X_INTC_EN2));
irqinfo(" MASK: %08x %08x %08x\n",
getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
getreg32(A1X_INTC_MASK2));
irqinfo(" RESP: %08x %08x %08x\n",
getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
getreg32(A1X_INTC_RESP2));
irqinfo(" FF: %08x %08x %08x\n",
getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
getreg32(A1X_INTC_FF2));
irqinfo(" PRIO: %08x %08x %08x %08x %08x\n",
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
leave_critical_section(flags);
}
#else
arch/arm/src/a1x/a1x_serial.c
+3 -3
View File
@@ -1156,7 +1156,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, A1X_UART_MSR_OFFSET);
vdbg("MSR: %02x\n", status);
_info("MSR: %02x\n", status);
break;
}
@@ -1167,7 +1167,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, A1X_UART_LSR_OFFSET);
vdbg("LSR: %02x\n", status);
_info("LSR: %02x\n", status);
break;
}
@@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
default:
{
lldbg("Unexpected IIR: %02x\n", status);
_llerr("Unexpected IIR: %02x\n", status);
break;
}
}
arch/arm/src/arm/up_assert.c
+23 -51
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_assert.c
*
* Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2010, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdarg.h>
#include <stdint.h>
#include <stdlib.h>
@@ -77,23 +66,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
/* The following is just intended to keep some ugliness out of the mainline
* code. We are going to print the task name if:
*
* CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
* (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
* defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
*/
#undef CONFIG_PRINT_TASKNAME
#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
# define CONFIG_PRINT_TASKNAME 1
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -127,7 +99,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
_alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -154,12 +126,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
_alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
_alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -228,12 +200,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
lldbg("sp: %08x\n", sp);
lldbg("IRQ stack:\n");
lldbg(" base: %08x\n", istackbase);
lldbg(" size: %08x\n", istacksize);
_alert("sp: %08x\n", sp);
_alert("IRQ stack:\n");
_alert(" base: %08x\n", istackbase);
_alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_intstack());
_alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -251,24 +223,24 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
lldbg("sp: %08x\n", sp);
_alert("sp: %08x\n", sp);
}
/* Show user stack info */
lldbg("User stack:\n");
lldbg(" base: %08x\n", ustackbase);
lldbg(" size: %08x\n", ustacksize);
_alert("User stack:\n");
_alert(" base: %08x\n", ustackbase);
_alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
_alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#else
lldbg("sp: %08x\n", sp);
lldbg("stack base: %08x\n", ustackbase);
lldbg("stack size: %08x\n", ustacksize);
_alert("sp: %08x\n", sp);
_alert("stack base: %08x\n", ustackbase);
_alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
_alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
#endif
@@ -279,7 +251,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
lldbg("ERROR: Stack pointer is not within allocated stack\n");
_alert("ERROR: Stack pointer is not within allocated stack\n");
#endif
}
else
@@ -339,17 +311,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
#if CONFIG_TASK_NAME_SIZE > 0
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
_alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
arch/arm/src/arm/up_dataabort.c
+5 -29
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_dataabort.c
*
* Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <debug.h>
@@ -63,18 +52,6 @@
# include "arm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -112,7 +89,6 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* for register dumps and possibly context switching.
*/
savestate = (uint32_t *)CURRENT_REGS;
#endif
CURRENT_REGS = regs;
@@ -131,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* fatal error.
*/
pglldbg("FSR: %08x FAR: %08x\n", fsr, far);
pgllerr("FSR: %08x FAR: %08x\n", fsr, far);
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -142,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;
@@ -180,7 +156,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
segfault:
#endif
lldbg("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
_alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
PANIC();
}
@@ -196,7 +172,7 @@ void up_dataabort(uint32_t *regs)
/* Crash -- possibly showing diagnost debug information. */
lldbg("Data abort. PC: %08x\n", regs[REG_PC]);
_alert("Data abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
arch/arm/src/arm/up_elf.c
+12 -12
View File
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if ((ehdr->e_entry & 3) != 0)
{
bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
return -ENOEXEC
}
@@ -172,7 +172,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -185,7 +185,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -201,7 +201,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -210,7 +210,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -225,7 +225,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -236,7 +236,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -256,7 +256,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
break;
default:
bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -266,6 +266,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
bdbg("RELA relocation not supported\n");
berr("RELA relocation not supported\n");
return -ENOSYS;
}
arch/arm/src/arm/up_head.S
+1 -1
View File
@@ -208,7 +208,7 @@
/* This macro will modify r0, r1, r2 and r14 */
#ifdef CONFIG_DEBUG
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
arch/arm/src/arm/up_nommuhead.S
+2 -2
View File
@@ -49,7 +49,7 @@
/* This macro will modify r0, r1, r2 and r14 */
#ifdef CONFIG_DEBUG
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
@@ -115,7 +115,7 @@ __start:
bl up_earlyserialinit
#endif
#ifdef CONFIG_DEBUG
#ifdef CONFIG_DEBUG_FEATURES
mov r0, #'C'
bl up_putc
mov r0, #'\n'
arch/arm/src/arm/up_prefetchabort.c
+3 -14
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_prefetchabort.c
*
* Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <debug.h>
@@ -110,7 +99,7 @@ void up_prefetchabort(uint32_t *regs)
* virtual addresses.
*/
pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
pgllerr("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
@@ -148,7 +137,7 @@ void up_prefetchabort(uint32_t *regs)
else
#endif
{
lldbg("Prefetch abort. PC: %08x\n", regs[REG_PC]);
_alert("Prefetch abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
}
arch/arm/src/arm/up_releasepending.c
+1 -1
View File
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
slldbg("From TCB=%p\n", rtcb);
sllerr("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
arch/arm/src/arm/up_reprioritizertr.c
+1 -1
View File
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
slldbg("TCB=%p PRI=%d\n", tcb, priority);
sllerr("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
arch/arm/src/arm/up_schedulesigaction.c
+2 -2
View File
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* being delivered to the currently executing task.
*/
sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
arch/arm/src/arm/up_sigdeliver.c
+2 -2
View File
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -126,7 +126,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
sdbg("Resuming\n");
serr("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
arch/arm/src/arm/up_syscall.c
+4 -31
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_syscall.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <debug.h>
@@ -58,22 +47,6 @@
#include "up_arch.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* vectors
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -82,8 +55,8 @@
* Name: up_syscall
*
* Description:
* SWI interrupts will vection here with insn=the SWI
* instruction and xcp=the interrupt context
* SWI interrupts will vector here with insn=the SWI instruction and
* xcp=the interrupt context
*
* The handler may get the SWI number be de-referencing
* the return address saved in the xcp and decoding
@@ -93,7 +66,7 @@
void up_syscall(uint32_t *regs)
{
lldbg("Syscall from 0x%x\n", regs[REG_PC]);
_alert("Syscall from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
arch/arm/src/arm/up_undefinedinsn.c
+2 -25
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_undefinedinsn.c
*
* Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <assert.h>
#include <debug.h>
@@ -58,18 +47,6 @@
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,7 +57,7 @@
void up_undefinedinsn(uint32_t *regs)
{
lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
_alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
arch/arm/src/armv6-m/nvic.h
+2 -1
View File
@@ -41,6 +41,7 @@
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
/****************************************************************************************************
* Pre-processor Definitions
@@ -386,7 +387,7 @@ extern "C"
*
****************************************************************************************************/
#ifdef CONFIG_DEBUG
#ifdef CONFIG_DEBUG_FEATURES
void up_dumpnvic(FAR const char *msg);
#else
# define up_dumpnvic(m)
arch/arm/src/armv6-m/up_assert.c
+28 -56
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_assert.c
*
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2015, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <stdlib.h>
#include <assert.h>
@@ -76,23 +65,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
/* The following is just intended to keep some ugliness out of the mainline
* code. We are going to print the task name if:
*
* CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
* (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
* defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
*/
#undef CONFIG_PRINT_TASKNAME
#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
# define CONFIG_PRINT_TASKNAME 1
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -126,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
_alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -144,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
#ifdef CONFIG_PRINT_TASKNAME
lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
#if CONFIG_TASK_NAME_SIZE > 0
_alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
lldbg("PID: %d Stack Used=%lu of %lu\n",
_alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,22 +156,22 @@ static inline void up_registerdump(void)
{
/* Yes.. dump the interrupt registers */
lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
_alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
_alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
lldbg("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
_alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
lldbg("xPSR: %08x PRIMASK: %08x\n",
_alert("xPSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
@@ -270,12 +242,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
lldbg("sp: %08x\n", sp);
lldbg("IRQ stack:\n");
lldbg(" base: %08x\n", istackbase);
lldbg(" size: %08x\n", istacksize);
_alert("sp: %08x\n", sp);
_alert("IRQ stack:\n");
_alert(" base: %08x\n", istackbase);
_alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_intstack());
_alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -297,14 +269,14 @@ static void up_dumpstate(void)
if (CURRENT_REGS)
{
sp = CURRENT_REGS[REG_R13];
lldbg("sp: %08x\n", sp);
_alert("sp: %08x\n", sp);
}
lldbg("User stack:\n");
lldbg(" base: %08x\n", ustackbase);
lldbg(" size: %08x\n", ustacksize);
_alert("User stack:\n");
_alert(" base: %08x\n", ustackbase);
_alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
_alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -317,11 +289,11 @@ static void up_dumpstate(void)
}
#else
lldbg("sp: %08x\n", sp);
lldbg("stack base: %08x\n", ustackbase);
lldbg("stack size: %08x\n", ustacksize);
_alert("sp: %08x\n", sp);
_alert("stack base: %08x\n", ustackbase);
_alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
_alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -330,7 +302,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
lldbg("ERROR: Stack pointer is not within allocated stack\n");
_alert("ERROR: Stack pointer is not within allocated stack\n");
}
else
{
@@ -394,17 +366,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
#if CONFIG_TASK_NAME_SIZE > 0
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
_alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
arch/arm/src/armv6-m/up_dumpnvic.c
+21 -31
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_dumpnvic.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -48,19 +48,7 @@
#include "nvic.h"
#ifdef CONFIG_DEBUG
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Public Functions
@@ -76,6 +64,7 @@
void up_dumpnvic(FAR const char *msg)
{
#ifdef CONFIG_DEBUG_INFO
irqstate_t flags;
int i;
@@ -83,29 +72,30 @@ void up_dumpnvic(FAR const char *msg)
flags = enter_critical_section();
lldbg("NVIC: %s\n", msg);
lldbg(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
_llinfo("NVIC: %s\n", msg);
_llinfo(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
for (i = 0 ; i < 8; i += 4)
{
lldbg(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
i, getreg32(ARMV6M_NVIC_IPR(i)),
i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
_llinfo(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
i, getreg32(ARMV6M_NVIC_IPR(i)),
i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
}
lldbg("SYSCON:\n");
lldbg(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
lldbg(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
getreg32(ARMV6M_SYSCON_SHPR3));
_llinfo("SYSCON:\n");
_llinfo(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
_llinfo(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
#endif
}
#endif /* CONFIG_DEBUG */
#endif /* CONFIG_DEBUG_FEATURES */
arch/arm/src/armv6-m/up_elf.c
+19 -19
View File
@@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_machine != EM_ARM)
{
bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
@@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
@@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
@@ -168,7 +168,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
binfo("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -181,7 +181,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -197,7 +197,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
@@ -245,7 +245,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -279,7 +279,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
binfo(" S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
S, J1, J2, (long)offset, offset + sym->st_value - addr);
offset += sym->st_value - addr;
@@ -290,7 +290,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
{
bdbg(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
berr(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -300,7 +300,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
{
bdbg(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
berr(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
@@ -320,14 +320,14 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
binfo(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
}
break;
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
@@ -342,7 +342,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
@@ -353,7 +353,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
binfo("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
@@ -408,7 +408,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
binfo("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
sym, (long)sym->st_value);
@@ -425,7 +425,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
/* And perform the relocation */
bvdbg(" offset=%08lx branch target=%08lx\n",
binfo(" offset=%08lx branch target=%08lx\n",
(long)offset, offset + sym->st_value);
offset += sym->st_value;
@@ -445,13 +445,13 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff));
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" insn [%04x %04x]\n",
binfo(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);
}
break;
default:
bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
@@ -461,6 +461,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
bdbg("RELA relocation not supported\n");
berr("RELA relocation not supported\n");
return -ENOSYS;
}
arch/arm/src/armv6-m/up_hardfault.c
+11 -23
View File
@@ -55,25 +55,13 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_HARDFAULT
# define hfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
# define hferr(format, ...) _llerr(format, ##__VA_ARGS__)
#else
# define hfdbg(x...)
# define hferr(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -118,7 +106,7 @@ int up_hardfault(int irq, FAR void *context)
/* Fetch the instruction that caused the Hard fault */
uint16_t insn = *pc;
hfdbg(" PC: %p INSN: %04x\n", pc, insn);
hferr(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
@@ -126,7 +114,7 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
hfdbg("Forward SVCall\n");
hferr("Forward SVCall\n");
return up_svcall(irq, context);
}
}
@@ -134,22 +122,22 @@ int up_hardfault(int irq, FAR void *context)
#if defined(CONFIG_DEBUG_HARDFAULT)
/* Dump some hard fault info */
hfdbg("\nHard Fault:\n");
hfdbg(" IRQ: %d regs: %p\n", irq, regs);
hfdbg(" PRIMASK: %08x IPSR: %08x\n",
hferr("\nHard Fault:\n");
hferr(" IRQ: %d regs: %p\n", irq, regs);
hferr(" PRIMASK: %08x IPSR: %08x\n",
getprimask(), getipsr());
hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
hferr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
hferr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
hferr(" xPSR: %08x PRIMASK: %08x (saved)\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
(void)up_irq_save();
lldbg("PANIC!!! Hard fault\n");
_llerr("PANIC!!! Hard fault\n");
PANIC();
return OK; /* Won't get here */
}
arch/arm/src/armv6-m/up_releasepending.c
+1 -1
View File
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
slldbg("From TCB=%p\n", rtcb);
sllerr("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
arch/arm/src/armv6-m/up_reprioritizertr.c
+1 -1
View File
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
slldbg("TCB=%p PRI=%d\n", tcb, priority);
sllerr("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
arch/arm/src/armv6-m/up_schedulesigaction.c
+2 -2
View File
@@ -107,7 +107,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{

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