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Fix all occurrences of "the the" in documentation and comments

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This commit is contained in:
Gregory Nutt
2013-08-27 09:40:19 -06:00
parent c5802dd5a0
commit bc46b447dc
148 changed files with 322 additions and 320 deletions
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ChangeLog
+13 -11
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@@ -2576,7 +2576,7 @@
* arch/arm/src/stm32/stm32f*0xx_rcc.c: In order to use CAN2, both CAN1 and
CAN2 clocking must be enabled.
* arch/mips/src/pic32mx/picm32mx-usbdev.c: Several stall-related fixes so that
the USB device driver can used the the mass storage class (which does a LOT
the USB device driver can used the mass storage class (which does a LOT
of stalling as part of its normal protocol). The PIC32 USB Mass Storage
device is, however, still non-functional when debug is OFF.
* include/nuttx/fs: Move all file-system related files from include/nuttx to
@@ -3288,7 +3288,7 @@
* arch/*/src/Makefile: Remove some old logic that was kicked off
when CONFIG_BOOT_RUNFROMFLASH=y. The old logic used to use
objcopy to move sections. Newer logic changes the load position
of sections in the the linker script. As far as I can tell, there
of sections in the linker script. As far as I can tell, there
is nothing in the source tree now that depends on the old way of
doing things (if I am wrong, they will need a change to the linker
script).
@@ -3406,7 +3406,7 @@
touchscreen driver).
* configs/shenzhou/src/up_touchscreen.c: Add ADS7843E touchscreen
support for the Shenzhou board. The initial check-in is untested
and basically a clone of the the touchscreen support for the SAM-3U.
and basically a clone of the touchscreen support for the SAM-3U.
* tools/cfgparser.c: There are some NxWidget configuration
settings that must be de-quoted.
* arch/arm/src/stm32/Kconfig: There is no SPI4. Some platforms
@@ -3567,7 +3567,7 @@
* net/netdev_ioctl.c: Add interface state flags and ioctl calls
to bring network interfaces up and down (from Darcy Gong).
* config/stm32f4discovery: Enable C++ exceptions. Now the entire
apps/examples/cxxtest works -- meaning the the uClibc++ is
apps/examples/cxxtest works -- meaning that the uClibc++ is
complete and verified for the STM32 platform.
6.24 2012-12-20 Gregory Nutt <gnutt@nuttx.org>
@@ -3636,7 +3636,7 @@
CONFIG_WINDOWS_NATIVE. This will allow me to eliminate a lot of
conditional logic elsewhere.
* nuttx/graphics: One a mouse button is pressed, continue to report all
mouse button events to the first window that received the the initial
mouse button events to the first window that received the initial
button down event, even if the mouse attempts to drag outside the
window. From Petteri Aimonen.
* nuttx/graphics/nxmu/nx_block.c: One more fix to the NX block message
@@ -3753,7 +3753,7 @@
Also from Petteri Aimonen.
* include/stdbool.h: Can now be disabled for C++ files if CONFIG_C99_BOOL8 is
defined. CONFIG_C99_BOOL8 indicates (1) that the sizeof(_Bool) is one in both
C and C++, and (2) the the C compiler is C99 and supports the _Bool intrinsic
C and C++, and (2) the C compiler is C99 and supports the _Bool intrinsic
type. Requested by Freddie Chopin.
* include/stdlib/lib_rand.c: Various additional changes so that the integer
value zero can be returned. Requested by Freddie Chopin.
@@ -4435,7 +4435,7 @@
and simpler. However, the C code intermixed with SVC calls was
not properly preserving registers. The more complex, assembly
language version does not suffer from these issues. I believe
the the kernel build can now be called "feature complete"
the kernel build can now be called "feature complete"
(2013-03-23).
* binfmt/binfmt_execmodule.c: Here is a place where I forget
to update the call to sched_releasetcb() to pass the thread
@@ -4509,7 +4509,7 @@
support for the touschscreen on the WaveShare LCD (2013-4-01).
* configs/several: There were already some functions called
lpc17_sspinitialize(). So they had to be renamed (2013-4-01).
* arch/arm/src/lpc17xx/lpc17_ssp.c: Adapted to work the the LPC178x
* arch/arm/src/lpc17xx/lpc17_ssp.c: Adapted to work with the LPC178x
family (2013-4-01).
* arch/arm/src/lpc17xx/lpc17_gpio.c/.h: Separate LPC176x and LPC178x
logic into separate files. The logic is diverging to much to
@@ -4725,7 +4725,7 @@
* nuttx/syscall/syscall.csv: Type of first parameter of on_exit() is
wrong. Reported by Ken Pettit (2013-5-17).
* configs/mikroe-stm32f4/kernel/, kostest/ and scripts/: Add kernel build
support and kernel mode OS test example for the the MikroElektronkia
support and kernel mode OS test example for the MikroElektronkia
MultiMedia STM32 M4 board. From Ken Pettit (2013-5-17).
* arch/arm/include/stm32/chip.h and arch/arm/src/stme32/chip/stm32l15xxx_pinmap.h:
Beginning of support for the STM32L15X family (2013-5-18).
@@ -4982,7 +4982,7 @@
so that is it compatible with the SPI drivers of other MCUs
(2013-6-16).
* configs/sam3u-ek/src/up_touchscreen.c and configs/sam4l-xplained/src/sam_mmcsd.c:
Changed needed because of the above change the the SAM3/4 SPI
Changed needed because of the above change to the SAM3/4 SPI
interface (2013-6-16).
* drivers/input/ads7843e.c: Remove the wait for the touchscreen busy
bit. I don't see the busy bit changing on the SAM3U-EK board. But
@@ -5211,7 +5211,7 @@
* The sama5d3x-ek/hello now runs correctly (2013-7-28).
* configs/sama5d3x-ek/ostest/: This configuration has been modified
to run out NOR flash. More work is still needed to reconfigure the
SMC so the the NOR flash can work with the high clock (2013-7-28).
SMC so that the NOR flash can work with the high clock (2013-7-28).
* arch/arm/src/sama5/sam_clockconfig.c/h and
configs/sama5d3x-ek/src/sam_norflash.c: Add a file structure that
will (eventually) support reconfiguration of NOR flash when NuttX
@@ -5467,4 +5467,6 @@
max packetsize. High speed needs 64 bytes, low speed needs 8 bytes,
and full speed can handle almost any size (2013-8-26).
* arch/arm: Add hooks for Cortex-A8. Not much more yet (2013-8-27).
* Lots of files: Fix all occurrents of "the the" in documentation and
comments (2013-8-27).
Documentation/NXGraphicsSubsystem.html
+4 -4
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@@ -1709,7 +1709,7 @@ void nx_getrectangle(NXWINDOW hwnd, FAR const struct nxgl_rect_s *rect,
<dt><code>dest</code>
<dd>The location to copy the memory region
<dt><code>deststride</code>
<dd>The width, in bytes, the the dest memory
<dd>The width, in bytes, of the dest memory
</dl></ul>
</p>
<p>
@@ -2335,7 +2335,7 @@ void nxtk_getwindow(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
<dt><code>dest</code>
<dd>The location to copy the memory region
<dt><code>deststride</code>
<dd>The width, in bytes, the the dest memory
<dd>The width, in bytes, of the dest memory
</dl>
</p>
<p>
@@ -2689,7 +2689,7 @@ int nxtk_gettoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
<dt><code>dest</code>
<dd>TThe location to copy the memory region.
<dt><code>deststride</code>
<dd>The width, in bytes, the the dest memory.
<dd>The width, in bytes, of the dest memory.
</dl>
</p>
<p>
@@ -3522,7 +3522,7 @@ enum nx_fontid_e
<li>
<p>
<b><code>nuttx/graphics/Makefile</code></b>.
This file needs logic to auto-generate a C source file from the header file that you generated with the the <i>bdf-converter</i> program.
This file needs logic to auto-generate a C source file from the header file that you generated with the <i>bdf-converter</i> program.
Notice <code>NXFONTS_FONTID=2</code>; this must be set to the same font ID value that you defined in the <code>include/nuttx/nx/nxfonts.h</code> file.
</p>
<ul><pre>
Documentation/NfsHowto.html
+1 -1
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@@ -249,7 +249,7 @@ nfsmount &lt;server-address&gt; &lt;mount-point&gt; &lt;remote-path&gt;
</p>
<p>
<b>Example</b>.
Suppose the the NFS server has been configured to export the directory <code>/export/shared</code>.
Suppose that the NFS server has been configured to export the directory <code>/export/shared</code>.
The the following command would mount that file system (assuming that the target also has privileges to mount the file system).
</p>
<ul><pre>
Documentation/NuttShell.html
+1 -1
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@@ -1043,7 +1043,7 @@ nsh> df
nsh>
</pre></ul>
<p>
If <code>CONFIG_NSH_CMDOPT_DF_H</code> is defined in the NuttX configuration, the the <code>df</code> will also support an option <code>-h</code> which may be used to show the the volume information in <i>human readable</i> format.
If <code>CONFIG_NSH_CMDOPT_DF_H</code> is defined in the NuttX configuration, then the <code>df</code> will also support an option <code>-h</code> which may be used to show the volume information in <i>human readable</i> format.
</p>
<table width ="100%">
Documentation/NuttX.html
+4 -4
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@@ -2612,7 +2612,7 @@ nsh>
Configurations available include include a verified NuttShell (NSH) configuration
(see the <a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH User Guide</a>).
The NSH configuration supports the Nucleus2G's microSD slot and additional configurations
are available to exercise the the USB serial and USB mass storage devices.
are available to exercise the USB serial and USB mass storage devices.
However, due to some technical reasons, neither the SPI nor the USB device drivers are fully verified.
(Although they have since been verfiied on other platforms; this needs to be revisited on the Nucleus2G).
</p>
@@ -2660,7 +2660,7 @@ nsh>
for USB serial deive and USB storage devices examples, and for the USB host HID keyboard driver.
Support for the USB host mass storage device can optionally be configured for the NSH example.
A driver for the <i>Nokia 6100 LCD</i> and an NX graphics configuration for the Olimex LPC1766-STK have been added.
However, neither the LCD driver nor the NX configuration have been verified as of the the NuttX-5.17 release.
However, neither the LCD driver nor the NX configuration have been verified as of the NuttX-5.17 release.
</p>
</li>
<li>
@@ -4219,7 +4219,7 @@ Other memory:
so that is it compatible with the SPI drivers of other MCUs
(2013-6-16).
* configs/sam3u-ek/src/up_touchscreen.c and configs/sam4l-xplained/src/sam_mmcsd.c:
Changed needed because of the above change the the SAM3/4 SPI
Changed needed because of the above change to the SAM3/4 SPI
interface (2013-6-16).
* drivers/input/ads7843e.c: Remove the wait for the touchscreen busy
bit. I don't see the busy bit changing on the SAM3U-EK board. But
@@ -4448,7 +4448,7 @@ Other memory:
* The sama5d3x-ek/hello now runs correctly (2013-7-28).
* configs/sama5d3x-ek/ostest/: This configuration has been modified
to run out NOR flash. More work is still needed to reconfigure the
SMC so the the NOR flash can work with the high clock (2013-7-28).
SMC so that the NOR flash can work with the high clock (2013-7-28).
* arch/arm/src/sama5/sam_clockconfig.c/h and
configs/sama5d3x-ek/src/sam_norflash.c: Add a file structure that
will (eventually) support reconfiguration of NOR flash when NuttX
Documentation/NuttXDemandPaging.html
+1 -1
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@@ -232,7 +232,7 @@
<li>
<b>Sanity checking</b>.
This function will ASSERT if the currently executing task is the page fill worker thread.
The page fill worker thread is how the the page fault is resolved and all logic associated with the page fill worker
The page fill worker thread is how the page fault is resolved and all logic associated with the page fill worker
must be &quot;<a href="#MemoryOrg">locked</a>&quot; and always present in memory.
</li>
<li>
Documentation/NuttxPortingGuide.html
+4 -4
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@@ -3513,7 +3513,7 @@ extern void up_ledoff(int led);
<p>
Each USB host class driver includes an intialization entry point that is called from the
application at initialization time.
This driver calls <code>usbhost_registerclass()</code> during this initialization in order to makes itself available in the event the the device that it supports is connected.
This driver calls <code>usbhost_registerclass()</code> during this initialization in order to makes itself available in the event the device that it supports is connected.
</p>
<p>
<b>Examples</b>:
@@ -3559,7 +3559,7 @@ extern void up_ledoff(int led);
<li>
<p>
<b><code>include/nuttx/usb/usbdev_trace.h</code></b>.
Declarations needed to work the the NuttX USB device driver trace capability.
Declarations needed to work with the NuttX USB device driver trace capability.
That USB trace capability is detailed in <a href="UsbTrace.html">separate document</a>.
</p>
</li>
@@ -4197,13 +4197,13 @@ void pm_activity(int priority);
enum pm_state_e pm_checkstate(void);
</pre></ul>
<p><b>Description:</b>
This function is called from the MCU-specific IDLE loop to monitor the the power management conditions.
This function is called from the MCU-specific IDLE loop to monitor the power management conditions.
This function returns the &quot;recommended&quot; power management state based on the PM configuration and activity reported in the last sampling periods.
The power management state is not automatically changed, however.
The IDLE loop must call <code>pm_changestate()</code> in order to make the state change.
</p>
<p>
These two steps are separated because the plaform-specific IDLE loop may have additional situational information that is not available to the the PM sub-system.
These two steps are separated because the platform-specific IDLE loop may have additional situational information that is not available to the PM sub-system.
For example, the IDLE loop may know that the battery charge level is very low and may force lower power states even if there is activity.
</p>
<p>
Documentation/NuttxUserGuide.html
+1 -1
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@@ -8462,7 +8462,7 @@ struct fat_format_s
<li>
<p>
The entire mapped portion of the file must be present in memory.
Since it is assumed the the MCU does not have an MMU, on-demanding
Since it is assumed that the MCU does not have an MMU, on-demanding
paging in of file blocks cannot be supported. Since the while mapped
portion of the file must be present in memory, there are limitations
in the size of files that may be memory mapped (especially on MCUs
README.txt
+2 -2
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@@ -477,7 +477,7 @@ NuttX Configuration Tool under DOS
And of course, after you use the configuration tool you need to
restore CONFIG_WINDOWS_NATIVE=y and the correct CONFIG_APPS_DIR.
2) You can, with some effort, run the the Cygwin kconfig-mconf tool
2) You can, with some effort, run the Cygwin kconfig-mconf tool
directly in the Windows console window. In this case, you do not
have to modify the .config file, but there are other complexities:
@@ -791,7 +791,7 @@ Installing GNUWin32
5. After running GetGNUWin32-0.x.x.exe, you will have a new directory
<this-directory>/GetGNUWin32
Note the the GNUWin32 installer didn't install GNUWin32. Instead, it
Note that the GNUWin32 installer didn't install GNUWin32. Instead, it
installed another, smarter downloader. That downloader is the GNUWin32
package management tool developed by the Open SSL project.
ReleaseNotes
+1 -1
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@@ -1769,7 +1769,7 @@ from the NuttX Porting Guide:
point that is called from the application at initialization
time. This driver calls usbhost_registerclass() during this
initialization in order to makes itself available in the
event the the device that it supports is connected. Examples:
event that the device that it supports is connected. Examples:
The function usbhost_storageinit() in the file
drivers/usbhost/usbhost_storage.c
2. Each application must include a waiter thread thread that
TODO
+2 -2
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@@ -117,7 +117,7 @@ o Task/Scheduler (sched/)
Title: GET_ENVIRON_PTR()
Description: get_environ_ptr() (sched/sched_getenvironptr.c) is not implemented.
The representation of the the environment strings selected for
The representation of the environment strings selected for
NutX is not compatible with the operation. Some significant
re-design would be required to implement this funcion and that
effort is thought to be not worth the result.
@@ -422,7 +422,7 @@ o Kernel Build
Linux, for example, has functions call up() and down(). up()
increments the semaphore count but does not call into the kernel
unless incrementing the count unblocks a task; similarly, down
decrements the count and does not call into the the kernel unless
decrements the count and does not call into the kernel unless
the count becomes negative the caller must be blocked.
Update:
arch/arm/src/arm/up_head.S
+1 -1
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@@ -275,7 +275,7 @@ __start:
* effect. First populate the L1 table for the locked and paged
* text regions.
*
* We could probably make the the pg_l1span and pg_l2map macros into
* We could probably make the pg_l1span and pg_l2map macros into
* call-able subroutines, but we would have to be carefully during
* this phase while we are operating in a physical address space.
*
arch/arm/src/armv7-a/arm_pghead.S
+1 -1
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@@ -265,7 +265,7 @@ __start:
* effect. First populate the L1 table for the locked and paged
* text regions.
*
* We could probably make the the pg_l1span and pg_l2map macros into
* We could probably make the pg_l1span and pg_l2map macros into
* call-able subroutines, but we would have to be carefully during
* this phase while we are operating in a physical address space.
*
arch/arm/src/armv7-a/arm_vectoraddrexcptn.S
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Shouldn't happen. This exception handler is in a separate file from
* other vector handlers because some processors (e.g., Cortex-A5) do not
* support the the Address Exception vector.
* support the Address Exception vector.
*
****************************************************************************/
arch/arm/src/armv7-a/cache.h
+1 -1
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@@ -968,7 +968,7 @@ void cp15_clean_dcache(uintptr_t start, uintptr_t end);
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the the D cache.
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region
arch/arm/src/armv7-a/cp15_flush_dcache.S
+1 -1
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@@ -76,7 +76,7 @@
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the the D cache.
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region
arch/arm/src/armv7-m/ram_vectors.h
+1 -1
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@@ -77,7 +77,7 @@
/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
* ARM-specific implementations of irq_initialize(), irq_attach(), and
* irq_dispatch. In this case, it is also assumed that the ARM vector
* table resides in RAM, has the the name up_ram_vectors, and has been
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*/
arch/arm/src/armv7-m/up_ramvec_initialize.c
+1 -1
View File
@@ -65,7 +65,7 @@
/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
* ARM-specific implementations of up_ramvec_initialize(), irq_attach(), and
* irq_dispatch. In this case, it is also assumed that the ARM vector
* table resides in RAM, has the the name up_ram_vectors, and has been
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*/
arch/arm/src/kinetis/kinetis_sdhc.c
+1 -1
View File
@@ -742,7 +742,7 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
* Name: kinetis_datadisable
*
* Description:
* Disable the the SDIO data path setup by kinetis_dataconfig() and
* Disable the SDIO data path setup by kinetis_dataconfig() and
* disable DMA.
*
****************************************************************************/
arch/arm/src/kinetis/kinetis_serial.c
+8 -8
View File
@@ -900,8 +900,8 @@ static int up_interrupts(int irq, void *context)
if (count > 0)
#else
/* Check if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*
@@ -929,8 +929,8 @@ static int up_interrupts(int irq, void *context)
# error "Missing logic"
#else
/* Check if the transmit data register is "empty." NOTE: If FIFOS
* are enabled, this does not mean that the the FIFO is empty, rather,
* it means that the the number of bytes in the TX FIFO is below the
* are enabled, this does not mean that the FIFO is empty, rather,
* it means that the number of bytes in the TX FIFO is below the
* watermark setting. There could actually be space for additional TX
* data.
*
@@ -1090,8 +1090,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
return count > 0;
#else
/* Return true if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*/
@@ -1175,8 +1175,8 @@ static bool up_txready(struct uart_dev_s *dev)
# error "Missing logic"
#else
/* Return true if the transmit data register is "empty." NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is empty,
* rather, it means that the the number of bytes in the TX FIFO is
* FIFOS are enabled, this does not mean that the FIFO is empty,
* rather, it means that the number of bytes in the TX FIFO is
* below the watermark setting. There may actually be space for
* additional TX data.
*/
arch/arm/src/kinetis/kinetis_vectors.S
+1 -1
View File
@@ -626,7 +626,7 @@ kinetis_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
arch/arm/src/kl/kl_serial.c
+8 -8
View File
@@ -547,8 +547,8 @@ static int up_interrupts(int irq, void *context)
s1 = up_serialin(priv, KL_UART_S1_OFFSET);
/* Check if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*
@@ -567,8 +567,8 @@ static int up_interrupts(int irq, void *context)
/* Handle outgoing, transmit bytes */
/* Check if the transmit data register is "empty." NOTE: If FIFOS
* are enabled, this does not mean that the the FIFO is empty, rather,
* it means that the the number of bytes in the TX FIFO is below the
* are enabled, this does not mean that the FIFO is empty, rather,
* it means that the number of bytes in the TX FIFO is below the
* watermark setting. There could actually be space for additional TX
* data.
*
@@ -728,8 +728,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Return true if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*/
@@ -804,8 +804,8 @@ static bool up_txready(struct uart_dev_s *dev)
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Return true if the transmit data register is "empty." NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is empty,
* rather, it means that the the number of bytes in the TX FIFO is
* FIFOS are enabled, this does not mean that the FIFO is empty,
* rather, it means that the number of bytes in the TX FIFO is
* below the watermark setting. There may actually be space for
* additional TX data.
*/
arch/arm/src/lm/lm_vectors.S
+1 -1
View File
@@ -229,7 +229,7 @@ lm_irqcommon:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
arch/arm/src/lpc17xx/lpc17_ethernet.c
+1 -1
View File
@@ -2495,7 +2495,7 @@ static inline int lpc17_ethinitialize(int intf)
#endif
if (ret != 0)
{
/* We could not attach the ISR to the the interrupt */
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}
arch/arm/src/lpc17xx/lpc17_sdcard.c
+2 -2
View File
@@ -636,7 +636,7 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl)
*
* Description:
* Return the current value of the the PWRCTRL field of the SD card P
* register. This function can be used to see the the SD card is power ON
* register. This function can be used to see if the SD card is powered ON
* or OFF
*
* Input Parameters:
@@ -908,7 +908,7 @@ static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
* Name: lpc17_datadisable
*
* Description:
* Disable the the SD card data path setup by lpc17_dataconfig() and
* Disable the SD card data path setup by lpc17_dataconfig() and
* disable DMA.
*
****************************************************************************/
arch/arm/src/lpc17xx/lpc17_vectors.S
+1 -1
View File
@@ -238,7 +238,7 @@ lpc17_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
arch/arm/src/lpc31xx/lpc31_cgudrvr.h
+2 -2
View File
@@ -794,7 +794,7 @@ EXTERN uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
* Name: lpc31_enableexten
*
* Description:
* Enable external enabling for the the specified possible clocks.
* Enable external enabling for the specified possible clocks.
*
************************************************************************/
@@ -804,7 +804,7 @@ EXTERN void lpc31_enableexten(enum lpc31_clockid_e clkid);
* Name: lpc31_disableexten
*
* Description:
* Disable external enabling for the the specified possible clocks.
* Disable external enabling for the specified possible clocks.
*
************************************************************************/
arch/arm/src/lpc31xx/lpc31_clkexten.c
+2 -2
View File
@@ -69,7 +69,7 @@
* Name: lpc31_enableexten
*
* Description:
* Enable external enabling for the the specified possible clocks.
* Enable external enabling for the specified possible clocks.
*
****************************************************************************/
@@ -112,7 +112,7 @@ void lpc31_enableexten(enum lpc31_clockid_e clkid)
* Name: lpc31_disableexten
*
* Description:
* Disable external enabling for the the specified possible clocks.
* Disable external enabling for the specified possible clocks.
*
****************************************************************************/
arch/arm/src/lpc31xx/lpc31_softreset.c
+1 -1
View File
@@ -84,7 +84,7 @@ void lpc31_softreset(enum lpc31_resetid_e resetid)
for (i = 0;i < 1000; i++);
/* Then set the the soft reset bit */
/* Then set the soft reset bit */
putreg32(CGU_SOFTRESET, address);
}
arch/arm/src/lpc43xx/lpc43_rgu.c
+2 -2
View File
@@ -76,7 +76,7 @@
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
* Assumptions:
@@ -93,7 +93,7 @@ void lpc43_softreset(void)
/* Disable interrupts */
flags = irqsave();
/* Reset all of the peripherals that we can (safely) */
putreg32((RGU_CTRL0_LCD_RST | RGU_CTRL0_USB0_RST |
arch/arm/src/lpc43xx/lpc43_rgu.h
+1 -1
View File
@@ -76,7 +76,7 @@ extern "C" {
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
****************************************************************************/
arch/arm/src/lpc43xx/lpc43_start.c
+4 -4
View File
@@ -114,7 +114,7 @@ static inline void lpc43_setbootrom(void)
putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP);
/* Address zero now maps to the Boot ROM. Make sure the the VTOR will
/* Address zero now maps to the Boot ROM. Make sure that the VTOR will
* use the ROM vector table at that address.
*/
@@ -197,7 +197,7 @@ static inline void lpc43_fpuconfig(void)
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval = getcontrol();
regval |= (1 << 2);
setcontrol(regval);
@@ -227,7 +227,7 @@ static inline void lpc43_fpuconfig(void)
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval = getcontrol();
regval &= ~(1 << 2);
setcontrol(regval);
@@ -273,7 +273,7 @@ void __start(void)
/* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*/
arch/arm/src/nuc1xx/nuc_gpio.c
+1 -1
View File
@@ -101,7 +101,7 @@ int nuc_configgpio(gpio_cfgset_t cfgset)
DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
base = NUC_GPIO_CTRL_BASE(port);
/* Set the the GPIO PMD register */
/* Set the GPIO PMD register */
regaddr = base + NUC_GPIO_PMD_OFFSET;
regval = getreg32(regaddr);
arch/arm/src/nuc1xx/nuc_lowputc.c
+1 -1
View File
@@ -86,7 +86,7 @@
#endif
/* Select either the external high speed crystal, the PLL output, or
* the internal high speed clock as the the UART clock source.
* the internal high speed clock as the UART clock source.
*/
#if defined(CONFIG_NUC_UARTCLK_XTALHI)
arch/arm/src/sam34/sam3u_dmac.c
+6 -6
View File
@@ -298,7 +298,7 @@ static inline uint32_t sam_fifocfg(struct sam_dma_s *dmach)
* Name: sam_txcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@@ -322,7 +322,7 @@ static inline uint32_t sam_txcfg(struct sam_dma_s *dmach)
* Name: sam_rxcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
@@ -346,7 +346,7 @@ static inline uint32_t sam_rxcfg(struct sam_dma_s *dmach)
* Name: sam_txctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a transmit (memory to peripheral) transfer. These are only the "fixed"
* CTRLA values and need to be updated with the actual transfer size before
* being written to CTRLA sam_txctrla).
@@ -492,7 +492,7 @@ static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
* Name: sam_rxctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
* values and need to be updated with the actual transfer size before being
* written to CTRLA sam_rxctrla).
@@ -637,7 +637,7 @@ static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
* Name: sam_txctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@@ -716,7 +716,7 @@ static inline uint32_t sam_txctrlb(struct sam_dma_s *dmach)
* Name: sam_rxctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
arch/arm/src/sam34/sam_vectors.S
+1 -1
View File
@@ -244,7 +244,7 @@ sam_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
+1 -1
View File
@@ -527,7 +527,7 @@
* in the file mmu.h
*
* We must declare the page table at the bottom or at the top of internal
* SRAM. We pick the the bottom of internal SRAM *unless* there are vectors
* SRAM. We pick the bottom of internal SRAM *unless* there are vectors
* in the way at that position.
*/
arch/arm/src/sama5/sam_boot.c
+1 -1
View File
@@ -172,7 +172,7 @@ static const struct section_mapping_s section_mapping[] =
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
* initialized. If we are running out of SDRAM now, we can assume that some
* second level boot loader has properly configured SRAM for us. In that
* case, we set the the MMU flags for the final, fully cache-able state.
* case, we set the MMU flags for the final, fully cache-able state.
*
* If we are running from ISRAM or NOR flash, then we will need to configure
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
arch/arm/src/sama5/sam_dmac.c
+8 -8
View File
@@ -748,7 +748,7 @@ static uint32_t sam_sink_channel(struct sam_dmach_s *dmach, uint8_t pid,
* Name: sam_txcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@@ -788,7 +788,7 @@ static inline uint32_t sam_txcfg(struct sam_dmach_s *dmach)
* Name: sam_rxcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
@@ -828,7 +828,7 @@ static inline uint32_t sam_rxcfg(struct sam_dmach_s *dmach)
* Name: sam_txctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a transmit (memory to peripheral) transfer. These are only the "fixed"
* CTRLA values and need to be updated with the actual transfer size before
* being written to CTRLA sam_txctrla).
@@ -932,7 +932,7 @@ static uint32_t sam_ntxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
{
unsigned int srcwidth;
/* Adjust the the source transfer size for the source chunk size (memory
/* Adjust the source transfer size for the source chunk size (memory
* chunk size). BTSIZE is "the number of transfers to be performed, that
* is, for writes it refers to the number of source width transfers
* to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@@ -992,7 +992,7 @@ static inline uint32_t sam_txctrla(struct sam_dmach_s *dmach,
* Name: sam_rxctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
* values and need to be updated with the actual transfer size before being
* written to CTRLA sam_rxctrla).
@@ -1100,7 +1100,7 @@ static uint32_t sam_nrxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
{
unsigned int srcwidth;
/* Adjust the the source transfer size for the source chunk size (peripheral
/* Adjust the source transfer size for the source chunk size (peripheral
* chunk size). BTSIZE is "the number of transfers to be performed, that
* is, for writes it refers to the number of source width transfers
* to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@@ -1160,7 +1160,7 @@ static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
* Name: sam_txctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@@ -1251,7 +1251,7 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
* Name: sam_rxctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
arch/arm/src/sama5/sam_ehci.c
+4 -4
View File
@@ -1389,7 +1389,7 @@ static void sam_qh_enqueue(struct sam_qh_s *qh)
{
uintptr_t physaddr;
/* Set the internal fqp field. When we transverse the the QH list later,
/* Set the internal fqp field. When we transverse the QH list later,
* we need to know the correct place to start because the overlay may no
* longer point to the first qTD entry.
*/
@@ -1554,7 +1554,7 @@ static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t bufl
next = (physaddr + 4096) & ~4095;
/* How many bytes were included in the last buffer? Was the the whole
/* How many bytes were included in the last buffer? Was it the whole
* thing?
*/
@@ -2059,7 +2059,7 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
**bp = qtd->hw.nqp;
/* Subtract the number of bytes left untransferred. The epinfo->xfrd
* field is initialized to the the total number of bytes to be transferred
* field is initialized to the total number of bytes to be transferred
* (all qTDs in the list). We subtract out the number of untransferred
* bytes on each transfer and the final result will be the number of bytes
* actually transferred.
@@ -3825,7 +3825,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
regval16 = sam_swap16(HCCR->hciversion);
uvdbg("HCIVERSION %x.%02x\n", regval16 >> 8, regval16 & 0xff);
/* Verify the the correct number of ports is reported */
/* Verify that the correct number of ports is reported */
regval = sam_getreg(&HCCR->hcsparams);
nports = (regval & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
arch/arm/src/stm32/stm32_can.c
+1 -1
View File
@@ -1332,7 +1332,7 @@ static int can_bittiming(struct stm32_can_s *priv)
canllvdbg("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
/* Configure bit timing. This also does the the following, less obvious
/* Configure bit timing. This also does the following, less obvious
* things. Unless loopback mode is enabled, it:
*
* - Disables silent mode.
arch/arm/src/stm32/stm32_eth.c
+4 -4
View File
@@ -1219,7 +1219,7 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev)
*
* Description:
* The function is called when a frame is received using the DMA receive
* interrupt. It scans the RX descriptors to the the received frame.
* interrupt. It scans the RX descriptors to the received frame.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1347,7 +1347,7 @@ static void stm32_disableint(FAR struct stm32_ethmac_s *priv, uint32_t ierbit)
*
* Description:
* The function is called when a frame is received using the DMA receive
* interrupt. It scans the RX descriptors to the the received frame.
* interrupt. It scans the RX descriptors to the received frame.
*
* Parameters:
* priv - Reference to the driver state structure
@@ -1506,7 +1506,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> ETH_RDES0_FL_SHIFT) - 4;
/* Get a buffer from the free list. We don't even check if
* this is successful because we already assure the the free
* this is successful because we already assure the free
* list is not empty above.
*/
@@ -2536,7 +2536,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
return ret;
}
/* Bit 8 of the DSCR register is zero, the the DM9161 has not selected RMII.
/* Bit 8 of the DSCR register is zero, then the DM9161 has not selected RMII.
* If RMII is not selected, then reset the MCU to recover.
*/
arch/arm/src/stm32/stm32_iwdg.c
+1 -1
View File
@@ -673,7 +673,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
/* Make sure that the LSI ocsillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file (because this file does
* not know the the global usage of the oscillator. Any clock management
* not know the global usage of the oscillator. Any clock management
* logic (say, as part of a power management scheme) needs handle other
* LSI controls outside of this file.
*/
arch/arm/src/stm32/stm32_otgfshost.c
+3 -3
View File
@@ -996,7 +996,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
FAR struct stm32_chan_s *chan)
{
/* Is the the transfer complete? Is there a thread waiting for this transfer
/* Is the transfer complete? Is there a thread waiting for this transfer
* to complete?
*/
@@ -1774,7 +1774,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
/* Clear any pending NAK condition. The 'indata1' data toggle
* should have been appropriately updated by the the RxFIFO
* should have been appropriately updated by the RxFIFO
* logic as each packet was received.
*/
@@ -2961,7 +2961,7 @@ static inline void stm32_hostinit_enable(void)
* Enable Tx FIFO empty interrupts. This is necessary when the entire
* transfer will not fit into Tx FIFO. The transfer will then be completed
* when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled
* the the fifo empty interrupt handler when the transfer is complete.
* the fifo empty interrupt handler when the transfer is complete.
*
* Input Parameters:
* priv - Driver state structure reference
arch/arm/src/stm32/stm32_rcc.h
+1 -1
View File
@@ -76,7 +76,7 @@ extern "C"
* Public Data
************************************************************************************/
/* This symbol references the Cortex-M3 vector table (as positioned by the the linker
/* This symbol references the Cortex-M3 vector table (as positioned by the linker
* script, ld.script or ld.script.dfu. The standard location for the vector table is
* at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU
* bootloader, then the vector table will be offset to a different location in FLASH
arch/arm/src/stm32/stm32_sdio.c
+3 -3
View File
@@ -203,7 +203,7 @@
# error "Unknown STM32 DMA"
#endif
/* SDIO DMA Channel/Stream selection. For the the case of the STM32 F4, there
/* SDIO DMA Channel/Stream selection. For the case of the STM32 F4, there
* are multiple DMA stream options that must be dis-ambiguated in the board.h
* file.
*/
@@ -682,7 +682,7 @@ static void stm32_setpwrctrl(uint32_t pwrctrl)
*
* Description:
* Return the current value of the the PWRCTRL field of the SDIO POWER
* register. This function can be used to see the the SDIO is power ON
* register. This function can be used to see if the SDIO is powered ON
* or OFF
*
* Input Parameters:
@@ -952,7 +952,7 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
* Name: stm32_datadisable
*
* Description:
* Disable the the SDIO data path setup by stm32_dataconfig() and
* Disable the SDIO data path setup by stm32_dataconfig() and
* disable DMA.
*
****************************************************************************/
arch/arm/src/stm32/stm32_vectors.S
+1 -1
View File
@@ -251,7 +251,7 @@ stm32_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
arch/arm/src/stm32/stm32_wwdg.c
+1 -1
View File
@@ -623,7 +623,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the the reset-on-expiration
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
* Returned Values:
arch/arm/src/stm32/stm32f20xxx_dma.c
+1 -1
View File
@@ -521,7 +521,7 @@ void weak_function up_dmainitialize(void)
*
* Input parameter:
* dmamap - Identifies the stream/channel resource. For the STM32 F2, this
* is a bit-encoded value as provided by the the DMAMAP_* definitions
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f20xxx_dma.h
*
* Returned Value:
arch/arm/src/stm32/stm32f40xxx_dma.c
+1 -1
View File
@@ -520,7 +520,7 @@ void weak_function up_dmainitialize(void)
*
* Input parameter:
* dmamap - Identifies the stream/channel resource. For the STM32 F4, this
* is a bit-encoded value as provided by the the DMAMAP_* definitions
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f40xxx_dma.h
*
* Returned Value:

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