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Fixed non-UTF8 characters.

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This commit is contained in:
Fotis Panagiotopoulos
2022-09-27 15:14:07 +03:00
committed by Xiang Xiao
parent 078a0486f5
commit bbf3f2866d
120 changed files with 449 additions and 449 deletions
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8
arch/arm/src/a1x/hardware/a10_memorymap.h
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@@ -46,7 +46,7 @@
#define A1X_SRAMC_PSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_PSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_PSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X Offsets from the internal memory section base address */
@@ -136,7 +136,7 @@
/* A1X offsets from the BRROM section base address */
#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X internal memory physical base addresses */
@@ -239,7 +239,7 @@
#define A1X_PERIPH_SIZE 0x00050000 /* Peripherals 0x01c0:0000-0x01c4:ffff */
#define A1X_SRAMC_SIZE 0x00100000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_SIZE 0x000c0000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000—0xffff:7fff 32K */
#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000-0xffff:7fff 32K */
/* Force configured sizes that might exceed 2GB to be unsigned long */
@@ -303,7 +303,7 @@
#define A1X_SRAMC_VSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_VSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_VSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000—0xffff:7fff 32K */
#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
#endif

8
arch/arm/src/armv7-a/arm.h
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@@ -19,10 +19,10 @@
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/

2
arch/arm/src/armv7-a/arm_l2cc_pl310.c
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@@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!

10
arch/arm/src/armv7-a/cp15.h
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@@ -20,10 +20,10 @@
/* References:
*
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/
@@ -55,7 +55,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__

2
arch/arm/src/armv7-a/l2cc_pl310.h
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@@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/

10
arch/arm/src/armv7-a/mmu.h
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@@ -19,10 +19,10 @@
****************************************************************************/
/* References:
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
@@ -62,7 +62,7 @@
/* MMU CP15 Register Bit Definitions ****************************************/
/* Reference: Cortex-A5™ MPCore
/* Reference: Cortex-A5™ MPCore
* Paragraph 6.7, "MMU software accessible registers."
*/

2
arch/arm/src/armv7-r/arm_l2cc_pl310.c
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@@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!

2
arch/arm/src/armv7-r/cp15.h
View File

@@ -52,7 +52,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__

2
arch/arm/src/armv7-r/l2cc_pl310.h
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@@ -18,7 +18,7 @@
*
****************************************************************************/
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/

2
arch/arm/src/kinetis/hardware/kinetis_ewm.h
View File

@@ -54,7 +54,7 @@
#define EWM_CTRL_EWMEN (1 << 0) /* Bit 0: EWM enable */
#define EWM_CTRL_ASSIN (1 << 2) /* Bit 1: EWM_in's Assertion State Select */
#define EWM_CTRL_INEN (1 << 3) /* Bit 2: Input Enable */
/* Bits 7–3: Reserved */
/* Bits 7-3: Reserved */
/* Service Register (8-bit values: 0xb4 followed by 0x2c) */

2
arch/arm/src/kinetis/hardware/kinetis_rngb.h
View File

@@ -61,7 +61,7 @@
#define RNG_VER_MINOR_MASK (0xff << RNG_VER_MINOR_SHIFT)
#define RNG_VER_MAJOR_SHIFT (8) /* Bits 8-15: Major version number */
#define RNG_VER_MAJOR_MASK (0xff << RNG_VER_MAJOR_SHIFT)
/* Bits 27–16: Reserved */
/* Bits 27-16: Reserved */
#define RNG_VER_TYPE_SHIFT (28) /* Bits 28-31: Random number generator type */
#define RNG_VER_TYPE_MASK (15 << RNG_VER_TYPE_SHIFT)
# define RNG_VER_TYPE_RNGA (0 << RNG_VER_TYPE_SHIFT)

4
arch/arm/src/kinetis/hardware/kinetis_tsi.h
View File

@@ -199,7 +199,7 @@
#define TSI_SCANC_EXTCHRG_SHIFT (19) /* Bits 19-23: External oscillator charge current select */
#define TSI_SCANC_EXTCHRG_MASK (31 << TSI_SCANC_EXTCHRG_SHIFT)
# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
#define TSI_SCANC_CAPTRM_SHIFT (24) /* Bits 24-26: Internal capacitance trim value */
#define TSI_SCANC_CAPTRM_MASK (7 << TSI_SCANC_CAPTRM_SHIFT)
@@ -214,7 +214,7 @@
#define TSI_SCANC_REFCHRG_SHIFT (27) /* Bits 27-31: Reference oscillator charge current select */
#define TSI_SCANC_REFCHRG_MASK (31 << TSI_SCANC_REFCHRG_SHIFT)
# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
/* Pin enable register */

4
arch/arm/src/kinetis/hardware/kinetis_wdog.h
View File

@@ -67,7 +67,7 @@
/* Watchdog Status and Control Register High (16-bit) */
#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG’s operation */
#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG's operation */
#define WDOG_STCTRLH_CLKSRC (1 << 1) /* Bit 1: Selects clock source for the WDOG timer */
#define WDOG_STCTRLH_IRQRSTEN (1 << 2) /* Bit 2: Enable the debug breadcrumbs feature */
#define WDOG_STCTRLH_WINEN (1 << 3) /* Bit 3: Enable windowing mode */
@@ -88,7 +88,7 @@
# define WDOG_STCTRLH_BYTESEL_BYTE2 (2 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 2 selected */
# define WDOG_STCTRLH_BYTESEL_BYTE3 (3 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 3 selected */
#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG’s functional test mode */
#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG's functional test mode */
/* Bit 15: Reserved */
/* Watchdog Status and Control Register Low (16-bit) */

2
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
View File

@@ -613,7 +613,7 @@ void lpc17_40_dmastop(DMA_HANDLE handle)
/* Disable this channel and mask any further interrupts from the channel.
* this channel. The channel is disabled by clearning the channel
* enable bit. Any outstanding data in the FIFO’s is lost.
* enable bit. Any outstanding data in the FIFO's is lost.
*/
regaddr = LPC17_40_DMACH_CONFIG((uint32_t)dmach->chn);

4
arch/arm/src/lpc31xx/lpc31_analogdie.h
View File

@@ -295,9 +295,9 @@
#define CODEC_DEC_DCFILTO (1 << 18) /* Bit 18: Enable DC blocking filter after decimation filters */
#define CODEC_DEC_DBLIN (1 << 17) /* Bit 17: Enable soft start-up after a reset */
#define CODEC_DEC_DELAY_DBLIN (1 << 16) /* Bit 16: Enable delay timer after a reset */
#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2’s compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINL_MASK (0xff << CODEC_DEC_GAINL_SHIFT)
#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2’s compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINR_MASK (0xff << CODEC_DEC_GAINR_SHIFT)
/* Interpolator control */

2
arch/arm/src/lpc31xx/lpc31_bcrndx.c
View File

@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_cgu.h
View File

@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
*/
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_CGU_H

2
arch/arm/src/lpc31xx/lpc31_cgudrvr.h
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_clkdomain.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_clkfreq.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_esrndx.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_fdcndx.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

6
arch/arm/src/lpc31xx/lpc31_fdivinit.c
View File

@@ -62,7 +62,7 @@
* Say an input frequency of 13 MHz is given while a frequency of 12
* MHz is required. In this case we want a frequency
*
* f’ = 12/13 × f
* f' = 12/13 x f
*
* So n = 12 and m = 13. This then gives
*
@@ -77,8 +77,8 @@
* 4 bits. If madd/msub bit width has been set to say 8 bits, it is allowed
* to shift 4 bits, giving:
*
* msub’ = -(12<<4)= -12 × 24 = -12 × 16 = -192
* madd’ = 1<<4 = 24 = 16
* msub' = -(12<<4)= -12 x 24 = -12 x 16 = -192
* madd' = 1<<4 = 24 = 16
*
****************************************************************************/

2
arch/arm/src/lpc31xx/lpc31_pllconfig.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_setfreqin.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/

2
arch/arm/src/lpc31xx/lpc31_softreset.c
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@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
* - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/

4
arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
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@@ -113,9 +113,9 @@
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
/* Bits 15-31: Reserved */
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
/* Transmit FIFO: 8 x 32-bit transmit FIFO */
/* Receive FIFO: 8 × 32-bit receive FIFO */
/* Receive FIFO: 8 x 32-bit receive FIFO */
/* Status Feedback Register */

10
arch/arm/src/sam34/hardware/sam_rtc.h
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@@ -120,11 +120,11 @@
# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
# define RTC_MR_THIGH_16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
# define RTC_MR_THIGH_4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)

4
arch/arm/src/sama5/hardware/sam_xdmac.h
View File

@@ -51,7 +51,7 @@
#define SAM_XDMAC_GSWR_OFFSET 0x0038 /* Global Channel Software Request Register */
#define SAM_XDMAC_GSWS_OFFSET 0x003c /* Global Channel Software Request Status Register */
#define SAM_XDMAC_GSWF_OFFSET 0x0040 /* Global Channel Software Flush Request Register */
/* 0x0044–0x004c Reserved */
/* 0x0044-0x004c Reserved */
/* Offsets to the base of the DMA channel registers */
@@ -92,7 +92,7 @@
#define SAM_XDMACH_CSUS_OFFSET 0x0030 /* Channel Source Microblock Stride */
#define SAM_XDMACH_CDUS_OFFSET 0x0034 /* Channel Destination Microblock Stride */
/* 0x0038-0x003c Reserved */
/* 0x0fec–0x0ffc Reserved */
/* 0x0fec-0x0ffc Reserved */
/* XDMAC Register Addresses *************************************************/

2
arch/arm/src/samd2l2/hardware/samd20_memorymap.h
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@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H

2
arch/arm/src/samd2l2/hardware/samd20_pinmap.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H

2
arch/arm/src/samd2l2/hardware/samd21_memorymap.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H

2
arch/arm/src/samd2l2/hardware/samd21_pinmap.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H

2
arch/arm/src/samd2l2/hardware/samd_evsys.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H

4
arch/arm/src/samd2l2/hardware/samd_fuses.h
View File

@@ -41,9 +41,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H

4
arch/arm/src/samd2l2/hardware/samd_gclk.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H

8
arch/arm/src/samd2l2/hardware/samd_i2c_master.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
@@ -203,9 +203,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */

2
arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H

4
arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H

4
arch/arm/src/samd2l2/hardware/samd_pm.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H

4
arch/arm/src/samd2l2/hardware/samd_port.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H

2
arch/arm/src/samd2l2/hardware/samd_sercom.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H

2
arch/arm/src/samd2l2/hardware/samd_spi.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H

68
arch/arm/src/samd2l2/hardware/samd_sysctrl.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
@@ -154,22 +154,22 @@
#define SYSCTRL_XOSC_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define SYSCTRL_XOSC_STARTUP_MASK (15 << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP(n) ((n) << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
/* 32kHz external crystal oscillator control register */
@@ -183,14 +183,14 @@
#define SYSCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_XOSC32K_STARTUP_MASK (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP(n) ((n) << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
#define SYSCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
@@ -208,14 +208,14 @@
#define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_OSC32K_STARTUP_MASK (7 << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP(n) ((n) << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define SYSCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define SYSCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */

4
arch/arm/src/samd2l2/hardware/samd_usart.h
View File

@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
* Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H

4
arch/arm/src/samd2l2/hardware/samd_wdt.h
View File

@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
* Datasheet", 42129J–SAM–12/2013
* Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
@@ -72,7 +72,7 @@
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */

6
arch/arm/src/samd2l2/hardware/saml_i2c_master.h
View File

@@ -164,9 +164,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */

16
arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
View File

@@ -115,14 +115,14 @@
#define OSC32KCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OSC32KCTRL_OSC32K_STARTUP_MASK (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_OSC32K_STARTUP(n) ((n) << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define OSC32KCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define OSC32KCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */

64
arch/arm/src/samd2l2/hardware/saml_oscctrl.h
View File

@@ -117,22 +117,22 @@
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
/* 16MHz internal oscillator control register */
@@ -159,22 +159,22 @@
#define OSCCTRL_OSC16MCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_OSC16MCTRL_STARTUP_MASK (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
# define OSCCTRL_OSC16MCTRL_STARTUP(n) ((n) << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000µs */
# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000µs */
/* DFLL48M control register */

2
arch/arm/src/samd2l2/hardware/saml_wdt.h
View File

@@ -72,7 +72,7 @@
/* Configuration register */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */

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