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Add support for fast GPIO on lpc214x

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1766 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2009-05-09 15:18:14 +00:00
parent cc0c478463
commit bb56732a70
4 changed files with 53 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/mcu123-lpc214x/README.txt
+3
View File
@@ -98,10 +98,13 @@ ARM/LPC214X-specific Configuration Options
LPC2148 specific chip initialization
These provide register setup values:
CONFIG_EXTMEM_MODE, CONFIG_RAM_MODE, CONFIG_CODE_BASE, CONFIG_PLL_SETUP,
CONFIG_MAM_SETUP, CONFIG_APBDIV_SETUP, CONFIG_EMC_SETUP, CONFIG_BCFG0_SETUP,
CONFIG_BCFG1_SETUP, CONFIG_BCFG2_SETUP, CONFIG_BCFG3_SETUP, CONFIG_ADC_SETUP
CONFIG_LPC214x_FIO - Enable fast GPIO (vs. legacy, "old" GPIO).
LPC214X specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
configs/mcu123-lpc214x/nsh/ld.script
+11 -4
View File
@@ -33,6 +33,12 @@
*
****************************************************************************/
MEMORY
{
flash (rx) : ORIGIN = 0, LENGTH = 500K
ram (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
}
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
@@ -42,7 +48,6 @@ SECTIONS
* 0x00000000 (default MEMMAP mode assumed)
*/
. = 0x00000000;
.text : {
_stext = ABSOLUTE(.);
*(.text)
@@ -54,7 +59,7 @@ SECTIONS
*(.glue_7t)
*(.got) /* Global offset table */
_etext = ABSOLUTE(.);
}
} > flash
_eronly = ABSOLUTE(.); /* This is where the .data section
* is relocated for execution out
* FLASH */
@@ -64,20 +69,22 @@ SECTIONS
* to _sdata at boot time.
*/
. = 0x40000000;
.data : {
_sdata = ABSOLUTE(.);
*(.data)
CONSTRUCTORS
_edata = ABSOLUTE(.);
}
} >ram AT>flash
. = ALIGN(32 / 8);
.bss : { /* BSS */
_sbss = ABSOLUTE(.);
*(.bss)
*(COMMON)
_ebss = ABSOLUTE(.);
}
. = ALIGN(32 / 8);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
configs/mcu123-lpc214x/src/up_leds.c
+23 -9
View File
@@ -50,11 +50,25 @@
/* P1.16-P1.23 control LEDS 1-8 */
#define LEDBIT(led) (0x00010000 << (led))
#define ALLLEDS (0x00ff0000)
#define LEDBIT(led) (0x00010000 << (led))
#define ALLLEDS (0x00ff0000)
#define putled(v,r) putreg32((v),(LPC214X_GPIO1_BASE+(r)))
#define CLRLEDS putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET)
#ifdef CONFIG_LPC214x_FIO
# define putled(v,r) putreg32((v),(LPC214X_FIO1_BASE+(r)))
# define CLRLEDS putled(ALLLEDS,LPC214X_FIO_SET_OFFSET)
# define LED_SET_OFFSET LPC214X_FIO_SET_OFFSET
# define LED_CLR_OFFSET LPC214X_FIO_CLR_OFFSET
# define LED_DIR_OFFSET LPC214X_FIO_DIR_OFFSET
#else
# define putled(v,r) putreg32((v),(LPC214X_GPIO1_BASE+(r)))
# define CLRLEDS putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET)
# define LED_SET_OFFSET LPC214X_GPIO_SET_OFFSET
# define LED_CLR_OFFSET LPC214X_GPIO_CLR_OFFSET
# define LED_DIR_OFFSET LPC214X_GPIO_DIR_OFFSET
#endif
/****************************************************************************
* Private Data
@@ -77,9 +91,9 @@ void up_ledinit(void)
{
/* Initilize GIOs P1.16-P1.23 */
putled(ALLLEDS,LPC214X_GPIO_DIR_OFFSET);
putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET);
putled(LEDBIT(0),LPC214X_GPIO_CLR_OFFSET);
putled(ALLLEDS,LED_DIR_OFFSET);
putled(ALLLEDS,LED_SET_OFFSET);
putled(LEDBIT(0),LED_CLR_OFFSET);
}
/****************************************************************************
@@ -88,7 +102,7 @@ void up_ledinit(void)
void up_ledon(int led)
{
putled(LEDBIT(led),LPC214X_GPIO_CLR_OFFSET);
putled(LEDBIT(led),LED_CLR_OFFSET);
}
/****************************************************************************
@@ -97,6 +111,6 @@ void up_ledon(int led)
void up_ledoff(int led)
{
putled(LEDBIT(led),LPC214X_GPIO_SET_OFFSET);
putled(LEDBIT(led),LED_SET_OFFSET);
}
#endif /* CONFIG_ARCH_LEDS */
configs/mcu123-lpc214x/src/up_spi.c
+16 -6
View File
@@ -82,6 +82,16 @@
#define LPC214X_CCLKFREQ (LPC214X_FOSC*LPC214X_PLL_M)
#define LPC214X_PCLKFREQ (LPC214X_CCLKFREQ/LPC214X_APB_DIV)
#ifdef CONFIG_LPC214x_FIO
# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET)
#else
# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET)
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@@ -143,13 +153,13 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean
{
/* Enable slave select (low enables) */
putreg32(bit, LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET);
putreg32(bit, CS_CLR_REGISTER);
}
else
{
/* Disable slave select (low enables) */
putreg32(bit, LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET);
putreg32(bit, CS_SET_REGISTER);
/* Wait for the TX FIFO not full indication */
@@ -425,7 +435,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
* PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1
* PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1
* PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1
* PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=10 for P0.20 (we'll control it via GPIO)
* PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=10 for P0.20 (we'll control it via GPIO or FIO)
*/
regval32 = getreg32(LPC214X_PINSEL1);
@@ -438,9 +448,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Disable chip select using P0.20 (SSEL1) (low enables) */
regval32 = 1 << 20;
putreg32(regval32, LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET);
regval32 |= getreg32(LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET);
putreg32(regval32, LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET);
putreg32(regval32, CS_SET_REGISTER);
regval32 |= getreg32(CS_DIR_REGISTER);
putreg32(regval32, CS_DIR_REGISTER);
/* Enable peripheral clocking to SPI1 */