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arch/stm32c0: add FDCAN support
add FDCAN support for stm32c0 family. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
committed by
Alan C. Assis
Alan C. Assis
parent
25876e327e
commit
ba00fa6478
@@ -82,8 +82,8 @@
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#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
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#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
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#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
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#define STM32_IRQ_FDCAN_IT0 (STM32_IRQ_EXTINT + 30) /* 30: FDCAN global interrupt 0 */
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#define STM32_IRQ_FDCAN_IT1 (STM32_IRQ_EXTINT + 31) /* 31: FDCAN global interrupt 1 */
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#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_EXTINT + 30) /* 30: FDCAN global interrupt 0 */
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#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_EXTINT + 31) /* 31: FDCAN global interrupt 1 */
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#define STM32_IRQ_NEXTINT (32)
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@@ -111,4 +111,13 @@ if(CONFIG_STM32F0L0G0_WWDG)
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list(APPEND SRCS stm32_wwdg.c)
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endif()
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if(CONFIG_STM32F0L0G0_FDCAN)
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if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER)
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list(APPEND SRCS stm32_fdcan.c)
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endif()
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if(CONFIG_STM32F0L0G0_FDCAN_SOCKET)
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list(APPEND SRCS stm32_fdcan_sock.c)
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endif()
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endif()
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target_sources(arch PRIVATE ${SRCS})
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@@ -1346,7 +1346,7 @@ config ARCH_CHIP_STM32C092XX
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select STM32F0L0G0_STM32C0
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select STM32F0L0G0_HAVE_USART3
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select STM32F0L0G0_HAVE_USART4
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select STM32F0L0G0_HAVE_FDCAN
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select STM32F0L0G0_HAVE_FDCAN1
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config STM32F0L0G0_DFU
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bool "DFU bootloader"
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@@ -1581,7 +1581,7 @@ config STM32F0L0G0_HAVE_OPAMP4
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bool
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default n
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config STM32F0L0G0_HAVE_FDCAN
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config STM32F0L0G0_HAVE_FDCAN1
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bool
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default n
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@@ -1680,6 +1680,12 @@ config STM32F0L0G0_DAC1
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depends on STM32F0L0G0_HAVE_DAC1
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select STM32F0L0G0_DAC
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config STM32F0L0G0_FDCAN1
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bool "FDCAN1"
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default n
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depends on STM32F0L0G0_HAVE_FDCAN1
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select STM32F0L0G0_FDCAN
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config STM32F0L0G0_FSMC
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bool "FSMC"
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default n
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@@ -1922,6 +1928,10 @@ config STM32F0L0G0_TIM
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bool
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default n
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config STM32F0L0G0_FDCAN
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bool
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default n
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config STM32F0L0G0_SERIALDRIVER
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bool
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default n
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@@ -2721,6 +2731,153 @@ config STM32F0L0G0_PWM_MULTICHAN
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endmenu # Timer Configuration
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menu "FDCAN driver configuration"
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depends on STM32F0L0G0_FDCAN
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choice
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prompt "FDCAN character driver or SocketCAN support"
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default STM32F0L0G0_FDCAN_CHARDRIVER
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config STM32F0L0G0_FDCAN_CHARDRIVER
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bool "STM32 FDCAN character driver support"
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select ARCH_HAVE_CAN_ERRORS
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select CAN
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config STM32F0L0G0_FDCAN_SOCKET
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bool "STM32 FDCAN SocketCAN support"
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select NET_CAN_HAVE_ERRORS
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select NET_CAN_HAVE_CANFD
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endchoice # FDCAN character driver or SocketCAN support
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config STM32F0L0G0_FDCAN_REGDEBUG
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bool "CAN Register level debug"
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depends on DEBUG_CAN_INFO
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default n
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---help---
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Output detailed register-level CAN device debug information.
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Requires also CONFIG_DEBUG_CAN_INFO.
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config STM32F0L0G0_FDCAN_QUEUE_MODE
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bool "FDCAN QUEUE mode (vs FIFO mode)"
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default n
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menu "FDCAN1 device driver options"
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depends on STM32F0L0G0_FDCAN1
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choice
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prompt "FDCAN1 frame format"
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default STM32F0L0G0_FDCAN1_ISO11898_1
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config STM32F0L0G0_FDCAN1_ISO11898_1
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bool "ISO11898-1"
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---help---
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Enable ISO11898-1 frame format
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config STM32F0L0G0_FDCAN1_NONISO_FORMAT
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bool "Non ISO"
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---help---
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Enable Non ISO, Bosch CAN FD Specification V1.0
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endchoice # FDCAN1 frame format
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choice
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prompt "FDCAN1 mode"
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default STM32F0L0G0_FDCAN1_CLASSIC
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config STM32F0L0G0_FDCAN1_CLASSIC
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bool "Classic CAN"
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---help---
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Enable Classic CAN mode
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config STM32F0L0G0_FDCAN1_FD
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bool "CAN FD"
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depends on CAN_FD || NET_CAN_CANFD
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---help---
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Enable CAN FD mode
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config STM32F0L0G0_FDCAN1_FD_BRS
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bool "CAN FD with fast bit rate switching"
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depends on CAN_FD || NET_CAN_CANFD
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---help---
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Enable CAN FD mode with fast bit rate switching mode.
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endchoice # FDCAN1 mode
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config STM32F0L0G0_FDCAN1_LOOPBACK
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bool "Enable FDCAN1 loopback mode"
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default n
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---help---
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Enable the FDCAN1 local loopback mode for testing purposes.
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comment "Nominal Bit Timing"
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config STM32F0L0G0_FDCAN1_BITRATE
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int "FDCAN bitrate"
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default 500000
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range 0 1000000
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---help---
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FDCAN1 bitrate in bits per second. Required if STM32F0L0G0_FDCAN1 is defined.
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config STM32F0L0G0_FDCAN1_NTSEG1
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int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)"
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default 6
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range 1 256
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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config STM32F0L0G0_FDCAN1_NTSEG2
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int "FDCAN1 NTSEG2 (PhaseSeg2)"
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default 7
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range 1 128
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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config STM32F0L0G0_FDCAN1_NSJW
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int "FDCAN1 synchronization jump width"
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default 1
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range 1 128
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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comment "Data Bit Timing"
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depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS
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config STM32F0L0G0_FDCAN1_DBITRATE
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int "FDCAN1 data bitrate"
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default 2000000
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depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS
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---help---
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FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS).
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config STM32F0L0G0_FDCAN1_DTSEG1
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int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)"
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default 4
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range 1 31
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depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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config STM32F0L0G0_FDCAN1_DTSEG2
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int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)"
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default 4
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range 1 15
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depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS
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---help---
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The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2).
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config STM32F0L0G0_FDCAN1_DSJW
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int "FDCAN1 fast synchronization jump width"
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default 2
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range 1 15
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depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS
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---help---
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The duration of a synchronization jump is Tcan_clk x DSJW.
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endmenu # FDCAN1 device driver options
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endmenu # "FDCAN driver configuration"
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menu "U[S]ART Configuration"
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depends on STM32F0L0G0_USART
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@@ -104,3 +104,12 @@ endif
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ifeq ($(CONFIG_STM32F0L0G0_WWDG),y)
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CHIP_CSRCS += stm32_wwdg.c
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endif
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ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y)
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ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y)
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CHIP_CSRCS += stm32_fdcan.c
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endif
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ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y)
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CHIP_CSRCS += stm32_fdcan_sock.c
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endif
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endif
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File diff suppressed because it is too large
Load Diff
@@ -73,7 +73,7 @@
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#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
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#define STM32_USBRAM_BASE 0x40009800 /* 0x40009800-0x40008fff USBRAM */
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#define STM32_FDCANSRAM_BASE 0x4000b800 /* 0x4000b800-0x4000cbff FDCAN scratch RAM */
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#define STM32_FDCANMRAM_BASE 0x4000b400 /* 0x4000b400-0x4000b7ff FDCAN message RAM */
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#define STM32_CANRAM_BASE 0x4000b400 /* 0x4000b400-0x4000b7ff FDCAN message RAM */
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#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG */
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/* EXTI ??? */
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#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */
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@@ -114,6 +114,27 @@
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#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14)
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#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
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/* FDCAN1 */
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#define GPIO_FDCAN1_RX_1 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11)
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#define GPIO_FDCAN1_RX_2 (GPIO_ALT | GPIO_AF3 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN0)
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#define GPIO_FDCAN1_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN5)
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#define GPIO_FDCAN1_RX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN12)
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#define GPIO_FDCAN1_RX_5 (GPIO_ALT | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8)
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#define GPIO_FDCAN1_RX_6 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN2)
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#define GPIO_FDCAN1_RX_7 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN4)
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#define GPIO_FDCAN1_RX_8 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN0)
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#define GPIO_FDCAN1_TX_1 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12)
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#define GPIO_FDCAN1_TX_2 (GPIO_ALT | GPIO_AF3 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN1)
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#define GPIO_FDCAN1_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13)
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#define GPIO_FDCAN1_TX_4 (GPIO_ALT | GPIO_AF15 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
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#define GPIO_FDCAN1_TX_5 (GPIO_ALT | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9)
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#define GPIO_FDCAN1_TX_6 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN3)
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#define GPIO_FDCAN1_TX_7 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN5)
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#define GPIO_FDCAN1_TX_8 (GPIO_ALT | GPIO_AF13 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN14)
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#define GPIO_FDCAN1_TX_9 (GPIO_ALT | GPIO_AF4 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN1)
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/* TODO: missing pinmaps */
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#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H */
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@@ -236,10 +236,10 @@
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#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */
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#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */
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/* Bits 2-11: Reserved */
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#define RCC_APB1RSTR_FDCANRST (1 << 11) /* Bit 11: FDCAN reset */
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/* Bit 12: Reserved */
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#define RCC_APB1RSTR_FDCANRST (1 << 12) /* Bit 12: FDCAN reset */
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#define RCC_APB1RSTR_USBRST (1 << 13) /* Bit 13: USB reset */
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#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
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#define RCC_APB1RSTR_USBRST (1 << 15) /* Bit 15: USB reset */
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/* Bit 15: Reserved */
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#define RCC_APB1RSTR_CRCRST (1 << 16) /* Bit 15: CRC reset */
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#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
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#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
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@@ -289,11 +289,11 @@
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#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */
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#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */
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/* Bits 2-11: Reserved */
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#define RCC_APB1ENR_FDCANEN (1 << 11) /* Bit 11: FDCAN clock enable */
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/* Bit 12: Reserved */
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#define RCC_APB1ENR_FDCANEN (1 << 12) /* Bit 12: FDCAN clock enable */
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#define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB clock enable */
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#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
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#define RCC_APB1ENR_USBEN (1 << 15) /* Bit 15: USB clock enable */
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#define RCC_APB1ENR_CRCEN (1 << 16) /* Bit 15: CRC clock enable */
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/* Bit 15: Reserved */
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#define RCC_APB1ENR_CRCEN (1 << 16) /* Bit 16: CRC clock enable */
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#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
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#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
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#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */
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@@ -326,6 +326,35 @@
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/* TODO: APB1 peripheral clock enable in Sleep mode register */
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/* RCC peripherals independent clock configuration register 1 */
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#define RCC_CCIPR1_USART1SEL_SHIFT (0) /* Bits 0-1: USART1 clock source selection */
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# define RCC_CCIPR1_USART1SEL_PCLK (0 << RCC_CCIPR1_USART1SEL_SHIFT)
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# define RCC_CCIPR1_USART1SEL_SYSCLK (1 << RCC_CCIPR1_USART1SEL_SHIFT)
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# define RCC_CCIPR1_USART1SEL_HSIKER (2 << RCC_CCIPR1_USART1SEL_SHIFT)
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# define RCC_CCIPR1_USART1SEL_LSE (3 << RCC_CCIPR1_USART1SEL_SHIFT)
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#define RCC_CCIPR1_FDCAN1SEL_SHIFT (8) /* Bits 8-9: FDCAN1 clock source selection */
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# define RCC_CCIPR1_FDCAN1SEL_PCLK (0 << RCC_CCIPR1_FDCAN1SEL_SHIFT)
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# define RCC_CCIPR1_FDCAN1SEL_SYSCLK (1 << RCC_CCIPR1_FDCAN1SEL_SHIFT)
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# define RCC_CCIPR1_FDCAN1SEL_HSIKER (2 << RCC_CCIPR1_FDCAN1SEL_SHIFT)
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#define RCC_CCIPR1_I2C1SEL_SHIFT (12) /* Bits 12-13: I2C1 clock source selection */
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# define RCC_CCIPR1_I2C1SEL_PCLK (0 << RCC_CCIPR1_I2C1SEL_SHIFT)
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# define RCC_CCIPR1_I2C1SEL_SYSCLK (1 << RCC_CCIPR1_I2C1SEL_SHIFT)
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# define RCC_CCIPR1_I2C1SEL_HSIKER (2 << RCC_CCIPR1_I2C1SEL_SHIFT)
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#define RCC_CCIPR1_I2S1SEL_SHIFT (14) /* Bits 14-15: I2S1 clock source selection */
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# define RCC_CCIPR1_I2S1SEL_PCLK (0 << RCC_CCIPR1_I2S1SEL_SHIFT)
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# define RCC_CCIPR1_I2S1SEL_HSIKER (2 << RCC_CCIPR1_I2S1SEL_SHIFT)
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# define RCC_CCIPR1_I2S1SEL_I2S (3 << RCC_CCIPR1_I2S1SEL_SHIFT)
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#define RCC_CCIPR1_ADC1SEL_SHIFT (30) /* Bits 30-31: ADC1 clock source selection */
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# define RCC_CCIPR1_ADC1SEL_SYSCLK (0 << RCC_CCIPR1_ADC1SEL_SHIFT)
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# define RCC_CCIPR1_ADC1SEL_HSIKER (2 << RCC_CCIPR1_ADC1SEL_SHIFT)
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/* RCC peripherals independent clock configuration register 2 */
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#define RCC_CCIPR2_USBSEL_SHIFT (12) /* Bit 12: SB clock source selection */
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#define RCC_CCIPR2_USBSEL_HSIUSB48 (0 << RCC_CCIPR2_USBSEL_SHIFT)
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#define RCC_CCIPR2_USBSEL_HSE (1 << RCC_CCIPR2_USBSEL_SHIFT)
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/* Clock configuration register 1 */
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#define RCC_CSR1_LSEON (1 << 0) /* Bit 0: LSE enable */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,112 @@
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/****************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32_fdcan.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H
|
||||
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_fdcan.h"
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Port numbers for use with stm32_fdcan_initialize() */
|
||||
|
||||
#define FDCAN1 1
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fdcaninitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected FDCAN port
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple FDCAN interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid FDCAN device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct can_dev_s *stm32_fdcaninitialize(int port);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fdcansockinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected FDCAN port as SocketCAN interface
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple FDCAN interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_fdcansockinitialize(int port);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -176,7 +176,7 @@ static inline void rcc_enableapb1(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F0L0G0_FDCAN
|
||||
#ifdef CONFIG_STM32F0L0G0_FDCAN1
|
||||
/* FDCAN1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_FDCANEN;
|
||||
@@ -475,6 +475,14 @@ static void stm32_stdclockconfig(void)
|
||||
/* Wait until the selected source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
|
||||
|
||||
#ifdef CONFIG_STM32F0L0G0_FDCAN1
|
||||
/* Configure FDCAN1 clock source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CCIPR1);
|
||||
regval |= STM32_FDCAN1_SEL;
|
||||
putreg32(regval, STM32_RCC_CCIPR1);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user