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Merged in raiden00/nuttx_h7/h7dma (pull request #831)

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Missing definitions and better organistaion for STM32H7 DMA

arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h: rename DMA channel definitions

arch/arm/src/stm32h7/chip/stm32_dma: separated files for MDMA, DMA, BDMA and DMAMUX

arch/arm/src/stm32h7/chip/stm32_dma: missing definitions for MDMA, BDMA and DMAMUX

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
2019-02-25 16:02:39 +00:00
committed by Gregory Nutt
parent 9a5134acac
commit b9ef70ed0f
8 changed files with 1640 additions and 1257 deletions
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arch/arm/src/stm32/chip/stm32_dma_v1.h
+12 -7
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@@ -49,16 +49,21 @@
#undef DMA_HAVE_CSELR
/* 2 DMA controllers */
#define DMA1 (0)
#define DMA2 (1)
/* These definitions apply to both the STM32 F1 and F3 families */
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
#define DMA_CHAN1 (0)
#define DMA_CHAN2 (1)
#define DMA_CHAN3 (2)
#define DMA_CHAN4 (3)
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
/* Register Offsets *****************************************************************/
arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
+12 -7
View File
@@ -51,15 +51,20 @@
# define DMA_HAVE_CSELR 1
#endif
/* 2 DMA controllers */
#define DMA1 (0)
#define DMA2 (1)
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
#define DMA1 0
#define DMA2 1
#define DMA3 2
#define DMA4 3
#define DMA5 4
#define DMA6 5
#define DMA7 6
#define DMA_CHAN1 (0)
#define DMA_CHAN2 (1)
#define DMA_CHAN3 (2)
#define DMA_CHAN4 (3)
#define DMA_CHAN5 (4)
#define DMA_CHAN6 (5)
#define DMA_CHAN7 (6)
/* Register Offsets *****************************************************************/
arch/arm/src/stm32h7/chip/stm32_bdma.h
+256
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@@ -0,0 +1,256 @@
/************************************************************************************
* arch/arm/src/stm32h7/chip/stm32_bdma.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_BDMA_ISR_OFFSET 0x0000 /* BDMA interrupt status register */
#define STM32_BDMA_IFCR_OFFSET 0x0004 /* BDMA interrupt flag clear register */
#define STM32_BDMA_CCRX_OFFSET(x) (0x0008+(x*0x0014)) /* BDMA channel x configuration register */
#define STM32_BDMA_CCR0_OFFSET STM32_BDMA_CCRX_OFFSET(0)
#define STM32_BDMA_CCR1_OFFSET STM32_BDMA_CCRX_OFFSET(1)
#define STM32_BDMA_CCR2_OFFSET STM32_BDMA_CCRX_OFFSET(2)
#define STM32_BDMA_CCR3_OFFSET STM32_BDMA_CCRX_OFFSET(3)
#define STM32_BDMA_CCR4_OFFSET STM32_BDMA_CCRX_OFFSET(4)
#define STM32_BDMA_CCR5_OFFSET STM32_BDMA_CCRX_OFFSET(5)
#define STM32_BDMA_CCR6_OFFSET STM32_BDMA_CCRX_OFFSET(6)
#define STM32_BDMA_CCR7_OFFSET STM32_BDMA_CCRX_OFFSET(7)
#define STM32_BDMA_CNDTRX_OFFSET(x) (0x000C+(x*0x0014)) /* BDMA channel x number of data to transfer register */
#define STM32_BDMA_CNDTR0_OFFSET STM32_BDMA_CNDTRX_OFFSET(0)
#define STM32_BDMA_CNDTR1_OFFSET STM32_BDMA_CNDTRX_OFFSET(1)
#define STM32_BDMA_CNDTR2_OFFSET STM32_BDMA_CNDTRX_OFFSET(2)
#define STM32_BDMA_CNDTR3_OFFSET STM32_BDMA_CNDTRX_OFFSET(3)
#define STM32_BDMA_CNDTR4_OFFSET STM32_BDMA_CNDTRX_OFFSET(4)
#define STM32_BDMA_CNDTR5_OFFSET STM32_BDMA_CNDTRX_OFFSET(5)
#define STM32_BDMA_CNDTR6_OFFSET STM32_BDMA_CNDTRX_OFFSET(6)
#define STM32_BDMA_CNDTR7_OFFSET STM32_BDMA_CNDTRX_OFFSET(7)
#define STM32_BDMA_CPARX_OFFSET(x) (0x0010+(x*0x0014)) /* BDMA channel x peripheral address register */
#define STM32_BDMA_CPAR0_OFFSET STM32_BDMA_CPARX_OFFSET(0)
#define STM32_BDMA_CPAR1_OFFSET STM32_BDMA_CPARX_OFFSET(1)
#define STM32_BDMA_CPAR2_OFFSET STM32_BDMA_CPARX_OFFSET(2)
#define STM32_BDMA_CPAR3_OFFSET STM32_BDMA_CPARX_OFFSET(3)
#define STM32_BDMA_CPAR4_OFFSET STM32_BDMA_CPARX_OFFSET(4)
#define STM32_BDMA_CPAR5_OFFSET STM32_BDMA_CPARX_OFFSET(5)
#define STM32_BDMA_CPAR6_OFFSET STM32_BDMA_CPARX_OFFSET(6)
#define STM32_BDMA_CPAR7_OFFSET STM32_BDMA_CPARX_OFFSET(7)
#define STM32_BDMA_CM0ARX_OFFSET(x) (0x0014+(x*0x0014)) /* BDMA channel x memory 0 address register */
#define STM32_BDMA_CM0AR0_OFFSET STM32_BDMA_CM0ARX_OFFSET(0)
#define STM32_BDMA_CM0AR1_OFFSET STM32_BDMA_CM0ARX_OFFSET(1)
#define STM32_BDMA_CM0AR2_OFFSET STM32_BDMA_CM0ARX_OFFSET(2)
#define STM32_BDMA_CM0AR3_OFFSET STM32_BDMA_CM0ARX_OFFSET(3)
#define STM32_BDMA_CM0AR4_OFFSET STM32_BDMA_CM0ARX_OFFSET(4)
#define STM32_BDMA_CM0AR5_OFFSET STM32_BDMA_CM0ARX_OFFSET(5)
#define STM32_BDMA_CM0AR6_OFFSET STM32_BDMA_CM0ARX_OFFSET(6)
#define STM32_BDMA_CM0AR7_OFFSET STM32_BDMA_CM0ARX_OFFSET(7)
#define STM32_BDMA_CM1ARX_OFFSET(x) (0x0018+(x*0x0014)) /* BDMA channel x memory 1 address register */
#define STM32_BDMA_CM1AR0_OFFSET STM32_BDMA_CM1ARX_OFFSET(0)
#define STM32_BDMA_CM1AR1_OFFSET STM32_BDMA_CM1ARX_OFFSET(1)
#define STM32_BDMA_CM1AR2_OFFSET STM32_BDMA_CM1ARX_OFFSET(2)
#define STM32_BDMA_CM1AR3_OFFSET STM32_BDMA_CM1ARX_OFFSET(3)
#define STM32_BDMA_CM1AR4_OFFSET STM32_BDMA_CM1ARX_OFFSET(4)
#define STM32_BDMA_CM1AR5_OFFSET STM32_BDMA_CM1ARX_OFFSET(5)
#define STM32_BDMA_CM1AR6_OFFSET STM32_BDMA_CM1ARX_OFFSET(6)
#define STM32_BDMA_CM1AR7_OFFSET STM32_BDMA_CM1ARX_OFFSET(7)
/* Register Addresses ***************************************************************/
#define STM32_BDMA_ISR (STM32_BDMA_BASE+STM32_BDMA_ISR_OFFSET)
#define STM32_BDMA_IFCR (STM32_BDMA_BASE+STM32_BDMA_IFCR_OFFSET)
#define STM32_BDMA_CCRX(x) (STM32_BDMA_BASE+STM32_BDMA_CCRX_OFFSET(x))
#define STM32_BDMA_CCR0 (STM32_BDMA_BASE+STM32_BDMA_CCR0_OFFSET)
#define STM32_BDMA_CCR1 (STM32_BDMA_BASE+STM32_BDMA_CCR1_OFFSET)
#define STM32_BDMA_CCR2 (STM32_BDMA_BASE+STM32_BDMA_CCR2_OFFSET)
#define STM32_BDMA_CCR3 (STM32_BDMA_BASE+STM32_BDMA_CCR3_OFFSET)
#define STM32_BDMA_CCR4 (STM32_BDMA_BASE+STM32_BDMA_CCR4_OFFSET)
#define STM32_BDMA_CCR5 (STM32_BDMA_BASE+STM32_BDMA_CCR5_OFFSET)
#define STM32_BDMA_CCR6 (STM32_BDMA_BASE+STM32_BDMA_CCR6_OFFSET)
#define STM32_BDMA_CCR7 (STM32_BDMA_BASE+STM32_BDMA_CCR7_OFFSET)
#define STM32_BDMA_CNDTRX(x) (STM32_BDMA_BASE+STM32_BDMA_CNDTRX_OFFSET(x))
#define STM32_BDMA_CNDTR0 (STM32_BDMA_BASE+STM32_BDMA_CNDTR0_OFFSET)
#define STM32_BDMA_CNDTR1 (STM32_BDMA_BASE+STM32_BDMA_CNDTR1_OFFSET)
#define STM32_BDMA_CNDTR2 (STM32_BDMA_BASE+STM32_BDMA_CNDTR2_OFFSET)
#define STM32_BDMA_CNDTR3 (STM32_BDMA_BASE+STM32_BDMA_CNDTR3_OFFSET)
#define STM32_BDMA_CNDTR4 (STM32_BDMA_BASE+STM32_BDMA_CNDTR4_OFFSET)
#define STM32_BDMA_CNDTR5 (STM32_BDMA_BASE+STM32_BDMA_CNDTR5_OFFSET)
#define STM32_BDMA_CNDTR6 (STM32_BDMA_BASE+STM32_BDMA_CNDTR6_OFFSET)
#define STM32_BDMA_CNDTR7 (STM32_BDMA_BASE+STM32_BDMA_CNDTR7_OFFSET)
#define STM32_BDMA_CPARX(x) (STM32_BDMA_BASE+STM32_BDMA_CPARX_OFFSET(x))
#define STM32_BDMA_CPAR0 (STM32_BDMA_BASE+STM32_BDMA_CPAR0_OFFSET)
#define STM32_BDMA_CPAR1 (STM32_BDMA_BASE+STM32_BDMA_CPAR1_OFFSET)
#define STM32_BDMA_CPAR2 (STM32_BDMA_BASE+STM32_BDMA_CPAR2_OFFSET)
#define STM32_BDMA_CPAR3 (STM32_BDMA_BASE+STM32_BDMA_CPAR3_OFFSET)
#define STM32_BDMA_CPAR4 (STM32_BDMA_BASE+STM32_BDMA_CPAR4_OFFSET)
#define STM32_BDMA_CPAR5 (STM32_BDMA_BASE+STM32_BDMA_CPAR5_OFFSET)
#define STM32_BDMA_CPAR6 (STM32_BDMA_BASE+STM32_BDMA_CPAR6_OFFSET)
#define STM32_BDMA_CPAR7 (STM32_BDMA_BASE+STM32_BDMA_CPAR7_OFFSET)
#define STM32_BDMA_CM0ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM0ARX_OFFSET(x))
#define STM32_BDMA_CM0AR0 (STM32_BDMA_BASE+STM32_BDMA_CM0AR0_OFFSET)
#define STM32_BDMA_CM0AR1 (STM32_BDMA_BASE+STM32_BDMA_CM0AR1_OFFSET)
#define STM32_BDMA_CM0AR2 (STM32_BDMA_BASE+STM32_BDMA_CM0AR2_OFFSET)
#define STM32_BDMA_CM0AR3 (STM32_BDMA_BASE+STM32_BDMA_CM0AR3_OFFSET)
#define STM32_BDMA_CM0AR4 (STM32_BDMA_BASE+STM32_BDMA_CM0AR4_OFFSET)
#define STM32_BDMA_CM0AR5 (STM32_BDMA_BASE+STM32_BDMA_CM0AR5_OFFSET)
#define STM32_BDMA_CM0AR6 (STM32_BDMA_BASE+STM32_BDMA_CM0AR6_OFFSET)
#define STM32_BDMA_CM0AR7 (STM32_BDMA_BASE+STM32_BDMA_CM0AR7_OFFSET)
#define STM32_BDMA_CM1ARX(x) (STM32_BDMA_BASE+STM32_BDMA_CM1ARX_OFFSET(x))
#define STM32_BDMA_CM1AR0 (STM32_BDMA_BASE+STM32_BDMA_CM1AR0_OFFSET)
#define STM32_BDMA_CM1AR1 (STM32_BDMA_BASE+STM32_BDMA_CM1AR1_OFFSET)
#define STM32_BDMA_CM1AR2 (STM32_BDMA_BASE+STM32_BDMA_CM1AR2_OFFSET)
#define STM32_BDMA_CM1AR3 (STM32_BDMA_BASE+STM32_BDMA_CM1AR3_OFFSET)
#define STM32_BDMA_CM1AR4 (STM32_BDMA_BASE+STM32_BDMA_CM1AR4_OFFSET)
#define STM32_BDMA_CM1AR5 (STM32_BDMA_BASE+STM32_BDMA_CM1AR5_OFFSET)
#define STM32_BDMA_CM1AR6 (STM32_BDMA_BASE+STM32_BDMA_CM1AR6_OFFSET)
#define STM32_BDMA_CM1AR7 (STM32_BDMA_BASE+STM32_BDMA_CM1AR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define BDMA_CHAN_SHIFT(n) ((n) << 2)
#define BDMA_CHAN_MASK 0xf
#define BDMA_CHAN_CGIF (1 << 0) /* Bit 0: Global interrupt flag */
#define BDMA_CHAN_TCIF (1 << 1) /* Bit 1: Transfer complete flag */
#define BDMA_CHAN_HTIF (1 << 2) /* Bit 2: half transfer complete flag */
#define BDMA_CHAN_TEIF (1 << 3) /* Bit 3: Transfer error flag */
/* BDMA interrupt status register */
#define BDMA_ISR_CHAN_SHIFT(n) BDMA_CHAN_SHIFT(n)
#define BDMA_ISR_CHAN_MASK(n) (BDMA_CHAN_MASK << BDMA_ISR_CHAN_SHIFT(n))
#define BDMA_ISR_CHAN0_SHIFT (0) /* Bits 3-0: BDMA Channel 0 interrupt status */
#define BDMA_ISR_CHAN0_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN1_SHIFT)
#define BDMA_ISR_CHAN1_SHIFT (4) /* Bits 7-4: BDMA Channel 1 interrupt status */
#define BDMA_ISR_CHAN1_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN2_SHIFT)
#define BDMA_ISR_CHAN2_SHIFT (8) /* Bits 11-8: BDMA Channel 2 interrupt status */
#define BDMA_ISR_CHAN2_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN3_SHIFT)
#define BDMA_ISR_CHAN3_SHIFT (12) /* Bits 15-12: BDMA Channel 3 interrupt status */
#define BDMA_ISR_CHAN3_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN4_SHIFT)
#define BDMA_ISR_CHAN4_SHIFT (16) /* Bits 19-16: BDMA Channel 4 interrupt status */
#define BDMA_ISR_CHAN4_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN5_SHIFT)
#define BDMA_ISR_CHAN5_SHIFT (20) /* Bits 23-20: BDMA Channel 5 interrupt status */
#define BDMA_ISR_CHAN5_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN6_SHIFT)
#define BDMA_ISR_CHAN6_SHIFT (24) /* Bits 27-24: BDMA Channel 6 interrupt status */
#define BDMA_ISR_CHAN6_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN7_SHIFT)
#define BDMA_ISR_CHAN7_SHIFT (28) /* Bits 31-28: BDMA Channel 7 interrupt status */
#define BDMA_ISR_CHAN7_MASK (BDMA_CHAN_MASK << BDMA_ISR_CHAN7_SHIFT)
#define BDMA_ISR_CGIF(n) (BDMA_CHAN_CGIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
#define BDMA_ISR_TCIF(n) (BDMA_CHAN_TCIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
#define BDMA_ISR_HTIF(n) (BDMA_CHAN_HTIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
#define BDMA_ISR_TEIF(n) (BDMA_CHAN_TEIF_BIT << BDMA_ISR_CHAN_SHIFT(n))
/* BDMA interrupt flag clear register */
#define BDMA_IFCR_CHAN_SHIFT(n) BDMA_CHAN_SHIFT(n)
#define BDMA_IFCR_CHAN_MASK(n) (BDMA_CHAN_MASK << BDMA_IFCR_CHAN_SHIFT(n))
#define BDMA_IFCR_CHAN0_SHIFT (0) /* Bits 3-0: BDMA Channel 0 interrupt status */
#define BDMA_IFCR_CHAN0_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN1_SHIFT)
#define BDMA_IFCR_CHAN1_SHIFT (4) /* Bits 7-4: BDMA Channel 1 interrupt status */
#define BDMA_IFCR_CHAN1_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN2_SHIFT)
#define BDMA_IFCR_CHAN2_SHIFT (8) /* Bits 11-8: BDMA Channel 2 interrupt status */
#define BDMA_IFCR_CHAN2_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN3_SHIFT)
#define BDMA_IFCR_CHAN3_SHIFT (12) /* Bits 15-12: BDMA Channel 3 interrupt status */
#define BDMA_IFCR_CHAN3_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN4_SHIFT)
#define BDMA_IFCR_CHAN4_SHIFT (16) /* Bits 19-16: BDMA Channel 4 interrupt status */
#define BDMA_IFCR_CHAN4_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN5_SHIFT)
#define BDMA_IFCR_CHAN5_SHIFT (20) /* Bits 23-20: BDMA Channel 5 interrupt status */
#define BDMA_IFCR_CHAN5_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN6_SHIFT)
#define BDMA_IFCR_CHAN6_SHIFT (24) /* Bits 27-24: BDMA Channel 6 interrupt status */
#define BDMA_IFCR_CHAN6_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN7_SHIFT)
#define BDMA_IFCR_CHAN7_SHIFT (28) /* Bits 31-28: BDMA Channel 7 interrupt status */
#define BDMA_IFCR_CHAN7_MASK (BDMA_CHAN_MASK << BDMA_IFCR_CHAN7_SHIFT)
#define BDMA_IFCR_CGIF(n) (BDMA_CHAN_CGIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
#define BDMA_IFCR_TCIF(n) (BDMA_CHAN_TCIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
#define BDMA_IFCR_HTIF(n) (BDMA_CHAN_HTIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
#define BDMA_IFCR_TEIF(n) (BDMA_CHAN_TEIF_BIT << BDMA_IFCR_CHAN_SHIFT(n))
/* BDMA channel x configuration register */
#define BDMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
#define BDMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
#define BDMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
#define BDMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
#define BDMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
#define BDMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
#define BDMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
#define BDMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment */
#define BDMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
#define BDMA_CCR_PSIZE_MASK (3 << BDMA_CCR_PSIZE_SHIFT)
# define BDMA_CCR_PSIZE_8BITS (0 << BDMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
# define BDMA_CCR_PSIZE_16BITS (1 << BDMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
# define BDMA_CCR_PSIZE_32BITS (2 << BDMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
#define BDMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size*/
#define BDMA_CCR_MSIZE_MASK (3 << BDMA_CCR_MSIZE_SHIFT)
# define BDMA_CCR_MSIZE_8BITS (0 << BDMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
# define BDMA_CCR_MSIZE_16BITS (1 << BDMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
# define BDMA_CCR_MSIZE_32BITS (2 << BDMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
#define BDMA_CCR_PL_SHIFT (12) /* Bits 12-13: Priority level */
#define BDMA_CCR_PL_MASK (3 << BDMA_CCR_PL_SHIFT)
# define BDMA_CCR_PRILO (0 << BDMA_CCR_PL_SHIFT) /* 00: Low */
# define BDMA_CCR_PRIMED (1 << BDMA_CCR_PL_SHIFT) /* 01: Medium */
# define BDMA_CCR_PRIHI (2 << BDMA_CCR_PL_SHIFT) /* 10: High */
# define BDMA_CCR_PRIVERYHI (3 << BDMA_CCR_PL_SHIFT) /* 11: Very high */
#define BDMA_CCR_M2M (1 << 14) /* Bit 14: Memory-to-memory mode */
#define BDMA_CCR_DBM (1 << 15) /* Bit 15: dobule buffer mode*/
#define BDMA_CCR_CT (1 << 16) /* Bit 16: Current target */
/* BDMA channel x number of data to transfer register */
#define BDMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define BDMA_CNDTR_NDT_MASK (0xffff << BDMA_CNDTR_NDT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H */
arch/arm/src/stm32h7/chip/stm32_dma.h
+329 -5
View File
@@ -43,10 +43,334 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H7_STM32H7X3XX)
# include "chip/stm32h7x3xx_dma.h"
#else
# error "Unsupported STM32 H7 sub family"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* 2 DMA controllers + 1 MDMA + 1 BDMA*/
#define DMA1 (0)
#define DMA2 (1)
#define MDMA (3)
#define BDMA (4)
/* 8 DMA streams */
#define DMA_STREAM0 (0)
#define DMA_STREAM1 (1)
#define DMA_STREAM2 (2)
#define DMA_STREAM3 (3)
#define DMA_STREAM4 (4)
#define DMA_STREAM5 (5)
#define DMA_STREAM6 (6)
#define DMA_STREAM7 (7)
/* Register Offsets *****************************************************************/
#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */
#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */
#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */
#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */
#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n))
#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */
#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */
#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */
#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */
#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */
#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */
#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */
#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */
#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */
#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */
#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */
#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */
#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */
#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */
#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */
#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */
#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */
#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */
#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */
#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */
#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */
#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */
#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */
#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */
#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */
#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */
#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */
#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */
#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */
#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */
#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */
#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */
#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */
#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */
#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */
#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */
#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */
#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */
#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */
#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */
#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */
#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */
#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */
#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */
#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */
#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */
#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */
#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */
#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */
#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */
#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */
#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */
#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */
#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */
/* Register Addresses ***************************************************************/
#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET)
#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET)
#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET)
#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET)
#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET)
#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET)
#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET)
#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET)
#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET)
#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET)
#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET)
#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET)
#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET)
#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET)
#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET)
#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET)
#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET)
#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET)
#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET)
#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET)
#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET)
#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET)
#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET)
#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET)
#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET)
#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET)
#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET)
#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET)
#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET)
#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET)
#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET)
#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET)
#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET)
#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET)
#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET)
#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET)
#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET)
#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET)
#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET)
#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET)
#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET)
#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET)
#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET)
#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET)
#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET)
#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET)
#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET)
#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET)
#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET)
#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET)
#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET)
#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET)
#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET)
#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET)
#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET)
#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET)
#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET)
#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET)
#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET)
#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET)
#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET)
#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET)
#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET)
#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET)
#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET)
#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET)
#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET)
#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET)
#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET)
#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET)
#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET)
#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET)
#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET)
#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET)
#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET)
#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET)
#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET)
#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET)
#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET)
#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET)
#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET)
#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET)
#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET)
#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET)
#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET)
#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET)
#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET)
#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET)
#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET)
#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET)
#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET)
#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET)
#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET)
#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET)
#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET)
#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET)
#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n))
#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET)
#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET)
#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET)
#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET)
#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET)
#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET)
#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET)
#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define DMA_STREAM_MASK 0x3f
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
/* DMA interrupt status register and interrupt flag clear register field definitions */
#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
/* DMA stream configuration register */
#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */
#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */
#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */
#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */
#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */
#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */
#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */
#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT)
# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */
# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */
# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */
#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */
#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */
#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */
#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */
#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT)
# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */
# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */
# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */
#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */
#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT)
# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */
# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */
# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */
#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */
#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */
#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT)
# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */
# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */
# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */
# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */
#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */
#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */
/* Bit 20: Reserved */
#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */
#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT)
# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */
# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */
# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */
# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */
#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */
#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT)
# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */
# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */
# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */
# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */
/* Bits 25-31: Reserved */
#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE)
/* DMA stream number of data register */
#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
/* DMA stream n FIFO control register */
#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
/* Bit 6: Reserved */
#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
/* Bits 8-31: Reserved */
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H */
arch/arm/src/stm32h7/chip/stm32_dmamux.h
+205
View File
@@ -0,0 +1,205 @@
/************************************************************************************
* arch/arm/src/stm32h7/chip/stm32_dmamux.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0)
#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1)
#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2)
#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3)
#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4)
#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5)
#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6)
#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7)
#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8)
#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9)
#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10)
#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11)
#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12)
#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13)
#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14)
#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15)
/* 0x040-0x07C: Reserved */
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
/* 0x088-0x0FC: Reserved */
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */
/* 0x148-0x3FC: Reserved */
/* Register Addresses ***************************************************************/
#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET)
#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET)
#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET)
#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET)
#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET)
#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
#define STM32_DMAMUX1_C14CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET)
#define STM32_DMAMUX1_C15CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C14CR_OFFSET)
#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
#define STM32_DMAMUX2_CXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
#define STM32_DMAMUX2_C0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C0CR_OFFSET)
#define STM32_DMAMUX2_C1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C1CR_OFFSET)
#define STM32_DMAMUX2_C2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C2CR_OFFSET)
#define STM32_DMAMUX2_C3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C3CR_OFFSET)
#define STM32_DMAMUX2_C4CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C4CR_OFFSET)
#define STM32_DMAMUX2_C5CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C5CR_OFFSET)
#define STM32_DMAMUX2_C6CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C6CR_OFFSET)
#define STM32_DMAMUX2_C7CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C7CR_OFFSET)
#define STM32_DMAMUX2_C8CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C8CR_OFFSET)
#define STM32_DMAMUX2_C9CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C9CR_OFFSET)
#define STM32_DMAMUX2_C10CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C10CR_OFFSET)
#define STM32_DMAMUX2_C11CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C11CR_OFFSET)
#define STM32_DMAMUX2_C12CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET)
#define STM32_DMAMUX2_C13CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C12CR_OFFSET)
#define STM32_DMAMUX2_C14CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C13CR_OFFSET)
#define STM32_DMAMUX2_C15CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_C14CR_OFFSET)
#define STM32_DMAMUX2_CSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CSR_OFFSET)
#define STM32_DMAMUX2_CFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_CFR_OFFSET)
#define STM32_DMAMUX2_RGXCR(x) (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
#define STM32_DMAMUX2_RG0CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG0CR_OFFSET)
#define STM32_DMAMUX2_RG1CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG1CR_OFFSET)
#define STM32_DMAMUX2_RG2CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG2CR_OFFSET)
#define STM32_DMAMUX2_RG3CR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RG3CR_OFFSET)
#define STM32_DMAMUX2_RGSR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGSR_OFFSET)
#define STM32_DMAMUX2_RGCFR (STM32_DMAMUX2_BASE+STM32_DMAMUX_RGCFR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* DMAMUX12 request line multiplexer channel x configuration register */
#define DMAMUX_CXCR_DMAREQID_SHIFT (0) /* Bits 0-6: DMA request identification */
#define DMAMUX_CXCR_DMAREQID_MASK (0x7f << DMAMUX_CXCR_DMAREQID_SHIFT)
#define DMAMUX_CXCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
#define DMAMUX_CXCR_EGE (9) /* Bit 9: Event generation enable */
#define DMAMUX_CXCR_SE (16) /* Bit 16: Synchronization enable */
#define DMAMUX_CXCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
#define DMAMUX_CXCR_SPOL_MASK (3 << DMAMUX_CXCR_SPOL_SHIFT)
#define DMAMUX_CXCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request - 1 to forward */
#define DMAMUX_CXCR_NBREQ_MASK (0x1f << DMAMUX_CXCR_NBREQ_SHIFT)
#define DMAMUX_CXCR_SYNCID_SHIFT (24) /* Bits 24-26: Synchronization identification */
#define DMAMUX_CXCR_SYNCID_MASK (7 << DMAMUX_CXCR_SYNCID_SHIFT)
/* DMAMUX12 request line multiplexer interrupt channel status register */
#define DMAMUX1_CSR_SOF(x) (1 << x) /* Synchronization overrun event flag */
/* DMAMUX12 request line multiplexer interrupt clear flag register */
#define DMAMUX1_CFR_SOF(x) (1 << x) /* Clear synchronization overrun event flag */
/* DMAMUX12 request generator channel x configuration register */
#define DMAMUX_RGXCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
#define DMAMUX_RGXCR_SIGID_MASK (0x1f << DMAMUX_RGXCR_SIGID_SHIFT)
#define DMAMUX_RGXCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
#define DMAMUX_RGXCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
#define DMAMUX_RGXCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
#define DMAMUX_RGXCR_GPOL_MASK (7 << DMAMUX_RGXCR_GPOL_SHIFT)
#define DMAMUX_RGXCR_GNBREQ_SHIFT (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
#define DMAMUX_RGXCR_GNBREQL_MASK (7 << DMAMUX_RGXCR_GNBREQ_SHIFT)
/* DMAMUX12 request generator interrupt status register */
#define DMAMUX1_RGSR_SOF(x) (1 << x) /* Trigger overrun event flag */
/* DMAMUX12 request generator interrupt clear flag register */
#define DMAMUX1_RGCFR_SOF(x) (1 << x) /* Clear trigger overrun event flag */
/* DMA Stream mapping.
* TODO:
*/
#define STM32_DMA_MAP(d,s,c) ((d) << 7 | (s) << 4 | (c))
#define STM32_DMA_CONTROLLER(m) (((m) >> 7) & 1)
#define STM32_DMA_STREAM(m) (((m) >> 4) & 7)
#define STM32_DMA_CHANNEL(m) ((m) & 15)
/* Import DMAMUX map */
#if defined(CONFIG_STM32H7_STM32H7X3XX)
# include "chip/stm32h7x3xx_dmamux.h"
#else
# error "Unsupported STM32 H7 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H */
arch/arm/src/stm32h7/chip/stm32_mdma.h
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arch/arm/src/stm32h7/chip/stm32h7x3xx_dma.h
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arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
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/************************************************************************************
* arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* DMAMUX1 mapping ****************************************************/
/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7.
* DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7.
*/
#define DMAMUX1_REQ_GEN0 (1)
#define DMAMUX1_REQ_GEN1 (2)
#define DMAMUX1_REQ_GEN2 (3)
#define DMAMUX1_REQ_GEN3 (4)
#define DMAMUX1_REQ_GEN4 (5)
#define DMAMUX1_REQ_GEN5 (6)
#define DMAMUX1_REQ_GEN6 (7)
#define DMAMUX1_REQ_GEN7 (8)
#define DMAMUX1_ADC1 (9)
#define DMAMUX1_ADC2 (10)
#define DMAMUX1_TIM1_CH1 (11)
#define DMAMUX1_TIM1_CH2 (12)
#define DMAMUX1_TIM1_CH3 (13)
#define DMAMUX1_TIM1_CH4 (14)
#define DMAMUX1_TIM1_UP (15)
#define DMAMUX1_TIM1_TRIG (16)
#define DMAMUX1_TIM1_COM (17)
#define DMAMUX1_TIM2_CH1 (18)
#define DMAMUX1_TIM2_CH2 (19)
#define DMAMUX1_TIM2_CH3 (20)
#define DMAMUX1_TIM2_CH4 (21)
#define DMAMUX1_TIM2_UP (22)
#define DMAMUX1_TIM3_CH1 (23)
#define DMAMUX1_TIM3_CH2 (24)
#define DMAMUX1_TIM3_CH3 (25)
#define DMAMUX1_TIM3_CH4 (26)
#define DMAMUX1_TIM3_UP (27)
#define DMAMUX1_TIM3_TRIG (28)
#define DMAMUX1_TIM4_CH1 (29)
#define DMAMUX1_TIM4_CH2 (30)
#define DMAMUX1_TIM4_CH3 (31)
#define DMAMUX1_TIM4_UP (32)
#define DMAMUX1_I2C1_RX (33)
#define DMAMUX1_I2C1_TX (34)
#define DMAMUX1_I2C2_RX (35)
#define DMAMUX1_I2C2_TX (36)
#define DMAMUX1_SPI1_RX (37)
#define DMAMUX1_SPI1_TX (38)
#define DMAMUX1_SPI2_RX (39)
#define DMAMUX1_SPI2_TX (40)
#define DMAMUX1_USART1_TX (41)
#define DMAMUX1_USART1_RX (42)
#define DMAMUX1_USART2_RX (43)
#define DMAMUX1_USART2_TX (44)
#define DMAMUX1_USART3_RX (45)
#define DMAMUX1_USART3_TX (46)
#define DMAMUX1_TIM8_CH1 (47)
#define DMAMUX1_TIM8_CH2 (48)
#define DMAMUX1_TIM8_CH3 (49)
#define DMAMUX1_TIM8_CH4 (50)
#define DMAMUX1_TIM8_UP (51)
#define DMAMUX1_TIM8_TRIG (52)
#define DMAMUX1_TIM8_COM (53)
/* DMAMUX1 54: Reserved */
#define DMAMUX1_TIM5_CH1 (55)
#define DMAMUX1_TIM5_CH2 (56)
#define DMAMUX1_TIM5_CH3 (57)
#define DMAMUX1_TIM5_CH4 (58)
#define DMAMUX1_TIM5_UP (59)
#define DMAMUX1_TIM5_TRIG (60)
#define DMAMUX1_SPI3_RX (61)
#define DMAMUX1_SPI3_TX (62)
#define DMAMUX1_UART4_RX (63)
#define DMAMUX1_UART4_TX (64)
#define DMAMUX1_UART5_RX (65)
#define DMAMUX1_UART5_TX (66)
#define DMAMUX1_DAC_CH1 (67)
#define DMAMUX1_DAC_CH2 (68)
#define DMAMUX1_TIM6_UP (69)
#define DMAMUX1_TIM7_UP (70)
#define DMAMUX1_USART6_RX (71)
#define DMAMUX1_USART6_TX (72)
#define DMAMUX1_I2C3_RX (73)
#define DMAMUX1_I2C3_TX (74)
#define DMAMUX1_DCMI (75)
#define DMAMUX1_CRYPT_IN (76)
#define DMAMUX1_CRYPT_OUT (77)
#define DMAMUX1_HASH_IN (78)
#define DMAMUX1_UART7_RX (70)
#define DMAMUX1_UART7_TX (80)
#define DMAMUX1_UART8_RX (81)
#define DMAMUX1_UART8_TX (82)
#define DMAMUX1_SPI4_RX (83)
#define DMAMUX1_SPI4_TX (84)
#define DMAMUX1_SPI5_RX (85)
#define DMAMUX1_SPI5_TX (86)
#define DMAMUX1_SAI1A (87)
#define DMAMUX1_SAI1B (88)
#define DMAMUX1_SAI2A (89)
#define DMAMUX1_SAI2B (90)
#define DMAMUX1_SWPMI_RX (91)
#define DMAMUX1_SWPMI_TX (92)
#define DMAMUX1_SPDIFRX_DAT (93)
#define DMAMUX1_SPDIFRX_CTRL (94)
#define DMAMUX1_HR_REQ1 (95)
#define DMAMUX1_HR_REQ2 (96)
#define DMAMUX1_HR_REQ3 (97)
#define DMAMUX1_HR_REQ4 (98)
#define DMAMUX1_HR_REQ5 (99)
#define DMAMUX1_HR_REQ6 (100)
#define DMAMUX1_DFSDM1_0 (101)
#define DMAMUX1_DFSDM1_1 (102)
#define DMAMUX1_DFSDM1_2 (103)
#define DMAMUX1_DFSDM1_3 (104)
#define DMAMUX1_TIM15_CH1 (105)
#define DMAMUX1_TIM15_UP (106)
#define DMAMUX1_TIM15_TRIG (107)
#define DMAMUX1_TIM15_COM (108)
#define DMAMUX1_TIM16_CH1 (109)
#define DMAMUX1_TIM16_UP (110)
#define DMAMUX1_TIM17_CH1 (111)
#define DMAMUX1_TIM17_UP (112)
#define DMAMUX1_SAI3A (113)
#define DMAMUX1_SAI3B (114)
#define DMAMUX1_ADC3 (115)
/* DMAMUX1 116-127: Reserved */
/* DMAMUX2 mapping ****************************************************/
/* NOTE: DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7 */
#define DMAMUX2_REQ_GEN0 (1)
#define DMAMUX2_REQ_GEN1 (2)
#define DMAMUX2_REQ_GEN2 (3)
#define DMAMUX2_REQ_GEN3 (4)
#define DMAMUX2_REQ_GEN4 (5)
#define DMAMUX2_REQ_GEN5 (6)
#define DMAMUX2_REQ_GEN6 (7)
#define DMAMUX2_REQ_GEN7 (8)
#define DMAMUX2_LPUART1_RX (9)
#define DMAMUX2_LPUART1_TX (10)
#define DMAMUX2_SPI6_RX (11)
#define DMAMUX2_SPI6_TX (12)
#define DMAMUX2_I2C4_RX (13)
#define DMAMUX2_I2C4_TX (14)
#define DMAMUX2_SAI4A (15)
#define DMAMUX2_SAI4B (16)
#define DMAMUX2_ADC3 (17)
/* DMAMUX2 18-32: Reserved */
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H */