Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-23 06:39:01 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

More progress on the STM32 OTG FS device driver

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4558 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-04-05 14:12:41 +00:00
parent bdf6434f72
commit b8f24208a6
6 changed files with 317 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/NuttX.html
+1 -1
View File
@@ -2912,7 +2912,7 @@ NxWidgets-1.0 2012-03-22 Gregory Nutt <gnutt@nuttx.org>
* This is the initial release of NxWidgets, the C++ graphics package for NuttX.
pascal-1.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org>
pascal-3.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org>
* nuttx/: The Pascal add-on module now installs and builds under the
apps/interpreters directory. This means that the pascal-2.1 module is
arch/arm/src/stm32/chip/stm32_usbotgfs.h → arch/arm/src/stm32/chip/stm32_otgfs.h
+18 -23
View File
@@ -1,5 +1,5 @@
/****************************************************************************************************
* arch/arm/src/stm32/chip/stm32_usbotgfs.h
* arch/arm/src/stm32/chip/stm32_otgfs.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H
/****************************************************************************************************
* Included Files
@@ -83,10 +83,10 @@
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
#define STM32_OTGFS_HCCHAR_OFFSET 0x0000 /* Host channel characteristics register */
#define STM32_OTGFS_HCINT_OFFSET 0x0008 /* Host channel interrupt register */
#define STM32_OTGFS_HCINTMSK_OFFSET 0x000c /* Host channel interrupt mask register */
#define STM32_OTGFS_HCTSIZ_OFFSET 0x0010 /* Host channel interrupt register */
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */
@@ -142,10 +142,10 @@
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGFS_DIEPCTL_OFFSET 0x0900 /* Device endpoint control register */
#define STM32_OTGFS_DIEPINT_OFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTGFS_DIEPTSIZ_OFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32_OTGFS_DTXFSTS_OFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */
@@ -171,9 +171,9 @@
#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 transfer size register */
#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 transfer size register */
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL_OFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTGFS_DOEPINT_OFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32_OTGFS_DOEP_OFFSET(n) 0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */
@@ -304,10 +304,6 @@
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
#define STM32_OTGFS_DIEPCTL (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET)
#define STM32_OTGFS_DIEPINT (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET)
#define STM32_OTGFS_DIEPTSIZ (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET)
#define STM32_OTGFS_DTXFSTS (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET)
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
#define STM32_OTGFS_DIEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET)
@@ -497,7 +493,7 @@
# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
/* Bits 21-31: Reserved, must be kept at reset value.
/* Bits 21-31: Reserved, must be kept at reset value */
/* Receive status debug read/OTG status read and pop registers (device mode) */
#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
@@ -519,7 +515,7 @@
# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-31: Reserved, must be kept at reset value.
/* Bits 25-31: Reserved, must be kept at reset value */
/* Receive FIFO size register */
#define OTGFS_GRXFSIZ_MASK (0xffff)
@@ -717,7 +713,6 @@
# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT)
# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT)
/* Bit 31 Reserved, must be kept at reset value */
/* Device-mode control and status registers */
/* Device configuration register */
@@ -734,7 +729,7 @@
# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTGFS_DCFG_PFIVL_85PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bits 13-31 Reserved, must be kept at reset value */
/* Device control register */
@@ -996,4 +991,4 @@
#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
/* Bits 5-31: Reserved, must be kept at reset value */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBOTG_H */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H */
arch/arm/src/stm32/stm32_otgfs.h
+93
View File
@@ -0,0 +1,93 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_otgfs.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H
#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "stm32.h"
#include "chip/stm32_otgfs.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGFS_PRI
# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver
* is used. This function is called whenever the USB enters or leaves suspend
* mode. This is an opportunity for the board logic to shutdown clocks, power,
* etc. while the USB is suspended.
*
************************************************************************************/
EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */
arch/arm/src/stm32/stm32_otgfsdev.c
+203 -162
View File
File diff suppressed because it is too large Load Diff
configs/stm3240g-eval/src/up_usbdev.c
+1 -19
View File
@@ -79,30 +79,12 @@ void stm32_usbinitialize(void)
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32_OTGFS
stm32_configgpio(GPIO_USB_PULLUP);
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/************************************************************************************
* Name: stm32_usbpullup
*
* Description:
* If USB is supported and the board supports a pullup via GPIO (for USB software
* connect and disconnect), then the board software must provide stm32_pullup.
* See include/nuttx/usb/usbdev.h for additional description of this method.
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
* NULL.
*
************************************************************************************/
int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
{
usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
return OK;
}
/************************************************************************************
* Name: stm32_usbsuspend
*
configs/stm32f4discovery/src/up_usbdev.c
+1 -19
View File
@@ -79,30 +79,12 @@ void stm32_usbinitialize(void)
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32_OTGFS
stm32_configgpio(GPIO_USB_PULLUP);
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/************************************************************************************
* Name: stm32_usbpullup
*
* Description:
* If USB is supported and the board supports a pullup via GPIO (for USB software
* connect and disconnect), then the board software must provide stm32_pullup.
* See include/nuttx/usb/usbdev.h for additional description of this method.
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
* NULL.
*
************************************************************************************/
int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable)
{
usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
return OK;
}
/************************************************************************************
* Name: stm32_usbsuspend
*