SAMV7 QSPI: Add DMA transfer support

arch/arm/src/samv7/Kconfig

@@ -512,7 +512,6 @@ config SAMV7_GPIOE_IRQ
 	default n
 
 endif # SAMV7_GPIO_IRQ
-endif # ARCH_CHIP_SAMV7
 
 menu "SDRAM Configuration"
 	depends on SAMV7_SDRAMC
@@ -628,7 +627,46 @@ config SAMV7_SPI_REGDEBUG
 		Output detailed register-level SPI device debug information.
 		Requires also DEBUG.
 
-endmenu # SAMV7 SPI device driver options
+endmenu # SPI device driver options
+
+menu "QSPI Device Driver Configuration"
+	depends on SAMV7_QSPI && !SAMV7_QSPI_IS_SPI
+
+config SAMV7_QSPI_DMA
+	bool "QSPI DMA"
+	default n
+	depends on SAMV7_XDMAC
+	---help---
+		Use DMA to improve SPI transfer performance.
+
+config SAMV7_QSPI_DMATHRESHOLD
+	int "QSPI DMA threshold"
+	default 4
+	depends on SAMV7_QSPI_DMA
+	---help---
+		When ASPI DMA is enabled, small DMA transfers will still be performed
+		by polling logic.  But we need a threshold value to determine what
+		is small.  That value is provided by SAMV7_QSPI_DMATHRESHOLD.
+
+config SAMV7_QSPI_DMADEBUG
+	bool "QSPI DMA transfer debug"
+	depends on SAMV7_QSPI_DMA && DEBUG && DEBUG_DMA
+	default n
+	---help---
+		Enable special debug instrumentation analyze QSPI DMA data transfers.
+		This logic is as non-invasive as possible:  It samples DMA
+		registers at key points in the data transfer and then dumps all of
+		the registers at the end of the transfer.
+
+config SAMV7_QSPI_REGDEBUG
+	bool "QSPI Register level debug"
+	depends on DEBUG
+	default n
+	---help---
+		Output detailed register-level QSPI device debug information.
+		Requires also DEBUG.
+
+endmenu # QSPI device driver options
 
 menu "TWIHS device driver options"
 	depends on SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
@@ -2046,3 +2084,4 @@ config SAMV7_MCAN_REGDEBUG
 
 endmenu # CAN device driver options
 endif # SAMV7_MCAN
+endif # ARCH_CHIP_SAMV7

arch/arm/src/samv7/sam_xdmac.h

@@ -101,7 +101,9 @@
 #  define DMACH_FLAG_PERIPHPID(n)           ((uint32_t)(n) << DMACH_FLAG_PERIPHPID_SHIFT)
 #  define DMACH_FLAG_PERIPHPID_MAX          DMACH_FLAG_PERIPHPID_MASK
 #define DMACH_FLAG_PERIPHH2SEL              (0)       /* No HW handshaking */
-#define DMACH_FLAG_PERIPHISPERIPH           (1 << 7)  /* Bit 7:  0=memory; 1=peripheral */
+#define DMACH_FLAG_PERIPHIS_MASK            (1 << 7)  /* Bit 7:  Peripheral type */
+#  define DMACH_FLAG_PERIPHISPERIPH         (1 << 7)  /* Bit 7:  1 = Peripheral */
+#  define DMACH_FLAG_PERIPHISMEMORY         (0 << 7)  /* Bit 7:  0 = Memory */
 #define DMACH_FLAG_PERIPHAHB_MASK           (1 << 8)  /* Bit 8:  Peripheral ABH layer 1 */
 #  define DMACH_FLAG_PERIPHAHB_AHB_IF0      (0)
 #  define DMACH_FLAG_PERIPHAHB_AHB_IF1      DMACH_FLAG_PERIPHAHB_MASK