mirror of
https://github.com/apache/nuttx.git
synced 2026-05-25 18:27:56 +08:00
arch: arm: a1x: fix nxstyle errors
Fix nxstyle errors to pass CI Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
committed by
Xiang Xiao
Xiang Xiao
parent
f2813416d1
commit
b5fd0af658
+12
-12
@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/a1x/a1x_boot.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@@ -16,31 +16,31 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_A1X_BOOT_H
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#define __ARCH_ARM_SRC_A1X_A1X_BOOT_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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/****************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_boardinitialize
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*
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* Description:
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* All A1x architectures must provide the following entry point. This entry
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* point is called early in the initialization -- after clocking and memory have
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* been configured but before caches have been enabled and before any devices have
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* been initialized.
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* All A1x architectures must provide the following entry point.
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* This entry point is called early in the initialization -- after
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* clocking and memory have been configured but before caches have been
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* enabled and before any devices have been initialized.
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*
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************************************************************************************/
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****************************************************************************/
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void a1x_boardinitialize(void);
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+31
-29
@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/a1x/a1x_pio.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@@ -16,14 +16,14 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_A1X_PIO_H
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#define __ARCH_ARM_SRC_A1X_A1X_PIO_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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@@ -32,11 +32,11 @@
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#include "hardware/a1x_pio.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Bit-encoded input to a1x_pio_config() ********************************************/
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/* Bit-encoded input to a1x_pio_config() ************************************/
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/* 32-bit Encoding:
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*
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@@ -122,7 +122,8 @@
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# define PIO_INT_LOWLEVEL (PIO_REG_INT_LOWLEVEL << PIO_INT_SHIFT)
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# define PIO_INT_BOTHEDGES (PIO_REG_INT_BOTHEDGES << PIO_INT_SHIFT)
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/* If the pin is an PIO output, then this identifies the initial output value:
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/* If the pin is an PIO output, then this identifies the initial
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* output value:
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*
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* 3322 2222 2222 1111 1111 11
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* 1098 7654 3210 9876 5432 1098 7654 3210
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@@ -198,23 +199,23 @@
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#define PIO_PIN30 (30 << PIO_PIN_SHIFT)
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#define PIO_PIN31 (31 << PIO_PIN_SHIFT)
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/* Must be big enough to hold the 32-bit encoding */
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typedef uint32_t pio_pinset_t;
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/************************************************************************************
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/****************************************************************************
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* Inline Functions
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************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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@@ -225,17 +226,18 @@ extern "C"
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#define EXTERN extern
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#endif
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/************************************************************************************
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/****************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_irqinitialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for PIO pins.
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* Initialize logic to support a second level of interrupt decoding for
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* PIO pins.
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*
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************************************************************************************/
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****************************************************************************/
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#ifdef CONFIG_A1X_PIO_IRQ
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void a1x_pio_irqinitialize(void);
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@@ -243,43 +245,43 @@ void a1x_pio_irqinitialize(void);
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# define a1x_pio_irqinitialize()
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#endif
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_config
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*
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* Description:
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* Configure a PIO pin based on bit-encoded description of the pin.
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*
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************************************************************************************/
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****************************************************************************/
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int a1x_pio_config(pio_pinset_t cfgset);
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_write
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*
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* Description:
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* Write one or zero to the selected PIO pin
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*
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************************************************************************************/
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****************************************************************************/
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void a1x_pio_write(pio_pinset_t pinset, bool value);
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_read
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*
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* Description:
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* Read one or zero from the selected PIO pin
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*
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************************************************************************************/
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****************************************************************************/
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bool a1x_pio_read(pio_pinset_t pinset);
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_irqenable
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*
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* Description:
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* Enable the interrupt for specified PIO IRQ
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*
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************************************************************************************/
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****************************************************************************/
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#ifdef CONFIG_A1X_PIO_IRQ
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void a1x_pio_irqenable(int irq);
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@@ -287,13 +289,13 @@ void a1x_pio_irqenable(int irq);
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# define a1x_pio_irqenable(irq)
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#endif
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/************************************************************************************
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/****************************************************************************
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* Name: a1x_pio_irqdisable
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*
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* Description:
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* Disable the interrupt for specified PIO IRQ
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*
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************************************************************************************/
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****************************************************************************/
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#ifdef CONFIG_A1X_PIO_IRQ
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void a1x_pio_irqdisable(int irq);
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@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/a1x/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@@ -16,12 +16,12 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_CHIP_H
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#define __ARCH_ARM_SRC_A1X_CHIP_H
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/*****************************************************************************
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/****************************************************************************
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* Included Files
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****************************************************************************/
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@@ -42,7 +42,7 @@
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_A1X_CHIP_H */
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@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/a1x/hardware/a10_memorymap.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@@ -16,23 +16,24 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
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#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/a1x/chip.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Decimal configuration values may exceed 2Gb and, hence, overflow to negative
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* values unless we force them to unsigned long:
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****************************************************************************/
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/* Decimal configuration values may exceed 2Gb and, hence, overflow to
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* negative values unless we force them to unsigned long:
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*/
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#define __CONCAT(a,b) a ## b
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@@ -281,8 +282,8 @@
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/* A1X Virtual (mapped) Memory Map
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*
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* board_memorymap.h contains special mappings that are needed when a ROM
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* memory map is used. It is included in this odd location because it depends
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* on some the virtual address definitions provided above.
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* memory map is used. It is included in this odd location because it
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* depends on some the virtual address definitions provided above.
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*/
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#include <arch/board/board_memorymap.h>
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@@ -429,9 +430,9 @@
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# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined"
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# endif
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/* A sanity check, if the configuration says that the page table is read-only
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* and pre-initialized (maybe ROM), then it should have also defined both of
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* the page table base addresses.
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/* A sanity check, if the configuration says that the page table is
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* read-only and pre-initialized (maybe ROM), then it should have also
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* defined both of the page table base addresses.
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*/
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# ifdef CONFIG_ARCH_ROMPGTABLE
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@@ -442,10 +443,10 @@
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/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
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* map probably do not apply because paging logic will probably partition
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* the SRAM section differently. In particular, if the page table is located
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* at the end of SRAM, then the virtual page table address defined below
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* will probably be in error. In that case PGTABLE_BASE_VADDR is defined
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* in the file mmu.h
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* the SRAM section differently. In particular, if the page table is
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* located at the end of SRAM, then the virtual page table address defined
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* below will probably be in error.
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* In that case PGTABLE_BASE_VADDR is defined in the file mmu.h
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*
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* We must declare the page table at the bottom or at the top of internal
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* SRAM. We pick the bottom of internal SRAM *unless* there are vectors
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@@ -469,9 +470,10 @@
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# endif /* CONFIG_ARCH_LOWVECTORS */
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/* Note that the page table does not lie in the same address space as does the
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* mapped RAM in either case. So we will need to create a special mapping for
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* the page table at boot time.
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/* Note that the page table does not lie in the same address space as does
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* the mapped RAM in either case.
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* So we will need to create a special mapping for the page table at boot
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* time.
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*/
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# define ARMV7A_PGTABLE_MAPPING 1
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@@ -480,10 +482,10 @@
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/* Level 2 Page table start addresses.
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*
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* 16Kb of memory is reserved hold the page table for the virtual mappings. A
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* portion of this table is not accessible in the virtual address space (for
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* normal operation). There are several large holes in the physical address
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* space for which there will never be level 1 mappings:
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* 16Kb of memory is reserved hold the page table for the virtual mappings.
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* A portion of this table is not accessible in the virtual address space
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* (for normal operation). There are several large holes in the physical
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* address space for which there will never be level 1 mappings:
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*
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* LI PAGE TABLE
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* ADDRESS RANGE SIZE ENTRIES SECTIONS
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@@ -560,7 +562,8 @@
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*
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* A1X_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
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* A1X_VECTOR_VSRAM - Virtual address of vector table in SRAM
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* A1X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
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* A1X_VECTOR_VADDR - Virtual address of vector table
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* (0x00000000 or 0xffff0000)
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*
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* NOTE: When using LOWVECTORS, the actual base of the vectors appears to be
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* offset to address 0x0000:0040
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@@ -588,16 +591,16 @@
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#endif
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H */
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@@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/a1x/hardware/a10_piocfg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@@ -16,31 +16,36 @@
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
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#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/a1x_memorymap.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* PIO pin definitions *************************************************************/
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****************************************************************************/
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/* PIO pin definitions ******************************************************/
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/* Alternate Pin Functions.
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*
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* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
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* Drivers, however, will use the pin selection without the numeric suffix.
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* Additional definitions are required in the board.h file. */
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* Alternative pin selections are provided with a numeric suffix like _1, _2,
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* etc. Drivers, however, will use the pin selection without the numeric
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* suffix.
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* Additional definitions are required in the board.h file.
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*/
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/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
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* Additional effort is required to select specific PIO options (such as pull-up or
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* -down). Just the basics are defined for most pins in this file at the present
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/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
|
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* Additional effort is required to select specific PIO options
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* (such as pull-up or-down).
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* Just the basics are defined for most pins in this file at the present
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* time.
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*/
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@@ -1,4 +1,4 @@
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/************************************************************************************
|
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/****************************************************************************
|
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* arch/arm/src/a1x/hardware/a1x_intc.h
|
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*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,23 +16,23 @@
|
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* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
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#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
|
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#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
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/************************************************************************************
|
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/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
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|
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#include <nuttx/config.h>
|
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#include "hardware/a1x_memorymap.h"
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|
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/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
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****************************************************************************/
|
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/* Register offsets *****************************************************************/
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/* Register offsets *********************************************************/
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#define A1X_INTC_VECTOR_OFFSET 0x0000 /* Interrupt Vector */
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#define A1X_INTC_BASEADDR_OFFSET 0x0004 /* Interrupt Base Address */
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@@ -81,7 +81,7 @@
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#define A1X_INTC_PRIO3_OFFSET 0x008c /* Interrupt Source Priority 3 */
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#define A1X_INTC_PRIO4_OFFSET 0x0090 /* Interrupt Source Priority 4 */
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/* Register virtual addresses *******************************************************/
|
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/* Register virtual addresses ***********************************************/
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#define A1X_INTC_VECTOR (A1X_INTC_VADDR+A1X_INTC_VECTOR_OFFSET)
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#define A1X_INTC_BASEADDR (A1X_INTC_VADDR+A1X_INTC_BASEADDR_OFFSET)
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@@ -130,7 +130,7 @@
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#define A1X_INTC_PRIO3 (A1X_INTC_VADDR+A1X_INTC_PRIO3_OFFSET)
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#define A1X_INTC_PRIO4 (A1X_INTC_VADDR+A1X_INTC_PRIO4_OFFSET)
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|
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/* Register bit field definitions ***************************************************/
|
||||
/* Register bit field definitions *******************************************/
|
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/* Interrupt Vector */
|
||||
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||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/a1x/hardware/a1x_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,14 +16,14 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/a1x/chip.h>
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/a1x/hardware/a1x_pio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,21 +16,21 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
|
||||
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/a1x_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#define PIO_REG_PORTA 0
|
||||
#define PIO_REG_PORTB 1
|
||||
@@ -61,7 +61,7 @@
|
||||
#define PIO_REG_INT_LOWLEVEL 3
|
||||
#define PIO_REG_INT_BOTHEDGES 4
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define A1X_PIO_CFG0_OFFSET(n) (0x0000 + (n)*0x24) /* Port Configure Register 0, n=0-9 */
|
||||
#define A1X_PIO_CFG1_OFFSET(n) (0x0004 + (n)*0x24) /* Port Configure Register 1, n=0-9 */
|
||||
@@ -82,7 +82,7 @@
|
||||
#define A1X_SDR_PAD_DRV_OFFSET 0x0220 /* SDRAM Pad Multi-Driving Register */
|
||||
#define A1X_SDR_PAD_PUL_OFFSET 0x0224 /* SDRAM Pad Pull Register */
|
||||
|
||||
/* Register virtual addresses *******************************************************/
|
||||
/* Register virtual addresses ***********************************************/
|
||||
|
||||
#define A1X_PIO_CFG0(n) (A1X_PIO_VADDR+A1X_PIO_CFG0_OFFSET(n))
|
||||
#define A1X_PIO_CFG1(n) (A1X_PIO_VADDR+A1X_PIO_CFG1_OFFSET(n))
|
||||
@@ -103,7 +103,7 @@
|
||||
#define A1X_SDR_PAD_DRV (A1X_PIO_VADDR+A1X_SDR_PAD_DRV_OFFSET)
|
||||
#define A1X_SDR_PAD_PUL (A1X_PIO_VADDR+A1X_SDR_PAD_PUL_OFFSET)
|
||||
|
||||
/* Register bit field definitions ***************************************************/
|
||||
/* Register bit field definitions *******************************************/
|
||||
|
||||
/* Port Configure Register 0, n=0-7 */
|
||||
|
||||
@@ -197,9 +197,11 @@
|
||||
# define PIO_INT_DEB_CLKPRESC(n) ((uint32_t)(n) << PIO_INT_DEB_CLKPRESC_SHIFT)
|
||||
|
||||
/* SDRAM Pad Multi-Driving Register */
|
||||
|
||||
/* REVISIT: Missing register bit definitions */
|
||||
|
||||
/* SDRAM Pad Pull Register */
|
||||
|
||||
/* REVISIT: Missing register bit definitions */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H */
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/a1x/hardware/a1x_piocfg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,14 +16,14 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIOCFG_H
|
||||
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIOCFG_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/a1x/chip.h>
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/a1x/hardware/a1x_timer.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,23 +16,23 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_TIMER_H
|
||||
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/a1x_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define A1X_TMR_IRQ_EN_OFFSET 0x0000 /* Timer IRQ Enable */
|
||||
#define A1X_TMR_IRQ_STA_OFFSET 0x0004 /* Timer Status */
|
||||
@@ -94,7 +94,7 @@
|
||||
|
||||
#define A1X_CPU_CFG_OFFSET 0x0140 /* CPU configuration register */
|
||||
|
||||
/* Register virtual addresses *******************************************************/
|
||||
/* Register virtual addresses ***********************************************/
|
||||
|
||||
#define A1X_TMR_IRQ_EN (A1X_TIMER_VADDR+A1X_TMR_IRQ_EN_OFFSET)
|
||||
#define A1X_TMR_IRQ_STA (A1X_TIMER_VADDR+A1X_TMR_IRQ_STA_OFFSET)
|
||||
@@ -156,7 +156,7 @@
|
||||
|
||||
#define A1X_CPU_CFG (A1X_TIMER_VADDR+A1X_CPU_CFG_OFFSET)
|
||||
|
||||
/* Register bit field definitions ***************************************************/
|
||||
/* Register bit field definitions *******************************************/
|
||||
|
||||
/* Timer IRQ Enable and Timer Status */
|
||||
|
||||
@@ -179,6 +179,7 @@
|
||||
# define TMR01_CTRL_SRC_PLL6DIV6 (2 << TMR_CTRL_SRC_SHIFT) /* PLL6/6 (Timers 0 and 1 only) */
|
||||
# define TMR4_CTRL_SRC_CLKIN0 (2 << TMR_CTRL_SRC_SHIFT) /* External CLKIN0 (Timer 4 only) */
|
||||
# define TMR5_CTRL_SRC_CLKIN1 (2 << TMR_CTRL_SRC_SHIFT) /* External CLKIN1 (Timer 5 only) */
|
||||
|
||||
#define TMR_CTRL_CLK_PRES_SHIFT (4) /* Bits 4-6: Select the pre-scale of timer n clock source */
|
||||
#define TMR_CTRL_CLK_PRES_MASK (7 << TMR_CTRL_CLK_PRES_SHIFT)
|
||||
# define TMR_CTRL_CLK_PRES_DIV1 (0 << TMR_CTRL_CLK_PRES_SHIFT) /* /1 */
|
||||
@@ -189,6 +190,7 @@
|
||||
# define TMR_CTRL_CLK_PRES_DIV32 (5 << TMR_CTRL_CLK_PRES_SHIFT) /* /32 (Not Timer 0) */
|
||||
# define TMR_CTRL_CLK_PRES_DIV64 (6 << TMR_CTRL_CLK_PRES_SHIFT) /* /64 (Not Timer 0) */
|
||||
# define TMR_CTRL_CLK_PRES_DIV128 (7 << TMR_CTRL_CLK_PRES_SHIFT) /* /128 (Not Timer 0) */
|
||||
|
||||
#define TMR_CTRL_MODE (1 << 7) /* Bit 7: Timer n mode, n={0,1,2,4,5} */
|
||||
# define TMR_CTRL_MODE_SINGLE (1 << 7) /* 1=single mode */
|
||||
# define TMR_CTRL_MODE_CONTINUOUS (0 << 7) /* 0=continuous mode */
|
||||
@@ -196,14 +198,17 @@
|
||||
/* Timer 3 Control */
|
||||
|
||||
#define TMR3_CTRL_EN (1 << 0) /* Bit 0: Timer 3 Enable*/
|
||||
|
||||
#define TMR3_CTRL_CLK_PRES_SHIFT (2) /* Bits 2-3: Select the pre-scale of timer 3 clock source (LOSC) */
|
||||
#define TMR3_CTRL_CLK_PRES_MASK (7 << TMR3_CTRL_CLK_PRES_SHIFT)
|
||||
# define TMR3_CTRL_CLK_PRES_DIV16 (0 << TMR3_CTRL_CLK_PRES_SHIFT) /* /16 */
|
||||
# define TMR3_CTRL_CLK_PRES_DIV32 (1 << TMR3_CTRL_CLK_PRES_SHIFT) /* /32 */
|
||||
# define TMR3_CTRL_CLK_PRES_DIV64 (2 << TMR3_CTRL_CLK_PRES_SHIFT) /* /64 */
|
||||
|
||||
#define TMR3_CTRL_MODE (1 << 4) /* Bit 4: Timer3 mode */
|
||||
|
||||
/* Timer Interval Value (32-bit value) */
|
||||
|
||||
/* Timer Current Value (32-bit value) */
|
||||
|
||||
/* AVS Control Register */
|
||||
@@ -214,6 +219,7 @@
|
||||
#define AVS_CNT1_PS (1 << 9) /* Bit 9: Audio/Video Sync Counter 1 Pause Control */
|
||||
|
||||
/* AVS Counter 0 Register (32-bit value) */
|
||||
|
||||
/* AVS Counter 1 Register (32-bit value) */
|
||||
|
||||
/* AVS Divisor */
|
||||
@@ -235,16 +241,16 @@
|
||||
#define WDOG_MODE_RSTEN (1 << 1) /* Bit 1: Watch-Dog Reset Enable */
|
||||
#define WDOG_MODE_INTV_SHIFT (3) /* Bits 3-6: Watch-Dog Interval Value */
|
||||
#define WDOG_MODE_INTV_MASK (15 << WDOG_MODE_INTV_SHIFT)
|
||||
# define WDOG_MODE_INTV_0p5SEC (0 << WDOG_MODE_INTV_SHIFT) /* 0.5 sec */
|
||||
# define WDOG_MODE_INTV_1SEc (1 << WDOG_MODE_INTV_SHIFT) /* 1 sec */
|
||||
# define WDOG_MODE_INTV_2SEC (2 << WDOG_MODE_INTV_SHIFT) /* 2 sec */
|
||||
# define WDOG_MODE_INTV_3SEC (3 << WDOG_MODE_INTV_SHIFT) /* 3 sec */
|
||||
# define WDOG_MODE_INTV_4SEC (4 << WDOG_MODE_INTV_SHIFT) /* 4 sec */
|
||||
# define WDOG_MODE_INTV_5SEC (5 << WDOG_MODE_INTV_SHIFT) /* 5 sec */
|
||||
# define WDOG_MODE_INTV_6SEC (6 << WDOG_MODE_INTV_SHIFT) /* 6 sec */
|
||||
# define WDOG_MODE_INTV_8SEC (7 << WDOG_MODE_INTV_SHIFT) /* 8 sec */
|
||||
# define WDOG_MODE_INTV_10SEC (8 << WDOG_MODE_INTV_SHIFT) /* 10 sec */
|
||||
# define WDOG_MODE_INTV_12SEC (9 << WDOG_MODE_INTV_SHIFT) /* 12 sec */
|
||||
# define WDOG_MODE_INTV_0p5SEC (0 << WDOG_MODE_INTV_SHIFT) /* 0.5 sec */
|
||||
# define WDOG_MODE_INTV_1SEc (1 << WDOG_MODE_INTV_SHIFT) /* 1 sec */
|
||||
# define WDOG_MODE_INTV_2SEC (2 << WDOG_MODE_INTV_SHIFT) /* 2 sec */
|
||||
# define WDOG_MODE_INTV_3SEC (3 << WDOG_MODE_INTV_SHIFT) /* 3 sec */
|
||||
# define WDOG_MODE_INTV_4SEC (4 << WDOG_MODE_INTV_SHIFT) /* 4 sec */
|
||||
# define WDOG_MODE_INTV_5SEC (5 << WDOG_MODE_INTV_SHIFT) /* 5 sec */
|
||||
# define WDOG_MODE_INTV_6SEC (6 << WDOG_MODE_INTV_SHIFT) /* 6 sec */
|
||||
# define WDOG_MODE_INTV_8SEC (7 << WDOG_MODE_INTV_SHIFT) /* 8 sec */
|
||||
# define WDOG_MODE_INTV_10SEC (8 << WDOG_MODE_INTV_SHIFT) /* 10 sec */
|
||||
# define WDOG_MODE_INTV_12SEC (9 << WDOG_MODE_INTV_SHIFT) /* 12 sec */
|
||||
# define WDOG_MODE_INTV_14SEC (10 << WDOG_MODE_INTV_SHIFT) /* 14 sec */
|
||||
# define WDOG_MODE_INTV_16SEC (11 << WDOG_MODE_INTV_SHIFT) /* 16 sec */
|
||||
|
||||
@@ -257,12 +263,13 @@
|
||||
# define CNT64_CTRL_SRC_PLL6DIV6 (1 << 2) /* 1=PLL6/6 */
|
||||
|
||||
/* 64-bit Counter low (32-bit value) */
|
||||
|
||||
/* 64-bit Counter high (32-bit value) */
|
||||
|
||||
/* Low Oscillator Control */
|
||||
|
||||
#define LOSC_CTRL_OSC32K_SRCSEL (1 << 0) /* Bit 0: OSC32KHz Clock source Select */
|
||||
#define LOSC_CTRL_EXT_GSM_SHIFT (2) /* Bits 2-3: External 32768Hz Crystal GSM */
|
||||
#define LOSC_CTRL_EXT_GSM_SHIFT (2) /* Bits 2-3: External 32768Hz Crystal GSM */
|
||||
#define LOSC_CTRL_EXT_GSM_MASK (3 << LOSC_CTRL_EXT_GSM_SHIFT)
|
||||
# define LOSC_CTRL_EXT_GSM_LOW (0 << LOSC_CTRL_EXT_GSM_SHIFT)
|
||||
# define LOSC_CTRL_EXT_GSM_MEDLOW (1 << LOSC_CTRL_EXT_GSM_SHIFT)
|
||||
@@ -349,7 +356,7 @@
|
||||
#define ALARM_EN_WK6EN (1 << 6) /* Bit 6: Week 6(Sunday) Alarm Enable */
|
||||
#define ALARM_EN_CNTEN (1 << 8) /* Bit 8: Alarm Counter Enable */
|
||||
|
||||
/* Alarm IRQ Enable and Alarm IRQ Status*/
|
||||
/* Alarm IRQ Enable and Alarm IRQ Status */
|
||||
|
||||
#define ALARM_IRQ_CNT (1 << 0) /* Bit 0: Alarm Counter IRQ */
|
||||
#define ALARM_IRQ_WK (1 << 1) /* Bit 1: Alarm Week IRQ */
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/a1x/hardware/a1x_uart.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
@@ -16,23 +16,23 @@
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_UART_H
|
||||
#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/a1x_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define A1X_UART_RBR_OFFSET 0x0000 /* UART Receive Buffer Register */
|
||||
#define A1X_UART_THR_OFFSET 0x0000 /* UART Transmit Holding Register */
|
||||
@@ -51,7 +51,7 @@
|
||||
#define A1X_UART_RFL_OFFSET 0x0084 /* UART Receive FIFO Level */
|
||||
#define A1X_UART_HALT_OFFSET 0x00a4 /* UART Halt TX Register */
|
||||
|
||||
/* Register virtual addresses *******************************************************/
|
||||
/* Register virtual addresses ***********************************************/
|
||||
|
||||
#define A1X_UART_RBR(n) (A1X_UART_VADDR(n)+A1X_UART_RBR_OFFSET)
|
||||
#define A1X_UART_THR(n) (A1X_UART_VADDR(n)+A1X_UART_THR_OFFSET)
|
||||
@@ -206,7 +206,7 @@
|
||||
#define A1X_UART7_RFL (A1X_UART7_VADDR+A1X_UART_RFL_OFFSET)
|
||||
#define A1X_UART7_HALT (A1X_UART7_VADDR+A1X_UART_HALT_OFFSET)
|
||||
|
||||
/* Register bit field definitions ***************************************************/
|
||||
/* Register bit field definitions *******************************************/
|
||||
|
||||
/* UART Receive Buffer Register */
|
||||
|
||||
@@ -244,6 +244,7 @@
|
||||
# define UART_IIR_IID_LINESTATUS (6 << UART_IIR_IID_SHIFT) /* Receiver line status */
|
||||
# define UART_IIR_IID_BUSY (7 << UART_IIR_IID_SHIFT) /* Busy detect */
|
||||
# define UART_IIR_IID_TIMEOUT (12 << UART_IIR_IID_SHIFT) /* Character timeout */
|
||||
|
||||
#define UART_IIR_FEFLAG_SHIFT (6) /* Bits 6-7: FIFOs Enable Flag */
|
||||
#define UART_IIR_FEFLAG_MASK (3 << UART_IIR_FEFLAG_SHIFT)
|
||||
# define UART_IIR_FEFLAG_DISABLE (0 << UART_IIR_FEFLAG_SHIFT)
|
||||
@@ -261,6 +262,7 @@
|
||||
# define UART_FCR_TFT_TWO (1 << UART_FCR_TFT_SHIFT) /* 2 characters in the FIFO */
|
||||
# define UART_FCR_TFT_QUARTER (2 << UART_FCR_TFT_SHIFT) /* FIFO 1/4 full */
|
||||
# define UART_FCR_TFT_HALF (3 << UART_FCR_TFT_SHIFT) /* FIFO 1/2 full */
|
||||
|
||||
#define UART_FCR_RT_SHIFT (6) /* Bits 6-7: RCVR Trigger */
|
||||
#define UART_FCR_RT_MASK (3 << UART_FCR_RT_SHIFT)
|
||||
# define UART_FCR_RT_ONE (0 << UART_FCR_RT_SHIFT) /* 1 character in the FIFO */
|
||||
@@ -276,6 +278,7 @@
|
||||
# define UART_LCR_DLS_6BITS (1 << UART_LCR_DLS_SHIFT) /* 6 bits */
|
||||
# define UART_LCR_DLS_7BITS (2 << UART_LCR_DLS_SHIFT) /* 7 bits */
|
||||
# define UART_LCR_DLS_8BITS (3 << UART_LCR_DLS_SHIFT) /* 8 bits */
|
||||
|
||||
#define UART_LCR_STOP (1 << 2) /* Bit 2: Number of stop bits */
|
||||
#define UART_LCR_PEN (1 << 3) /* Bit 3: Parity Enable */
|
||||
#define UART_LCR_EPS (1 << 4) /* Bit 4: Even Parity Select */
|
||||
|
||||
Reference in New Issue
Block a user