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STM32 DAC DMA fixes from John Wharington

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This commit is contained in:
Gregory Nutt
2013-07-30 08:54:32 -06:00
parent 413aba0bf5
commit b57f54fbd0
7 changed files with 363 additions and 45 deletions
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ChangeLog
+3
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@@ -5229,4 +5229,7 @@
(2013-7-29).
* arch/arm/src/armv7-a/arm_cache.S: Separate the bigger cache
operations into separater files (2013-7-29).
* arch/arm/src/stm32/stm32_dac.c: Fixed numerous DAC driver
errors and added support for DAC DMA (contributed by John
Wharington, 2013-7-30).
arch/arm/src/stm32/Kconfig
+57 -2
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@@ -675,7 +675,7 @@ config STM32_SPI1
config STM32_SPI2
bool "SPI2"
default n
depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY) || (STM32_STM32F10XX && (STM32_HIGHDENSITY || STM32_MEDIUMDENSITY))
depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY) || (STM32_STM32F10XX && (STM32_HIGHDENSITY || STM32_MEDIUMDENSITY)) || STM32_STM32F30XX
select SPI
select STM32_SPI
@@ -1121,7 +1121,7 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
config STM32_CCMEXCLUDE
bool "Exclude CCM SRAM from the heap"
depends on STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_STM32F30XX
default y if ARCH_DMA || ELF
---help---
Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA
@@ -2202,6 +2202,61 @@ config STM32_TIM14_DAC2
endchoice
menu "DAC Configuration"
depends on STM32_DAC1 || STM32_DAC2
config STM32_DAC1_DMA
bool "DAC1 DMA"
depends on STM32_DAC1
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by and EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC1_DMA
config STM32_DAC1_TIMER
int "DAC1 timer"
range 2 7
config STM32_DAC1_TIMER_FREQUENCY
int "DAC1 timer frequency"
default 0
range 0 14
endif
config STM32_DAC2_DMA
bool "DAC2 DMA"
depends on STM32_DAC2
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by and EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC2_DMA
config STM32_DAC2_TIMER
int "DAC2 timer"
default 0
range 2 7
config STM32_DAC2_TIMER_FREQUENCY
int "DAC2 timer frequency"
default 0
endif
config STM32_DAC_DMA_BUFFER_SIZE
int "DAC DMA buffer size"
default 256
endmenu
config STM32_USART
bool
arch/arm/src/stm32/chip/stm32_dac.h
+1 -1
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@@ -103,7 +103,7 @@
# define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */
# define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */
# define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */
#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */enable
#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */
#define DAC_CR_WAVE_MASK (3 << DAC_CR_WAVE_SHIFT)
# define DAC_CR_WAVE_DISABLED (0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */
# define DAC_CR_WAVE_NOISE (1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */
arch/arm/src/stm32/chip/stm32f10xxx_dma.h
+1 -1
View File
@@ -291,7 +291,7 @@
#define STM32_DMA2_CHAN1 (7)
#define STM32_DMA2_CHAN2 (8)
#define STM32_DMA2_CHAN3 (1)
#define STM32_DMA2_CHAN3 (9)
#define STM32_DMA2_CHAN4 (10)
#define STM32_DMA2_CHAN5 (11)
arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
+9
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@@ -97,6 +97,15 @@
#define GPIO_COMP6_OUT_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
#define GPIO_COMP7_OUT (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN2)
/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
* (PA4 or PA5) is automatically connected to the analog converter output
* (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
* should first be configured to analog (AIN)".
*/
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15)
arch/arm/src/stm32/stm32_dac.c
+286 -37
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32f10xxx_dma.c
+6 -4
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@@ -58,7 +58,7 @@
/* Only for the STM32F10xx family for now */
#ifdef CONFIG_STM32_STM32F10XX
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
/****************************************************************************
* Pre-processor Definitions
@@ -157,7 +157,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
{
.chan = 3,
#ifdef CONFIG_STM32_CONNECTIVITYLINE
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
.irq = STM32_IRQ_DMA2CH4,
#else
.irq = STM32_IRQ_DMA2CH45,
@@ -166,7 +166,7 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
{
.chan = 4,
#ifdef CONFIG_STM32_CONNECTIVITYLINE
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
.irq = STM32_IRQ_DMA2CH5,
#else
.irq = STM32_IRQ_DMA2CH45,
@@ -288,7 +288,7 @@ static int stm32_dmainterrupt(int irq, void *context)
}
else
#if STM32_NDMA > 1
#ifdef CONFIG_STM32_CONNECTIVITYLINE
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F30XX)
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
#else
if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
@@ -615,10 +615,12 @@ bool stm32_dmacapable(uint32_t maddr)
{
switch (maddr & STM32_REGION_MASK)
{
#if defined(CONFIG_STM32_STM32F10XX)
case STM32_FSMC_BANK1:
case STM32_FSMC_BANK2:
case STM32_FSMC_BANK3:
case STM32_FSMC_BANK4:
#endif
case STM32_SRAM_BASE:
case STM32_CODE_BASE:
/* All RAM and flash is supported */