mirror of
https://github.com/apache/nuttx.git
synced 2026-09-20 04:47:58 +08:00
Misoc LM3: Add Misoc Ethernet driver. Integrate network support into configs/misoc/hello. Remove configs/misoc/include/generated directory. I suppose the the intent now is that this is a symbolic link? DANGER! This means that you cannot compile this code with first generating these files a providing a symbolic link to this location!
This commit is contained in:
Ramtin Amin
committed by
Gregory Nutt
Gregory Nutt
parent
00215fbc98
commit
b568bfa813
@@ -43,6 +43,13 @@ config MISOC_UART1
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select ARCH_HAVE_UART1
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select MISOC_UART
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config MISOC_ETHERNET
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bool "Ethernet"
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default n
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select NETDEVICES
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select ARCH_HAVE_PHY
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select ARCH_HAVE_NETDEV_STATISTICS
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endmenu # MISOC Peripheral Support
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config MISOC_UART
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@@ -73,6 +73,16 @@
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void misoc_timer_initialize(void);
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/****************************************************************************
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* Name: flush_cpu_dcache
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*
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* Description:
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* flush cpu cache Data cache
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*
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****************************************************************************/
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void flush_cpu_dcache(void);
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/****************************************************************************
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* Name: up_serialinit
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*
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File diff suppressed because it is too large
Load Diff
@@ -39,7 +39,7 @@ HEAD_ASRC = lm32_vectors.S
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CMN_ASRCS =
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CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c
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CMN_CSRCS += misoc_modifyreg8.c misoc_modifyreg16.c misoc_modifyreg32.c
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CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c
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CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c misoc_net.c
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CHIP_ASRCS = lm32_syscall.S
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@@ -97,7 +97,6 @@
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void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
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{
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irqstate_t flags;
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uint32_t int_ctx;
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sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
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+278
-16
@@ -59,6 +59,7 @@ CONFIG_DEBUG_FEATURES=y
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# CONFIG_DEBUG_GRAPHICS is not set
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# CONFIG_DEBUG_LIB is not set
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# CONFIG_DEBUG_MM is not set
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# CONFIG_DEBUG_NET is not set
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# CONFIG_DEBUG_SCHED is not set
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#
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@@ -105,6 +106,7 @@ CONFIG_ARCH_CHIP_LM32=y
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#
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CONFIG_MISOC_HAVE_UART1=y
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CONFIG_MISOC_UART1=y
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CONFIG_MISOC_ETHERNET=y
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CONFIG_MISOC_UART=y
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CONFIG_MISOC_UART_RX_BUF_SIZE=64
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CONFIG_MISOC_UART_TX_BUF_SIZE=64
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@@ -131,7 +133,7 @@ CONFIG_LM32_TOOLCHAIN_GNUL=y
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# CONFIG_ARCH_HAVE_POWEROFF is not set
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# CONFIG_ARCH_HAVE_RESET is not set
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CONFIG_ARCH_STACKDUMP=y
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# CONFIG_ENDIAN_BIG is not set
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CONFIG_ENDIAN_BIG=y
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# CONFIG_ARCH_IDLE_CUSTOM is not set
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# CONFIG_ARCH_HAVE_RAMFUNCS is not set
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# CONFIG_ARCH_HAVE_RAMVECTORS is not set
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@@ -178,6 +180,7 @@ CONFIG_ARCH_BOARD_CUSTOM_DIR="/configs/misoc/"
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CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
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# CONFIG_BOARD_CUSTOM_LEDS is not set
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# CONFIG_BOARD_CUSTOM_BUTTONS is not set
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# CONFIG_BOARD_CUSTOM_INTERRUPT is not set
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#
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# Common Board Options
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@@ -192,7 +195,12 @@ CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
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#
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# RTOS Features
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#
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# CONFIG_DISABLE_OS_API is not set
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CONFIG_DISABLE_OS_API=y
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# CONFIG_DISABLE_POSIX_TIMERS is not set
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# CONFIG_DISABLE_PTHREAD is not set
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# CONFIG_DISABLE_SIGNALS is not set
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# CONFIG_DISABLE_MQUEUE is not set
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# CONFIG_DISABLE_ENVIRON is not set
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#
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# Clocks and Timers
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@@ -206,9 +214,9 @@ CONFIG_START_YEAR=2011
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CONFIG_START_MONTH=6
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CONFIG_START_DAY=16
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CONFIG_MAX_WDOGPARMS=2
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CONFIG_PREALLOC_WDOGS=4
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CONFIG_WDOG_INTRESERVE=0
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CONFIG_PREALLOC_TIMERS=0
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CONFIG_PREALLOC_WDOGS=8
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CONFIG_WDOG_INTRESERVE=1
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CONFIG_PREALLOC_TIMERS=4
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#
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# Tasks and Scheduling
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@@ -290,7 +298,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048
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#
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# Device Drivers
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#
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CONFIG_DISABLE_POLL=y
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# CONFIG_DISABLE_POLL is not set
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CONFIG_DEV_NULL=y
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# CONFIG_DEV_ZERO is not set
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# CONFIG_DEV_URANDOM is not set
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@@ -349,6 +357,50 @@ CONFIG_DEV_NULL=y
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# CONFIG_MODEM is not set
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# CONFIG_MTD is not set
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# CONFIG_EEPROM is not set
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CONFIG_NETDEVICES=y
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#
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# General Ethernet MAC Driver Options
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#
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# CONFIG_NETDEV_LOOPBACK is not set
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CONFIG_NETDEV_TELNET=y
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CONFIG_TELNET_RXBUFFER_SIZE=256
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CONFIG_TELNET_TXBUFFER_SIZE=256
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# CONFIG_NETDEV_MULTINIC is not set
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CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y
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# CONFIG_NETDEV_LATEINIT is not set
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# CONFIG_NET_DUMPPACKET is not set
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#
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# External Ethernet MAC Device Support
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#
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# CONFIG_NET_DM90x0 is not set
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# CONFIG_ENC28J60 is not set
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# CONFIG_ENCX24J600 is not set
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# CONFIG_NET_E1000 is not set
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# CONFIG_NET_SLIP is not set
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# CONFIG_NET_FTMAC100 is not set
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# CONFIG_NET_VNET is not set
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#
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# External Ethernet PHY Device Support
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#
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# CONFIG_ARCH_PHY_INTERRUPT is not set
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CONFIG_ETH0_PHY_NONE=y
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# CONFIG_ETH0_PHY_AM79C874 is not set
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# CONFIG_ETH0_PHY_KS8721 is not set
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# CONFIG_ETH0_PHY_KSZ8041 is not set
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# CONFIG_ETH0_PHY_KSZ8051 is not set
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# CONFIG_ETH0_PHY_KSZ8061 is not set
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# CONFIG_ETH0_PHY_KSZ8081 is not set
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# CONFIG_ETH0_PHY_KSZ90x1 is not set
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# CONFIG_ETH0_PHY_DP83848C is not set
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# CONFIG_ETH0_PHY_LAN8720 is not set
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# CONFIG_ETH0_PHY_LAN8740 is not set
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# CONFIG_ETH0_PHY_LAN8740A is not set
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# CONFIG_ETH0_PHY_LAN8742A is not set
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# CONFIG_ETH0_PHY_DM9161 is not set
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# CONFIG_NETDEV_PHY_DEBUG is not set
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# CONFIG_PIPES is not set
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# CONFIG_PM is not set
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# CONFIG_POWER is not set
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@@ -428,9 +480,117 @@ CONFIG_SYSLOG_CONSOLE=y
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#
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# Networking Support
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#
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# CONFIG_ARCH_HAVE_NET is not set
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# CONFIG_ARCH_HAVE_PHY is not set
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# CONFIG_NET is not set
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CONFIG_ARCH_HAVE_NET=y
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CONFIG_ARCH_HAVE_PHY=y
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CONFIG_NET=y
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# CONFIG_NET_NOINTS is not set
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# CONFIG_NET_PROMISCUOUS is not set
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#
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# Driver buffer configuration
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#
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# CONFIG_NET_MULTIBUFFER is not set
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CONFIG_NET_ETH_MTU=1400
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CONFIG_NET_ETH_TCP_RECVWNDO=742
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CONFIG_NET_GUARDSIZE=648
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#
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# Data link support
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#
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# CONFIG_NET_MULTILINK is not set
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CONFIG_NET_ETHERNET=y
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# CONFIG_NET_LOOPBACK is not set
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# CONFIG_NET_TUN is not set
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#
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# Network Device Operations
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#
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# CONFIG_NETDEV_PHY_IOCTL is not set
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#
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# Internet Protocol Selection
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#
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CONFIG_NET_IPv4=y
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# CONFIG_NET_IPv6 is not set
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#
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# Socket Support
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#
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CONFIG_NSOCKET_DESCRIPTORS=8
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CONFIG_NET_NACTIVESOCKETS=16
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CONFIG_NET_SOCKOPTS=y
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# CONFIG_NET_SOLINGER is not set
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#
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# Raw Socket Support
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#
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# CONFIG_NET_PKT is not set
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#
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# TCP/IP Networking
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#
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CONFIG_NET_TCP=y
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# CONFIG_NET_TCPURGDATA is not set
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CONFIG_NET_TCP_CONNS=40
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CONFIG_NET_MAX_LISTENPORTS=40
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CONFIG_NET_TCP_READAHEAD=y
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CONFIG_NET_TCP_WRITE_BUFFERS=y
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CONFIG_NET_TCP_NWRBCHAINS=8
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# CONFIG_NET_TCP_WRBUFFER_DEBUG is not set
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CONFIG_NET_TCP_RECVDELAY=0
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# CONFIG_NET_TCPBACKLOG is not set
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# CONFIG_NET_SENDFILE is not set
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#
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# UDP Networking
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#
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CONFIG_NET_UDP=y
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CONFIG_NET_UDP_CHECKSUMS=y
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CONFIG_NET_UDP_CONNS=8
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CONFIG_NET_BROADCAST=y
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# CONFIG_NET_RXAVAIL is not set
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CONFIG_NET_UDP_READAHEAD=y
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#
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# ICMP Networking Support
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#
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CONFIG_NET_ICMP=y
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CONFIG_NET_ICMP_PING=y
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#
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# IGMPv2 Client Support
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#
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# CONFIG_NET_IGMP is not set
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#
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# ARP Configuration
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#
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CONFIG_NET_ARP=y
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CONFIG_NET_ARPTAB_SIZE=16
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CONFIG_NET_ARP_MAXAGE=120
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CONFIG_NET_ARP_IPIN=y
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CONFIG_NET_ARP_SEND=y
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CONFIG_ARP_SEND_MAXTRIES=5
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CONFIG_ARP_SEND_DELAYMSEC=20
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#
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# Network I/O Buffer Support
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#
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CONFIG_NET_IOB=y
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CONFIG_IOB_NBUFFERS=24
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CONFIG_IOB_BUFSIZE=196
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CONFIG_IOB_NCHAINS=8
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CONFIG_IOB_THROTTLE=8
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# CONFIG_IOB_DEBUG is not set
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# CONFIG_NET_ARCH_INCR32 is not set
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# CONFIG_NET_ARCH_CHKSUM is not set
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# CONFIG_NET_STATISTICS is not set
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#
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# Routing Table Configuration
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#
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# CONFIG_NET_ROUTE is not set
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CONFIG_NET_HOSTNAME="nuttx"
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#
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# Crypto API
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@@ -495,14 +655,14 @@ CONFIG_BUILTIN=y
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#
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# Standard C Library Options
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#
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CONFIG_STDIO_BUFFER_SIZE=0
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CONFIG_STDIO_BUFFER_SIZE=64
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CONFIG_STDIO_LINEBUFFER=y
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CONFIG_NUNGET_CHARS=0
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CONFIG_NUNGET_CHARS=2
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CONFIG_LIB_HOMEDIR="/"
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# CONFIG_LIBM is not set
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# CONFIG_NOPRINTF_FIELDWIDTH is not set
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# CONFIG_LIBC_FLOATINGPOINT is not set
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# CONFIG_LIBC_LONG_LONG is not set
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CONFIG_LIBC_LONG_LONG=y
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# CONFIG_LIBC_IOCTL_VARIADIC is not set
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# CONFIG_LIBC_WCHAR is not set
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# CONFIG_LIBC_LOCALE is not set
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@@ -523,7 +683,15 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
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# CONFIG_ARCH_ROMGETC is not set
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# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
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# CONFIG_ARCH_HAVE_TLS is not set
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# CONFIG_LIBC_NETDB is not set
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CONFIG_LIBC_NETDB=y
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CONFIG_NETDB_DNSCLIENT=y
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CONFIG_NETDB_DNSCLIENT_ENTRIES=8
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CONFIG_NETDB_DNSCLIENT_NAMESIZE=32
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CONFIG_NETDB_DNSCLIENT_LIFESEC=3600
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CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96
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# CONFIG_NETDB_DNSSERVER_NOADDR is not set
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CONFIG_NETDB_DNSSERVER_IPv4=y
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CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808
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#
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# Non-standard Library Support
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@@ -537,7 +705,14 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
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# Basic CXX Support
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#
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# CONFIG_C99_BOOL8 is not set
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# CONFIG_HAVE_CXX is not set
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CONFIG_HAVE_CXX=y
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# CONFIG_HAVE_CXXINITIALIZE is not set
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# CONFIG_CXX_NEWLONG is not set
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#
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# uClibc++ Standard C++ Library
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#
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# CONFIG_UCLIBCXX is not set
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#
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# Application Configuration
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@@ -558,13 +733,16 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
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# CONFIG_EXAMPLES_CCTYPE is not set
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# CONFIG_EXAMPLES_CHAT is not set
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# CONFIG_EXAMPLES_CONFIGDATA is not set
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# CONFIG_EXAMPLES_CXXTEST is not set
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# CONFIG_EXAMPLES_DHCPD is not set
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# CONFIG_EXAMPLES_DISCOVER is not set
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# CONFIG_EXAMPLES_ELF is not set
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# CONFIG_EXAMPLES_FTPC is not set
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# CONFIG_EXAMPLES_FTPD is not set
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CONFIG_EXAMPLES_HELLO=y
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CONFIG_EXAMPLES_HELLO_PRIORITY=100
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CONFIG_EXAMPLES_HELLO_STACKSIZE=2048
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# CONFIG_EXAMPLES_HELLOXX is not set
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# CONFIG_EXAMPLES_HIDKBD is not set
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# CONFIG_EXAMPLES_IGMP is not set
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# CONFIG_EXAMPLES_JSON is not set
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@@ -573,6 +751,20 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048
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# CONFIG_EXAMPLES_MM is not set
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# CONFIG_EXAMPLES_MODBUS is not set
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# CONFIG_EXAMPLES_MOUNT is not set
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CONFIG_EXAMPLES_NETTEST=y
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# CONFIG_EXAMPLES_NETTEST_SERVER is not set
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CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y
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CONFIG_EXAMPLES_NETTEST_IPv4=y
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CONFIG_EXAMPLES_NETTEST_INIT=y
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CONFIG_EXAMPLES_NETTEST_NOMAC=y
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#
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# IPv4 addresses
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#
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CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80132
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CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80101
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CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
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CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8023b
|
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# CONFIG_EXAMPLES_NRF24L01TERM is not set
|
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CONFIG_EXAMPLES_NSH=y
|
||||
# CONFIG_EXAMPLES_NULL is not set
|
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@@ -604,13 +796,27 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
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# CONFIG_EXAMPLES_SMART is not set
|
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# CONFIG_EXAMPLES_SMART_TEST is not set
|
||||
# CONFIG_EXAMPLES_SMP is not set
|
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# CONFIG_EXAMPLES_TCPECHO is not set
|
||||
# CONFIG_EXAMPLES_TELNETD is not set
|
||||
CONFIG_EXAMPLES_TCPECHO=y
|
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CONFIG_EXAMPLES_TCPECHO_PORT=80
|
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CONFIG_EXAMPLES_TCPECHO_BACKLOG=8
|
||||
CONFIG_EXAMPLES_TCPECHO_NCONN=8
|
||||
CONFIG_EXAMPLES_TELNETD=y
|
||||
CONFIG_EXAMPLES_TELNETD_NOMAC=y
|
||||
CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80132
|
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CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101
|
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CONFIG_EXAMPLES_TELNETD_NETMASK=0xffffff00
|
||||
CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=100
|
||||
CONFIG_EXAMPLES_TELNETD_DAEMONSTACKSIZE=2048
|
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CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=100
|
||||
CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048
|
||||
# CONFIG_EXAMPLES_TIFF is not set
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
|
||||
# CONFIG_EXAMPLES_UDPBLASTER is not set
|
||||
# CONFIG_EXAMPLES_UDP is not set
|
||||
# CONFIG_EXAMPLES_USBTERM is not set
|
||||
# CONFIG_EXAMPLES_WATCHDOG is not set
|
||||
# CONFIG_EXAMPLES_WEBSERVER is not set
|
||||
# CONFIG_EXAMPLES_XMLRPC is not set
|
||||
|
||||
#
|
||||
# File System Utilities
|
||||
@@ -644,11 +850,32 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
|
||||
#
|
||||
# Network Utilities
|
||||
#
|
||||
# CONFIG_NETUTILS_CHAT is not set
|
||||
# CONFIG_NETUTILS_CODECS is not set
|
||||
CONFIG_NETUTILS_DHCPC=y
|
||||
# CONFIG_NETUTILS_DHCPD is not set
|
||||
CONFIG_NETUTILS_DISCOVER=y
|
||||
CONFIG_DISCOVER_STACK_SIZE=1024
|
||||
CONFIG_DISCOVER_PRIORITY=50
|
||||
CONFIG_DISCOVER_PORT=96
|
||||
CONFIG_DISCOVER_INTERFACE="eth0"
|
||||
CONFIG_DISCOVER_DEVICE_CLASS=0xff
|
||||
CONFIG_DISCOVER_DESCR="NuttX"
|
||||
# CONFIG_NETUTILS_ESP8266 is not set
|
||||
# CONFIG_NETUTILS_FTPC is not set
|
||||
# CONFIG_NETUTILS_FTPD is not set
|
||||
# CONFIG_NETUTILS_JSON is not set
|
||||
CONFIG_NETUTILS_NETLIB=y
|
||||
# CONFIG_NETUTILS_NTPCLIENT is not set
|
||||
# CONFIG_NETUTILS_PPPD is not set
|
||||
# CONFIG_NETUTILS_SMTP is not set
|
||||
CONFIG_NETUTILS_TELNETD=y
|
||||
# CONFIG_NETUTILS_TFTPC is not set
|
||||
CONFIG_NETUTILS_WEBCLIENT=y
|
||||
CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)"
|
||||
CONFIG_WEBCLIENT_TIMEOUT=10
|
||||
# CONFIG_NETUTILS_WEBSERVER is not set
|
||||
# CONFIG_NETUTILS_XMLRPC is not set
|
||||
|
||||
#
|
||||
# NSH Library
|
||||
@@ -673,6 +900,7 @@ CONFIG_NSH_BUILTIN_APPS=y
|
||||
# Disable Individual commands
|
||||
#
|
||||
# CONFIG_NSH_DISABLE_ADDROUTE is not set
|
||||
# CONFIG_NSH_DISABLE_ARP is not set
|
||||
# CONFIG_NSH_DISABLE_BASENAME is not set
|
||||
# CONFIG_NSH_DISABLE_CAT is not set
|
||||
# CONFIG_NSH_DISABLE_CD is not set
|
||||
@@ -703,8 +931,10 @@ CONFIG_NSH_DISABLE_LOSMART=y
|
||||
# CONFIG_NSH_DISABLE_MOUNT is not set
|
||||
# CONFIG_NSH_DISABLE_MV is not set
|
||||
# CONFIG_NSH_DISABLE_MW is not set
|
||||
# CONFIG_NSH_DISABLE_NSLOOKUP is not set
|
||||
CONFIG_NSH_DISABLE_PRINTF=y
|
||||
CONFIG_NSH_DISABLE_PS=y
|
||||
# CONFIG_NSH_DISABLE_PING is not set
|
||||
# CONFIG_NSH_DISABLE_PUT is not set
|
||||
# CONFIG_NSH_DISABLE_PWD is not set
|
||||
# CONFIG_NSH_DISABLE_RM is not set
|
||||
@@ -743,6 +973,37 @@ CONFIG_NSH_FILEIOSIZE=1024
|
||||
CONFIG_NSH_CONSOLE=y
|
||||
# CONFIG_NSH_ALTCONDEV is not set
|
||||
# CONFIG_NSH_ARCHINIT is not set
|
||||
|
||||
#
|
||||
# Networking Configuration
|
||||
#
|
||||
CONFIG_NSH_NETINIT=y
|
||||
CONFIG_NSH_NETINIT_THREAD=y
|
||||
CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568
|
||||
CONFIG_NSH_NETINIT_THREAD_PRIORITY=80
|
||||
CONFIG_NSH_NETINIT_DEBUG=y
|
||||
|
||||
#
|
||||
# IP Address Configuration
|
||||
#
|
||||
# CONFIG_NSH_DHCPC is not set
|
||||
|
||||
#
|
||||
# IPv4 Addresses
|
||||
#
|
||||
CONFIG_NSH_IPADDR=0xc0a80132
|
||||
CONFIG_NSH_DRIPADDR=0xc0a80101
|
||||
CONFIG_NSH_NETMASK=0xffffff00
|
||||
# CONFIG_NSH_DNS is not set
|
||||
CONFIG_NSH_NOMAC=y
|
||||
CONFIG_NSH_SWMAC=y
|
||||
CONFIG_NSH_MACADDR=0x00e0deadbeef
|
||||
CONFIG_NSH_MAX_ROUNDTRIP=20
|
||||
|
||||
#
|
||||
# Telnet Configuration
|
||||
#
|
||||
# CONFIG_NSH_TELNET is not set
|
||||
# CONFIG_NSH_LOGIN is not set
|
||||
# CONFIG_NSH_CONSOLE_LOGIN is not set
|
||||
|
||||
@@ -765,6 +1026,7 @@ CONFIG_SYSTEM_CLE_DEBUGLEVEL=0
|
||||
# CONFIG_SYSTEM_HEX2BIN is not set
|
||||
# CONFIG_SYSTEM_HEXED is not set
|
||||
# CONFIG_SYSTEM_INSTALL is not set
|
||||
# CONFIG_SYSTEM_NETDB is not set
|
||||
# CONFIG_SYSTEM_RAMTEST is not set
|
||||
CONFIG_READLINE_HAVE_EXTMATCH=y
|
||||
CONFIG_SYSTEM_READLINE=y
|
||||
|
||||
@@ -1,49 +0,0 @@
|
||||
/****************************************************************************
|
||||
* configs/misoc/include/generated/common.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Ramtin Amin <keytwo@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H
|
||||
#define __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
# define MMPTR(x) x
|
||||
#else
|
||||
# define MMPTR(x) (*((volatile unsigned int *)(x)))
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H */
|
||||
@@ -1,250 +0,0 @@
|
||||
#ifndef __GENERATED_CSR_H
|
||||
#define __GENERATED_CSR_H
|
||||
#include <hw/common.h>
|
||||
|
||||
/* sdram */
|
||||
#define CSR_SDRAM_BASE 0xe0004000
|
||||
#define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000
|
||||
#define CSR_SDRAM_DFII_CONTROL_SIZE 1
|
||||
static inline unsigned char sdram_dfii_control_read(void) {
|
||||
unsigned char r = MMPTR(0xe0004000);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_control_write(unsigned char value) {
|
||||
MMPTR(0xe0004000) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004
|
||||
#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1
|
||||
static inline unsigned char sdram_dfii_pi0_command_read(void) {
|
||||
unsigned char r = MMPTR(0xe0004004);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_pi0_command_write(unsigned char value) {
|
||||
MMPTR(0xe0004004) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008
|
||||
#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1
|
||||
static inline unsigned char sdram_dfii_pi0_command_issue_read(void) {
|
||||
unsigned char r = MMPTR(0xe0004008);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) {
|
||||
MMPTR(0xe0004008) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c
|
||||
#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2
|
||||
static inline unsigned short int sdram_dfii_pi0_address_read(void) {
|
||||
unsigned short int r = MMPTR(0xe000400c);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0004010);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_pi0_address_write(unsigned short int value) {
|
||||
MMPTR(0xe000400c) = value >> 8;
|
||||
MMPTR(0xe0004010) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014
|
||||
#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1
|
||||
static inline unsigned char sdram_dfii_pi0_baddress_read(void) {
|
||||
unsigned char r = MMPTR(0xe0004014);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_pi0_baddress_write(unsigned char value) {
|
||||
MMPTR(0xe0004014) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018
|
||||
#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2
|
||||
static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) {
|
||||
unsigned short int r = MMPTR(0xe0004018);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe000401c);
|
||||
return r;
|
||||
}
|
||||
static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) {
|
||||
MMPTR(0xe0004018) = value >> 8;
|
||||
MMPTR(0xe000401c) = value;
|
||||
}
|
||||
#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004020
|
||||
#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2
|
||||
static inline unsigned short int sdram_dfii_pi0_rddata_read(void) {
|
||||
unsigned short int r = MMPTR(0xe0004020);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0004024);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* timer0 */
|
||||
#define CSR_TIMER0_BASE 0xe0002000
|
||||
#define CSR_TIMER0_LOAD_ADDR 0xe0002000
|
||||
#define CSR_TIMER0_LOAD_SIZE 4
|
||||
static inline unsigned int timer0_load_read(void) {
|
||||
unsigned int r = MMPTR(0xe0002000);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002004);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002008);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe000200c);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_load_write(unsigned int value) {
|
||||
MMPTR(0xe0002000) = value >> 24;
|
||||
MMPTR(0xe0002004) = value >> 16;
|
||||
MMPTR(0xe0002008) = value >> 8;
|
||||
MMPTR(0xe000200c) = value;
|
||||
}
|
||||
#define CSR_TIMER0_RELOAD_ADDR 0xe0002010
|
||||
#define CSR_TIMER0_RELOAD_SIZE 4
|
||||
static inline unsigned int timer0_reload_read(void) {
|
||||
unsigned int r = MMPTR(0xe0002010);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002014);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002018);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe000201c);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_reload_write(unsigned int value) {
|
||||
MMPTR(0xe0002010) = value >> 24;
|
||||
MMPTR(0xe0002014) = value >> 16;
|
||||
MMPTR(0xe0002018) = value >> 8;
|
||||
MMPTR(0xe000201c) = value;
|
||||
}
|
||||
#define CSR_TIMER0_EN_ADDR 0xe0002020
|
||||
#define CSR_TIMER0_EN_SIZE 1
|
||||
static inline unsigned char timer0_en_read(void) {
|
||||
unsigned char r = MMPTR(0xe0002020);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_en_write(unsigned char value) {
|
||||
MMPTR(0xe0002020) = value;
|
||||
}
|
||||
#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024
|
||||
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
|
||||
static inline unsigned char timer0_update_value_read(void) {
|
||||
unsigned char r = MMPTR(0xe0002024);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_update_value_write(unsigned char value) {
|
||||
MMPTR(0xe0002024) = value;
|
||||
}
|
||||
#define CSR_TIMER0_VALUE_ADDR 0xe0002028
|
||||
#define CSR_TIMER0_VALUE_SIZE 4
|
||||
static inline unsigned int timer0_value_read(void) {
|
||||
unsigned int r = MMPTR(0xe0002028);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe000202c);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002030);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0002034);
|
||||
return r;
|
||||
}
|
||||
#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038
|
||||
#define CSR_TIMER0_EV_STATUS_SIZE 1
|
||||
static inline unsigned char timer0_ev_status_read(void) {
|
||||
unsigned char r = MMPTR(0xe0002038);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_ev_status_write(unsigned char value) {
|
||||
MMPTR(0xe0002038) = value;
|
||||
}
|
||||
#define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c
|
||||
#define CSR_TIMER0_EV_PENDING_SIZE 1
|
||||
static inline unsigned char timer0_ev_pending_read(void) {
|
||||
unsigned char r = MMPTR(0xe000203c);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_ev_pending_write(unsigned char value) {
|
||||
MMPTR(0xe000203c) = value;
|
||||
}
|
||||
#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040
|
||||
#define CSR_TIMER0_EV_ENABLE_SIZE 1
|
||||
static inline unsigned char timer0_ev_enable_read(void) {
|
||||
unsigned char r = MMPTR(0xe0002040);
|
||||
return r;
|
||||
}
|
||||
static inline void timer0_ev_enable_write(unsigned char value) {
|
||||
MMPTR(0xe0002040) = value;
|
||||
}
|
||||
|
||||
/* uart */
|
||||
#define CSR_UART_BASE 0xe0001000
|
||||
#define CSR_UART_RXTX_ADDR 0xe0001000
|
||||
#define CSR_UART_RXTX_SIZE 1
|
||||
static inline unsigned char uart_rxtx_read(void) {
|
||||
unsigned char r = MMPTR(0xe0001000);
|
||||
return r;
|
||||
}
|
||||
static inline void uart_rxtx_write(unsigned char value) {
|
||||
MMPTR(0xe0001000) = value;
|
||||
}
|
||||
#define CSR_UART_TXFULL_ADDR 0xe0001004
|
||||
#define CSR_UART_TXFULL_SIZE 1
|
||||
static inline unsigned char uart_txfull_read(void) {
|
||||
unsigned char r = MMPTR(0xe0001004);
|
||||
return r;
|
||||
}
|
||||
#define CSR_UART_RXEMPTY_ADDR 0xe0001008
|
||||
#define CSR_UART_RXEMPTY_SIZE 1
|
||||
static inline unsigned char uart_rxempty_read(void) {
|
||||
unsigned char r = MMPTR(0xe0001008);
|
||||
return r;
|
||||
}
|
||||
#define CSR_UART_EV_STATUS_ADDR 0xe000100c
|
||||
#define CSR_UART_EV_STATUS_SIZE 1
|
||||
static inline unsigned char uart_ev_status_read(void) {
|
||||
unsigned char r = MMPTR(0xe000100c);
|
||||
return r;
|
||||
}
|
||||
static inline void uart_ev_status_write(unsigned char value) {
|
||||
MMPTR(0xe000100c) = value;
|
||||
}
|
||||
#define CSR_UART_EV_PENDING_ADDR 0xe0001010
|
||||
#define CSR_UART_EV_PENDING_SIZE 1
|
||||
static inline unsigned char uart_ev_pending_read(void) {
|
||||
unsigned char r = MMPTR(0xe0001010);
|
||||
return r;
|
||||
}
|
||||
static inline void uart_ev_pending_write(unsigned char value) {
|
||||
MMPTR(0xe0001010) = value;
|
||||
}
|
||||
#define CSR_UART_EV_ENABLE_ADDR 0xe0001014
|
||||
#define CSR_UART_EV_ENABLE_SIZE 1
|
||||
static inline unsigned char uart_ev_enable_read(void) {
|
||||
unsigned char r = MMPTR(0xe0001014);
|
||||
return r;
|
||||
}
|
||||
static inline void uart_ev_enable_write(unsigned char value) {
|
||||
MMPTR(0xe0001014) = value;
|
||||
}
|
||||
|
||||
/* uart_phy */
|
||||
#define CSR_UART_PHY_BASE 0xe0000800
|
||||
#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800
|
||||
#define CSR_UART_PHY_TUNING_WORD_SIZE 4
|
||||
static inline unsigned int uart_phy_tuning_word_read(void) {
|
||||
unsigned int r = MMPTR(0xe0000800);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0000804);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe0000808);
|
||||
r <<= 8;
|
||||
r |= MMPTR(0xe000080c);
|
||||
return r;
|
||||
}
|
||||
static inline void uart_phy_tuning_word_write(unsigned int value) {
|
||||
MMPTR(0xe0000800) = value >> 24;
|
||||
MMPTR(0xe0000804) = value >> 16;
|
||||
MMPTR(0xe0000808) = value >> 8;
|
||||
MMPTR(0xe000080c) = value;
|
||||
}
|
||||
|
||||
/* constants */
|
||||
#define UART_INTERRUPT 0
|
||||
#define TIMER0_INTERRUPT 1
|
||||
#define SYSTEM_CLOCK_FREQUENCY 80000000
|
||||
#define L2_SIZE 8192
|
||||
|
||||
#endif
|
||||
@@ -1,13 +0,0 @@
|
||||
#ifndef __GENERATED_MEM_H
|
||||
#define __GENERATED_MEM_H
|
||||
|
||||
#define ROM_BASE 0x00000000
|
||||
#define ROM_SIZE 0x00008000
|
||||
|
||||
#define SRAM_BASE 0x10000000
|
||||
#define SRAM_SIZE 0x00001000
|
||||
|
||||
#define MAIN_RAM_BASE 0x40000000
|
||||
#define MAIN_RAM_SIZE 0x00800000
|
||||
|
||||
#endif
|
||||
@@ -1 +0,0 @@
|
||||
OUTPUT_FORMAT("elf32-lm32")
|
||||
@@ -1,5 +0,0 @@
|
||||
MEMORY {
|
||||
rom : ORIGIN = 0x00000000, LENGTH = 0x00008000
|
||||
sram : ORIGIN = 0x10000000, LENGTH = 0x00001000
|
||||
main_ram : ORIGIN = 0x40000000, LENGTH = 0x00800000
|
||||
}
|
||||
@@ -1,80 +0,0 @@
|
||||
#ifndef __GENERATED_SDRAM_PHY_H
|
||||
#define __GENERATED_SDRAM_PHY_H
|
||||
#include <hw/common.h>
|
||||
#include <generated/csr.h>
|
||||
#include <hw/flags.h>
|
||||
|
||||
#define DFII_NPHASES 1
|
||||
|
||||
static void cdelay(int i);
|
||||
|
||||
static void command_p0(int cmd)
|
||||
{
|
||||
sdram_dfii_pi0_command_write(cmd);
|
||||
sdram_dfii_pi0_command_issue_write(1);
|
||||
}
|
||||
|
||||
|
||||
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
|
||||
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
|
||||
|
||||
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
|
||||
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
|
||||
|
||||
#define command_prd(X) command_p0(X)
|
||||
#define command_pwr(X) command_p0(X)
|
||||
|
||||
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
|
||||
|
||||
const unsigned int sdram_dfii_pix_wrdata_addr[1] = {
|
||||
CSR_SDRAM_DFII_PI0_WRDATA_ADDR
|
||||
};
|
||||
|
||||
const unsigned int sdram_dfii_pix_rddata_addr[1] = {
|
||||
CSR_SDRAM_DFII_PI0_RDDATA_ADDR
|
||||
};
|
||||
|
||||
static void init_sequence(void)
|
||||
{
|
||||
/* Bring CKE high */
|
||||
sdram_dfii_pi0_address_write(0x0);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
|
||||
cdelay(20000);
|
||||
|
||||
/* Precharge All */
|
||||
sdram_dfii_pi0_address_write(0x400);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
|
||||
|
||||
/* Load Mode Register / Reset DLL, CL=2, BL=1 */
|
||||
sdram_dfii_pi0_address_write(0x120);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
|
||||
cdelay(200);
|
||||
|
||||
/* Precharge All */
|
||||
sdram_dfii_pi0_address_write(0x400);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
|
||||
|
||||
/* Auto Refresh */
|
||||
sdram_dfii_pi0_address_write(0x0);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
|
||||
cdelay(4);
|
||||
|
||||
/* Auto Refresh */
|
||||
sdram_dfii_pi0_address_write(0x0);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
|
||||
cdelay(4);
|
||||
|
||||
/* Load Mode Register / CL=2, BL=1 */
|
||||
sdram_dfii_pi0_address_write(0x20);
|
||||
sdram_dfii_pi0_baddress_write(0);
|
||||
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
|
||||
cdelay(200);
|
||||
|
||||
}
|
||||
#endif
|
||||
@@ -1,11 +0,0 @@
|
||||
TRIPLE=lm32-elf
|
||||
CPU=lm32
|
||||
CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled
|
||||
CPUENDIANNESS=big
|
||||
CLANG=0
|
||||
SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc
|
||||
BUILDINC_DIRECTORY=/home/lenovo/fpga/litex/litex/boards/targets/soc_basesoc_papilio_pro/software/include
|
||||
LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase
|
||||
LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt
|
||||
LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet
|
||||
BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios
|
||||
Reference in New Issue
Block a user