mirror of
https://github.com/apache/nuttx.git
synced 2026-05-25 09:45:55 +08:00
Add uid file needed for ethernet
copied over files, not modified properly yet Squashing lots of define errors to get ethernet.c working quick path rename Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does). Fixed stm32_get_uniqueid Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations. Turn on SBS peripheral when using Ethernet The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either. Style Updates
This commit is contained in:
stbenn
Alan C. Assis
@@ -103,4 +103,10 @@
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
|
||||
|
||||
#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
|
||||
# define STM32H5_NETHERNET 1 /* Ethernet MAC */
|
||||
#else
|
||||
# define STM32H5_NETHERNET 0 /* No Ethernet MAC */
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */
|
||||
|
||||
@@ -31,12 +31,10 @@ include armv8-m/Make.defs
|
||||
|
||||
# Required STM32H5 files
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = stm32_gpio.c
|
||||
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c
|
||||
CHIP_CSRCS += stm32_serial.c stm32_start.c
|
||||
CHIP_CSRCS += stm32_pwr.c stm32_timerisr.c
|
||||
CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c
|
||||
CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_pwr.c stm32_timerisr.c
|
||||
CHIP_CSRCS += stm32_lse.c stm32_lsi.c
|
||||
CHIP_CSRCS += stm32_uid.c stm32_ethernet.c
|
||||
|
||||
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
|
||||
CHIP_CSRCS += stm32_idle.c
|
||||
|
||||
@@ -50,4 +50,12 @@
|
||||
|
||||
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
|
||||
|
||||
/* Cache line sizes set in line with ST document RM0481 Rev 2.
|
||||
* DCACHE implementation, pg 284, Table 93
|
||||
* ICACHE implementation, pg 367, Table 85.
|
||||
*/
|
||||
|
||||
#define ARMV8M_ICACHE_LINESIZE 16 /* 16 bytes */
|
||||
#define ARMV8M_DCACHE_LINESIZE 16 /* 16 bytes */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_CHIP_H */
|
||||
|
||||
@@ -93,8 +93,8 @@
|
||||
#define SBS_PMCR_PB9_FMP (1 << 19) /* Fast-mode Plus on PB9*/
|
||||
|
||||
#define SBS_PMCR_ETH_SEL_PHY_SHIFT (21) /* Bits 23-21 Ethernet PHY interface selection */
|
||||
#define SBS_PMCR_ETH_SEL_PHY_MASK (0b111 << SBS_ETH_SEL_PHY_SHIFT)
|
||||
# define SBS_PMCR_ETH_SEL_PHY_GMII_OR_MII (0 << SBS_ETH_SEL_PHY_SHIFT)
|
||||
# define SBS_PMCR_ETH_SEL_PHY_RMII (4 << SBS_ETH_SEL_PHY_SHIFT)
|
||||
#define SBS_PMCR_ETH_SEL_PHY_MASK (0b111 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
|
||||
# define SBS_PMCR_ETH_SEL_PHY_GMII_OR_MII (0 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
|
||||
# define SBS_PMCR_ETH_SEL_PHY_RMII (4 << SBS_PMCR_ETH_SEL_PHY_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_SBS_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_ethernet.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hardware/stm32_ethernet.h"
|
||||
|
||||
#if STM32H5_NETHERNET > 0
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_ethinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Ethernet driver for one interface. If the STM32 chip
|
||||
* supports multiple Ethernet controllers, then board specific logic must
|
||||
* implement arm_netinitialize() and call this function to initialize the
|
||||
* desired interfaces.
|
||||
*
|
||||
* Parameters:
|
||||
* intf - In the case where there are multiple EMACs, this value identifies
|
||||
* which EMAC is to be initialized.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
|
||||
int stm32_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_phy_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* Some boards require specialized initialization of the PHY before it can
|
||||
* be used. This may include such things as configuring GPIOs, resetting
|
||||
* the PHY, etc. If CONFIG_STM32H5_PHYINIT is defined in the configuration
|
||||
* then the board specific logic must provide stm32_phyinitialize(); The
|
||||
* STM32 Ethernet driver will call this function one time before it first
|
||||
* uses the PHY.
|
||||
*
|
||||
* Parameters:
|
||||
* intf - Always zero for now.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H5_PHYINIT
|
||||
int stm32_phy_boardinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* STM32H5_NETHERNET > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_uid.c
|
||||
*
|
||||
* Copyright (C) 2015 Marawan Ragab. All rights reserved.
|
||||
* Authors: Marawan Ragab <marawan31@gmail.com>
|
||||
* David Sidrane <david.sirane@nscdg.com>
|
||||
* Modified for STM32H5 by Tyler Bennett <tbennett@2g-eng.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hardware/stm32_memorymap.h"
|
||||
|
||||
#include "stm32_uid.h"
|
||||
|
||||
#ifdef STM32_SYSMEM_UID
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_get_uniqueid(uint8_t uniqueid[12])
|
||||
{
|
||||
int i;
|
||||
uint32_t *uid = (uint32_t *) uniqueid;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
*uid = *((uint32_t *)(STM32_SYSMEM_UID) + i);
|
||||
uid++;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32_SYSMEM_UID */
|
||||
@@ -0,0 +1,53 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_uid.h
|
||||
*
|
||||
* Copyright (C) 2015 Marawan Ragab. All rights reserved.
|
||||
* Authors: Marawan Ragab <marawan31@gmail.com>
|
||||
* David Sidrane <david.sirane@nscdg.com>
|
||||
* Modified for STM32H5 by Tyler Bennett <tbennett@2g-eng.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_UID_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_UID_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_get_uniqueid(uint8_t uniqueid[12]);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_UID_H */
|
||||
@@ -130,18 +130,15 @@ static inline void rcc_enableahb1(void)
|
||||
regval |= RCC_AHB1ENR_RAMCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_ETH
|
||||
#ifdef CONFIG_STM32H5_ETHMAC
|
||||
/* ETH clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_ETHEN;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32H5_ETHTX
|
||||
|
||||
/* ETH TX clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_ETHTXEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_ETHRX
|
||||
/* ETH RX clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_ETHRXEN;
|
||||
@@ -597,7 +594,7 @@ static inline void rcc_enableapb3(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB3ENR);
|
||||
|
||||
#ifdef CONFIG_STM32H5_SBS
|
||||
#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32H5_ETHMAC)
|
||||
/* Bit 1: SBS clock enable */
|
||||
|
||||
regval |= RCC_APB3ENR_SBSEN;
|
||||
|
||||
@@ -231,15 +231,15 @@
|
||||
|
||||
/* Ethernet definitions *****************************************************/
|
||||
|
||||
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /* PC1 */
|
||||
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /* PA2 */
|
||||
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /* PC4 */
|
||||
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /* PC5 */
|
||||
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_3 | GPIO_SPEED_100MHz) /* PG13 */
|
||||
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /* PB15 */
|
||||
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_3 | GPIO_SPEED_100MHz) /* PG11 */
|
||||
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /* PA7 */
|
||||
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */
|
||||
#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHZ) /* PC1 */
|
||||
#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHZ) /* PA2 */
|
||||
#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHZ) /* PC4 */
|
||||
#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHZ) /* PC5 */
|
||||
#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_3 | GPIO_SPEED_100MHZ) /* PG13 */
|
||||
#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHZ) /* PB15 */
|
||||
#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_3 | GPIO_SPEED_100MHZ) /* PG11 */
|
||||
#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHZ) /* PA7 */
|
||||
#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHZ) /* PA1 */
|
||||
|
||||
/* ADC Clock Source *********************************************************/
|
||||
|
||||
|
||||
Reference in New Issue
Block a user