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synced 2026-05-13 02:18:38 +08:00
arch/imx9: Fix uSDHC driver DMA and cache compilation flags
All combinations of CONFIG_IMX9_USDHC_DMA and CONFIG_ARM64_DCACHE_DISABLE are valid. Only the required alignment of the DMA buffers are different, If the cache is enabled, cacle-line aligned buffers need to be used. Otherwise, the USDHC DMA alignment requirement is just 32-bits. Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen
committed by
Matteo Golin
Matteo Golin
parent
72b67832ea
commit
b4ccaf4b1c
@@ -69,9 +69,11 @@
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#define DCACHE_LINEMASK (ARMV8A_DCACHE_LINESIZE - 1)
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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# define USDHC_DATABUF_ALIGN ARMV8A_DCACHE_LINESIZE
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# define cache_aligned_alloc(s) kmm_memalign(ARMV8A_DCACHE_LINESIZE,(s))
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# define CACHE_ALIGNED_DATA aligned_data(ARMV8A_DCACHE_LINESIZE)
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#else
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# define USDHC_DATABUF_ALIGN sizeof(uint32_t)
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# define cache_aligned_alloc kmm_malloc
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# define CACHE_ALIGNED_DATA
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#endif
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@@ -87,12 +89,6 @@
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#error Unrecognised number of SDHC slots
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#endif
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#if !defined(CONFIG_IMX9_USDHC_DMA)
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# warning "Large Non-DMA transfer may result in RX overrun failures"
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#elif !defined(CONFIG_SDIO_DMA)
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# warning CONFIG_SDIO_DMA should be defined with CONFIG_IMX9_USDHC_DMA
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#endif
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#if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK)
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# error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK"
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#endif
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@@ -126,7 +122,7 @@
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/* Block size for multi-block transfers */
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#define SDMMC_MAX_BLOCK_SIZE (512)
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#define USDHC_MAX_BLOCK_SIZE (512)
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/* Data transfer / Event waiting interrupt mask bits */
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@@ -202,19 +198,17 @@ struct imx9_dev_s
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size_t remaining; /* Number of bytes remaining in the
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* transfer */
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uint32_t xfrints; /* Interrupt enables for data transfer */
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#ifdef CONFIG_IMX9_USDHC_DMA
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/* DMA data transfer support */
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volatile uint8_t xfrflags; /* Used to synchronize SDIO and DMA
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* completion */
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/* DMA buffer for unaligned transfers */
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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/* DMA data transfer support */
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#if defined(CONFIG_IMX9_USDHC_DMA)
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uint32_t blocksize; /* Current block size */
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uint8_t rxbuffer[SDMMC_MAX_BLOCK_SIZE]
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__attribute__((aligned(ARMV8A_DCACHE_LINESIZE)));
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uint8_t rxbuffer[USDHC_MAX_BLOCK_SIZE]
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__attribute__((aligned(USDHC_DATABUF_ALIGN)));
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bool unaligned_rx; /* buffer is not cache-line aligned */
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#endif
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#endif
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/* Card interrupt support for SDIO */
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@@ -304,10 +298,9 @@ static void imx9_dataconfig(struct imx9_dev_s *priv, bool bwrite,
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#ifndef CONFIG_IMX9_USDHC_DMA
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static void imx9_transmit(struct imx9_dev_s *priv);
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static void imx9_receive(struct imx9_dev_s *priv);
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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#else
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static void imx9_recvdma(struct imx9_dev_s *priv);
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#endif
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#endif
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static void imx9_eventtimeout(wdparm_t arg);
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static void imx9_endwait(struct imx9_dev_s *priv,
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@@ -799,7 +792,7 @@ static void imx9_dataconfig(struct imx9_dev_s *priv, bool bwrite,
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regval |= timeout << USDHC_SYSCTL_DTOCV_SHIFT;
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putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
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#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE)
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#if defined(CONFIG_IMX9_USDHC_DMA)
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/* If cache is enabled, and this is an unaligned receive,
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* receive one block at a time to the internal buffer
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*/
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@@ -1034,14 +1027,14 @@ static void imx9_receive(struct imx9_dev_s *priv)
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* Receive SDIO data in dma mode
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*
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* Input Parameters:
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* priv - Instance of the SDMMC private state structure.
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* priv - Instance of the USDHC private state structure.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE)
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#if defined(CONFIG_IMX9_USDHC_DMA)
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static void imx9_recvdma(struct imx9_dev_s *priv)
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{
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unsigned int watermark;
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@@ -1052,10 +1045,12 @@ static void imx9_recvdma(struct imx9_dev_s *priv)
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* we receive them one-by-one
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*/
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# if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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/* Invalidate the cache before receiving next block */
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up_invalidate_dcache((uintptr_t)priv->rxbuffer,
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(uintptr_t)priv->rxbuffer + priv->blocksize);
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#endif
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/* Copy the received data to client buffer */
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@@ -1067,10 +1062,12 @@ static void imx9_recvdma(struct imx9_dev_s *priv)
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}
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else
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{
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# if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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/* In an aligned case, we have always received all blocks */
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up_invalidate_dcache((uintptr_t)priv->buffer,
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(uintptr_t)priv->buffer + priv->remaining);
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# endif
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priv->remaining = 0;
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}
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@@ -1304,7 +1301,7 @@ static int imx9_interrupt(int irq, void *context, void *arg)
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if ((pending & USDHC_INT_TC) != 0)
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{
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/* Terminate the transfer */
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#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE)
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#if defined(CONFIG_IMX9_USDHC_DMA)
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imx9_recvdma(priv);
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#else
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imx9_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
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@@ -2254,7 +2251,7 @@ static void imx9_blocksetup(struct sdio_dev_s *dev,
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/* Configure block size for next transfer */
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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#ifdef CONFIG_IMX9_USDHC_DMA
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priv->blocksize = blocklen;
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#endif
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@@ -2981,8 +2978,8 @@ static int imx9_dmapreflight(struct sdio_dev_s *dev,
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*/
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if (buffer != priv->rxbuffer &&
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(((uintptr_t)buffer & (ARMV8A_DCACHE_LINESIZE - 1)) != 0 ||
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((uintptr_t)(buffer + buflen) & (ARMV8A_DCACHE_LINESIZE - 1)) != 0))
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(((uintptr_t)buffer & (USDHC_DATABUF_ALIGN - 1)) != 0 ||
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((uintptr_t)(buffer + buflen) & (USDHC_DATABUF_ALIGN - 1)) != 0))
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{
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mcerr("dcache unaligned buffer:%p end:%p\n",
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buffer, buffer + buflen - 1);
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@@ -3020,8 +3017,7 @@ static int imx9_dmarecvsetup(struct sdio_dev_s *dev,
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struct imx9_dev_s *priv = (struct imx9_dev_s *)dev;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) && \
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!defined(CONFIG_ARM64_DCACHE_DISABLE)
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#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT)
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/* Normally imx9_dmapreflight is called prior to imx9_dmarecvsetup
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* except for the case where the CSR read is done at initialization.
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*
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@@ -3040,27 +3036,29 @@ static int imx9_dmarecvsetup(struct sdio_dev_s *dev,
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imx9_sampleinit();
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imx9_sample(priv, SAMPLENDX_BEFORE_SETUP);
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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if (((uintptr_t)buffer & (ARMV8A_DCACHE_LINESIZE - 1)) != 0 ||
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(buflen & (ARMV8A_DCACHE_LINESIZE - 1)) != 0)
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if (((uintptr_t)buffer & (USDHC_DATABUF_ALIGN - 1)) != 0 ||
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(buflen & (USDHC_DATABUF_ALIGN - 1)) != 0)
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{
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/* The read buffer is not cache-line aligned, but will fit in
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/* The read buffer is not aligned, but will fit in
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* the rxbuffer. So read to an internal buffer instead.
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*/
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# if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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up_invalidate_dcache((uintptr_t)priv->rxbuffer,
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(uintptr_t)priv->rxbuffer + priv->blocksize);
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# endif
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priv->unaligned_rx = true;
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}
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else
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{
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# if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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up_invalidate_dcache((uintptr_t)buffer,
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(uintptr_t)buffer + buflen);
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# endif
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priv->unaligned_rx = false;
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}
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#endif
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/* Save the destination buffer information for use by the interrupt
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* handler
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@@ -3076,14 +3074,12 @@ static int imx9_dmarecvsetup(struct sdio_dev_s *dev,
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/* Configure the RX DMA */
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imx9_configxfrints(priv, USDHC_DMADONE_INTS);
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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if (priv->unaligned_rx)
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{
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putreg32((uint64_t) priv->rxbuffer,
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priv->addr + IMX9_USDHC_DSADDR_OFFSET);
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}
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else
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#endif
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{
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putreg32((uint64_t) priv->buffer,
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priv->addr + IMX9_USDHC_DSADDR_OFFSET);
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@@ -3130,9 +3126,9 @@ static int imx9_dmasendsetup(struct sdio_dev_s *dev,
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/* Save the source buffer information for use by the interrupt handler */
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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priv->unaligned_rx = false;
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#if !defined(CONFIG_ARM64_DCACHE_DISABLE)
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/* Flush cache to physical memory when not in DTCM memory */
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up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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