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xtensa/esp32s3: Add support for Main System Watchdog Timers
Support for RTC Watchdog Timer is currently in place, but not yet functional due to not yet implemented RTC driver. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
committed by
Xiang Xiao
Xiang Xiao
parent
9603b8f67c
commit
b49ee3d4ed
@@ -306,6 +306,10 @@ config ESP32S3_TIMER
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bool
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default n
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config ESP32S3_WDT
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bool
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default n
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config ESP32S3_UART0
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bool "UART 0"
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default n
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@@ -355,6 +359,33 @@ config ESP32S3_TIMER3
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---help---
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Enables Timer 3
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config ESP32S3_MWDT0
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bool "Main System Watchdog Timer (Group 0)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT0. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_MWDT1
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bool "Main System Watchdog Timer (Group 1)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT1. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_RWDT
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bool "RTC Watchdog Timer"
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default n
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select ESP32S3_WDT
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---help---
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Includes RWDT. This watchdog timer is from the RTC module.
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When it is selected, if the developer sets it to reset on expiration
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it will reset Main System and the RTC module. If you don't want
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to have the RTC module reset, please, use the Timers' Module WDTs.
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They will only reset Main System.
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endmenu # ESP32-S3 Peripheral Selection
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menu "UART configuration"
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@@ -79,3 +79,7 @@ ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += esp32s3_tim_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_WATCHDOG),y)
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CHIP_CSRCS += esp32s3_wdt_lowerhalf.c
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endif
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File diff suppressed because it is too large
Load Diff
@@ -25,10 +25,125 @@
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/irq.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Helpers ******************************************************************/
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#define ESP32S3_WDT_START(d) ((d)->ops->start(d))
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#define ESP32S3_WDT_STOP(d) ((d)->ops->stop(d))
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#define ESP32S3_WDT_LOCK(d) ((d)->ops->enablewp(d))
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#define ESP32S3_WDT_UNLOCK(d) ((d)->ops->disablewp(d))
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#define ESP32S3_MWDT_PRE(d, v) ((d)->ops->pre(d, v))
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#define ESP32S3_WDT_STO(d, v, s) ((d)->ops->settimeout(d, v, s))
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#define ESP32S3_WDT_FEED(d) ((d)->ops->feed(d))
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#define ESP32S3_WDT_STG_CONF(d, s, c) ((d)->ops->stg_conf(d, s, c))
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#define ESP32S3_RWDT_CLK(d) ((d)->ops->rtc_clk(d))
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#define ESP32S3_WDT_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg))
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#define ESP32S3_WDT_ENABLEINT(d) ((d)->ops->enableint(d))
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#define ESP32S3_WDT_DISABLEINT(d) ((d)->ops->disableint(d))
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#define ESP32S3_WDT_ACKINT(d) ((d)->ops->ackint(d))
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* Instances of Watchdog Timer */
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enum esp32s3_wdt_inst_e
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{
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ESP32S3_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */
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ESP32S3_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */
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ESP32S3_WDT_RWDT /* RTC Watchdog Timer (RWDT) */
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};
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/* Stages of a Watchdog Timer. A WDT has 4 stages. */
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enum esp32s3_wdt_stage_e
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{
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ESP32S3_WDT_STAGE0 = 0, /* Stage 0 */
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ESP32S3_WDT_STAGE1 = 1, /* Stage 1 */
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ESP32S3_WDT_STAGE2 = 2, /* Stage 2 */
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ESP32S3_WDT_STAGE3 = 3 /* Stage 3 */
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};
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/**
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* Behavior of the WDT stage if it times out.
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*
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* @note These enum values should be compatible with the
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* corresponding register field values.
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*/
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enum esp32s3_wdt_stage_action_e
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{
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ESP32S3_WDT_STAGE_ACTION_OFF = 0, /* Disabled. This stage will have no effects on the system. */
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ESP32S3_WDT_STAGE_ACTION_INT = 1, /* Trigger an interrupt when the stage expires. */
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ESP32S3_WDT_STAGE_ACTION_RESET_CPU = 2, /* Reset a CPU core when the stage expires. */
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ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM = 3, /* Reset the main system when the stage expires.
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* This includes the CPU and all peripherals.
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* The RTC is an exception and will not be reset.
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*/
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ESP32S3_WDT_STAGE_ACTION_RESET_RTC = 4 /* Reset the main system and the RTC when the stage expires.
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* ONLY AVAILABLE FOR RWDT.
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*/
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};
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/* ESP32-S3 WDT device */
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struct esp32s3_wdt_dev_s
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{
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struct esp32s3_wdt_ops_s *ops;
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};
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/* ESP32-S3 WDT operations
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*
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* This is a struct containing the pointers to the WDT operations.
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*/
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struct esp32s3_wdt_ops_s
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{
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/* WDT tasks */
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void (*start)(struct esp32s3_wdt_dev_s *dev);
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void (*stop)(struct esp32s3_wdt_dev_s *dev);
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/* WDT configuration */
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void (*enablewp)(struct esp32s3_wdt_dev_s *dev);
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void (*disablewp)(struct esp32s3_wdt_dev_s *dev);
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void (*pre)(struct esp32s3_wdt_dev_s *dev, uint16_t value);
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int32_t (*settimeout)(struct esp32s3_wdt_dev_s *dev,
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uint32_t value,
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enum esp32s3_wdt_stage_e stage);
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void (*feed)(struct esp32s3_wdt_dev_s *dev);
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int32_t (*stg_conf)(struct esp32s3_wdt_dev_s *dev,
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enum esp32s3_wdt_stage_e stage,
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enum esp32s3_wdt_stage_action_e conf);
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uint16_t (*rtc_clk)(struct esp32s3_wdt_dev_s *dev);
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/* WDT interrupts */
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int32_t (*setisr)(struct esp32s3_wdt_dev_s *dev, xcpt_t handler,
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void *arg);
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void (*enableint)(struct esp32s3_wdt_dev_s *dev);
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void (*disableint)(struct esp32s3_wdt_dev_s *dev);
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void (*ackint)(struct esp32s3_wdt_dev_s *dev);
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};
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id);
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void esp32s3_wdt_early_deinit(void);
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void esp32s3_wdt_deinit(struct esp32s3_wdt_dev_s *dev);
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bool esp32s3_wdt_is_running(struct esp32s3_wdt_dev_s *dev);
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,57 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H
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#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "esp32s3_wdt.h"
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s3_wdt_initialize
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*
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* Description:
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* Initialize the watchdog timer. The watchdog timer is initialized
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* and registered as 'devpath'.
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*
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* Input Parameters:
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* devpath - The full path to the watchdog.
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* wdt - WDT instance to be initialized.
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*
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* Returned Values:
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* Zero (OK) is returned on success; a negated errno value is returned on
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* any failure.
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*
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****************************************************************************/
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int esp32s3_wdt_initialize(const char *devpath, enum esp32s3_wdt_inst_e wdt);
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_LOWERHALF_H */
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File diff suppressed because it is too large
Load Diff
@@ -31,12 +31,49 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Offset relative to each watchdog timer instance memory base */
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#define RWDT_CONFIG0_OFFSET 0x0090
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/* RWDT */
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#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0094
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#define RWDT_STAGE1_TIMEOUT_OFFSET 0x0098
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#define RWDT_STAGE2_TIMEOUT_OFFSET 0x009c
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#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00a0
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#define RWDT_FEED_OFFSET 0x00a4
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#define RWDT_WP_REG 0x00a8
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#define RWDT_INT_ENA_REG_OFFSET 0x0040
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#define RWDT_INT_CLR_REG_OFFSET 0x004c
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/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
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* write-enable the wdt registers
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*/
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#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1
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/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG
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* to write-enable the wdt registers
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*/
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#define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a
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/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH
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* and RTC_CNTL_WDT_SYS_RESET_LENGTH
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*/
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#define RTC_WDT_RESET_LENGTH_100_NS 0
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#define RTC_WDT_RESET_LENGTH_200_NS 1
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#define RTC_WDT_RESET_LENGTH_300_NS 2
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#define RTC_WDT_RESET_LENGTH_400_NS 3
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#define RTC_WDT_RESET_LENGTH_500_NS 4
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#define RTC_WDT_RESET_LENGTH_800_NS 5
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#define RTC_WDT_RESET_LENGTH_1600_NS 6
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#define RTC_WDT_RESET_LENGTH_3200_NS 7
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#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
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#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
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/* RTC_CNTL_RTC_OPTIONS0_REG register
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* RTC common configure register
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*/
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