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arch/arm/src/stm32: PLLI2S support for F427/F437. Enable support of the I2S Phase Locked Loop on STM32F427 and STM32F437 MCUs.

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This commit is contained in:
Michael Jung
2019-08-25 09:01:35 -06:00
committed by Gregory Nutt
parent 4227d2aaa5
commit b395cde043
3 changed files with 4 additions and 2 deletions
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arch/arm/src/stm32/Kconfig
+1
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@@ -1702,6 +1702,7 @@ config STM32_STM32F427
select STM32_HAVE_I2C3 select STM32_HAVE_I2C3
select STM32_HAVE_OTGFS select STM32_HAVE_OTGFS
select STM32_HAVE_SPI6 select STM32_HAVE_SPI6
select STM32_HAVE_I2SPLL
# This is really 429/439, but we treat the two the same. # This is really 429/439, but we treat the two the same.
arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
+2 -1
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@@ -159,7 +159,8 @@
#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT) #define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */ # define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F446) ||\
defined(CONFIG_STM32_STM32F469)
# define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: Main PLLR (PLLR) divider # define RCC_PLLCFG_PLLR_SHIFT (28) /* Bits 28-30: Main PLLR (PLLR) divider
* (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */ * (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */
# define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) # define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT)
arch/arm/src/stm32/stm32f40xxx_rcc.c
+1 -1
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@@ -901,7 +901,7 @@ static void stm32_stdclockconfig(void)
| STM32_RCC_PLLI2SCFGR_PLLI2SQ | STM32_RCC_PLLI2SCFGR_PLLI2SQ
| STM32_RCC_PLLI2SCFGR_PLLI2SR); | STM32_RCC_PLLI2SCFGR_PLLI2SR);
# elif defined(CONFIG_STM32_STM32F469) # elif defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F427)
regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
| RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SQ_MASK