diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index c6f589d89d2..23c2669d7c5 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -1702,6 +1702,7 @@ config STM32_STM32F427
 	select STM32_HAVE_I2C3
 	select STM32_HAVE_OTGFS
 	select STM32_HAVE_SPI6
+	select STM32_HAVE_I2SPLL
 
 # This is really 429/439, but we treat the two the same.
 
diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
index 1701c7b59da..b0b3feb1ec1 100644
--- a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
@@ -159,7 +159,8 @@
 #define RCC_PLLCFG_PLLQ_MASK        (15 << RCC_PLLCFG_PLLQ_SHIFT)
 #  define RCC_PLLCFG_PLLQ(n)        ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
 
-#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
+#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F446) ||\
+    defined(CONFIG_STM32_STM32F469)
 #  define RCC_PLLCFG_PLLR_SHIFT     (28)      /* Bits 28-30: Main PLLR (PLLR) divider
                                                * (I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks) */
 #  define RCC_PLLCFG_PLLR_MASK      (7 << RCC_PLLCFG_PLLR_SHIFT)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index d22111c87c1..02da518931d 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -901,7 +901,7 @@ static void stm32_stdclockconfig(void)
                 | STM32_RCC_PLLI2SCFGR_PLLI2SQ
                 | STM32_RCC_PLLI2SCFGR_PLLI2SR);
 
-#  elif defined(CONFIG_STM32_STM32F469)
+#  elif defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F427)
 
       regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
                  | RCC_PLLI2SCFGR_PLLI2SQ_MASK