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xtensa/esp32s2: enable sysclk and deassert reset signal for uart1

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The uart1 is found be in reset state, and the sysclk is not enabled
for it.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
This commit is contained in:
chenxiaoyi
2025-04-08 20:07:49 +08:00
committed by Xiang Xiao
parent 84cb21791f
commit b3567fe964
2 changed files with 3 additions and 0 deletions
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1
arch/xtensa/src/esp32s2/esp32s2_lowputc.c
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@@ -817,6 +817,7 @@ void esp32s2_lowsetup(void)
#ifdef CONFIG_ESP32S2_UART1 #ifdef CONFIG_ESP32S2_UART1
esp32s2_lowputc_rst_peripheral(&g_uart1_config);
esp32s2_lowputc_config_pins(&g_uart1_config); esp32s2_lowputc_config_pins(&g_uart1_config);
#endif #endif

2
arch/xtensa/src/esp32s2/esp32s2_serial.c
View File

@@ -301,6 +301,8 @@ static int esp32s2_setup(struct uart_dev_s *dev)
/* Initialize UART module */ /* Initialize UART module */
esp32s2_lowputc_enable_sysclk(priv);
/* Discard corrupt RX data */ /* Discard corrupt RX data */
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_ERR_WR_MASK_M); modifyreg32(UART_CONF0_REG(priv->id), 0, UART_ERR_WR_MASK_M);