xtensa/esp32s2: enable sysclk and deassert reset signal for uart1

The uart1 is found be in reset state, and the sysclk is not enabled
for it.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>

arch/xtensa/src/esp32s2/esp32s2_lowputc.c

@@ -817,6 +817,7 @@ void esp32s2_lowsetup(void)
 
 #ifdef CONFIG_ESP32S2_UART1
 
+  esp32s2_lowputc_rst_peripheral(&g_uart1_config);
   esp32s2_lowputc_config_pins(&g_uart1_config);
 
 #endif

arch/xtensa/src/esp32s2/esp32s2_serial.c

@@ -301,6 +301,8 @@ static int esp32s2_setup(struct uart_dev_s *dev)
 
   /* Initialize UART module */
 
+  esp32s2_lowputc_enable_sysclk(priv);
+
   /* Discard corrupt RX data */
 
   modifyreg32(UART_CONF0_REG(priv->id), 0, UART_ERR_WR_MASK_M);