mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
Add beginning of m9s12x GPIO support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3317 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -326,8 +326,6 @@ void up_irqinitialize(void)
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lpc17_dumpnvic("initial", LPC17_IRQ_NIRQS);
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* Initialize FIQs */
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#ifdef CONFIG_ARCH_FIQ
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@@ -344,6 +342,7 @@ void up_irqinitialize(void)
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/* And finally, enable interrupts */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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setbasepri(NVIC_SYSH_PRIORITY_MAX);
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irqrestore(0);
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#endif
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@@ -43,5 +43,13 @@ CMN_CSRCS = up_allocateheap.c up_blocktask.c up_copystate.c up_createstack.c \
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up_udelay.c up_unblocktask.c up_usestack.c
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CHIP_ASRCS = m9s12_start.S m9s12_lowputc.S m9s12_saveusercontext.S
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CHIP_CSRCS = m9s12_assert.c m9s12_serial.c m9s12_initialstate.c m9s12_irq.c \
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m9s12_timerisr.c
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CHIP_CSRCS = m9s12_assert.c m9s12_gpio.c m9s12_initialstate.c m9s12_irq.c \
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m9s12_serial.c m9s12_timerisr.c
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ifeq ($(CONFIG_GPIO_IRQ),y)
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CHIP_CSRCS += m9s12_gpioint.c
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endif
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ifeq ($(CONFIG_DEBUG_GPIO),y)
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CHIP_CSRCS += m9s12_gpiodbg.c
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endif
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Executable
+84
@@ -0,0 +1,84 @@
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/****************************************************************************
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* arch/arm/src/m9s12/m9s12_dumpgpio.c
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* arch/arm/src/chip/m9s12_dumpgpio.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "m9s12_internal.h"
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#ifdef CONFIG_DEBUG_GPIO
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Function: hcs12_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the base address of the provided pinset.
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*
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************************************************************************************/
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int hcs12_dumpgpio(uint16_t pinset, const char *msg)
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{
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#warning "Not implemented"
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return -ENOSYS;
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}
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#endif /* CONFIG_DEBUG_GPIO */
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Executable
+438
@@ -0,0 +1,438 @@
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/****************************************************************************
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* arch/arm/src/m9s12/m9s12_gpio.c
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* arch/arm/src/chip/m9s12_gpio.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include <errno.h>
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#include "up_arch.h"
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#include "m9s12_internal.h"
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#include "m9s12_pim.h"
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#include "m9s12_mebi.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* GPIO management macros:
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*
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* The GPIO configuration is represented by a 16-bit value encoded as follows:
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*
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* xxII OUUR DMGG GPPP
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* || |||| ||| `-Pin number
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* || |||| || `- Port number
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* || |||| | `- PIM Ports
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* || |||| `- Direction
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* || |||`- Reduced drive
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* || ||`- Polarity
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* || |`- Pull up (or down)
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* || `- Wired OR open drain
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* |`- Interrupt or rising/falling (polarity)
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* `- Interrupt
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*
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* NOTE: MEBI ports E and K can have special configurations as controlled by
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* the PEAR and MODE registers. Those special configurations are not managed
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* by the logic below; that logic is only intended to support general GPIO
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* pin usage.
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*/
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/* PIM ports (T,S,G,H,J,L) */
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#define HCS12_PIM_NPORTS 6
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/* MEBI ports (A,B,E,K) */
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#define HCS12_MEBI_NPORTS 4
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/* Which ports have which registers? */
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#define HCS12_PORT_T (1 << 0)
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#define HCS12_PORT_S (1 << 1)
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#define HCS12_PORT_G (1 << 2)
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#define HCS12_PORT_H (1 << 3)
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#define HCS12_PORT_J (1 << 4)
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#define HCS12_PORT_L (1 << 5)
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#define HCS12_PORT_ALL 0x3f
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#define HCS12_IO_PORTS HCS12_PORT_ALL
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#define HCS12_INPUT_PORTS HCS12_PORT_ALL
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#define HCS12_DDR_PORTS HCS12_PORT_ALL
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#define HCS12_RDR_PORTS HCS12_PORT_ALL
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#define HCS12_PER_PORTS HCS12_PORT_ALL
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#define HCS12_PS_PORTS HCS12_PORT_ALL
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#define HCS12_WOM_PORTS (HCS12_PORT_S|HCS12_PORT_L)
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#define HCS12_IE_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J)
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#define HCS12_IF_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J)
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/* Decoding help macros */
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#define HCS12_PIN(cfg) (((cfg) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT)
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#define HCS12_PORTNDX(cfg) (((cfg) >> GPIO_PORT_SHIFT) & 7)
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#define HCS12_PIMPORT(cfg) (((cfg) & GPIO_PORT_PIM) != 0)
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#define HCS12_MEBIPORT(cfg) (((cfg) & GPIO_PORT_PIM) == 0)
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#define HCS12_PULL(cfg) (((cfg) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT)
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# define HCS12_PULL_NONE 0
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# define HCS12_PULL_POLARITY 1
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# define HCS12_PULL_ENABLE 2
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# define HCS12_PULL_UP 2
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# define HCS12_PULL_DOWN 3
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#define HCS12_INTERRUPT(cfg) (((cfg) & GPIO_INT_MASK) >> GPIO_INT_SHIFT)
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# define HCS12_INT_NONE 0
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# define HCS12_INT_POLARITY 1
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# define HCS12_INT_ENABLE 2
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# define HCS12_INT_FALLING 2
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# define HCS12_INT_RISING 3
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct mebi_portaddr_s
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{
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uint16_t data; /* Data register */
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uint16_t ddr; /* Direction register */
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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static const struct mebi_portaddr_s mebi_portaddr[HCS12_MEBI_NPORTS] =
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{
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{HCS12_MEBI_PORTA, HCS12_MEBI_DDRA}, /* Port A */
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{HCS12_MEBI_PORTB, HCS12_MEBI_DDRB}, /* Port B */
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{HCS12_MEBI_PORTE, HCS12_MEBI_DDRE}, /* Port E */
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{HCS12_MEBI_PORTK, HCS12_MEBI_DDRK} /* Port K */
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};
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static uint8_t mebi_bits[HCS12_MEBI_NPORTS] =
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{
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(1 << 0), (1 << 1), (1 << 4), (1 << 7)
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Misc. Low-Level, Inline Helper Functions
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****************************************************************************/
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static inline void gpio_writebit(uint16_t regaddr, uint8_t pin, bool set)
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{
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uint8_t regval = getreg8(regaddr);
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if (set)
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{
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regval |= (1 << pin);
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}
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else
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{
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regval &= ~(1 << pin);
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}
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putreg8(regval, regaddr);
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}
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static inline bool gpio_readbit(uint16_t regaddr, uint8_t pin)
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{
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uint8_t regval = getreg8(regaddr);
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return ((regval & (1 << pin)) != 0);
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}
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static inline void pim_direction(uint8_t portndx, uint8_t pin, bool output)
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{
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gpio_writebit(HCS12_PIM_PORT_DDR(portndx), pin, output);
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}
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static inline void mebi_direction(uint8_t portndx, uint8_t pin, bool output)
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{
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gpio_writebit(mebi_portaddr[portndx].ddr, pin, output);
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}
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static inline void pim_opendrain(uint8_t portndx, uint8_t pin, bool opendrain)
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{
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DEBUGASSERT(!opendrain || (HCS12_WOM_PORTS & (1 << pin)) != 0);
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gpio_writebit(HCS12_PIM_PORT_WOM(portndx), pin, opendrain);
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}
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static inline void pim_pullpin(uint8_t portndx, uint8_t pin, uint8_t pull)
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{
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bool enable = false;
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bool polarity = false;
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if ((pull & HCS12_PULL_ENABLE) != 0)
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{
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enable = true;
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if ((pull & HCS12_PULL_POLARITY) != 0)
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{
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polarity = true;
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}
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}
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gpio_writebit(HCS12_PIM_PORT_PER(portndx), pin, enable);
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gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, polarity);
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}
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static inline void mebi_pullport(uint8_t portndx, uint8_t pull)
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{
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uint8_t regval = getreg8(HCS12_MEBI_PUCR);
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if (pull == HCS12_PULL_UP)
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{
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regval |= mebi_bits[portndx];
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}
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else
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{
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regval &= ~mebi_bits[portndx];
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}
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putreg8(regval, HCS12_MEBI_PUCR);
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}
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static inline void pim_rdpin(uint8_t portndx, uint8_t pin, bool rdenable)
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{
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gpio_writebit(HCS12_PIM_PORT_RDR(portndx), pin, rdenable);
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}
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static inline void mebi_rdport(uint8_t portndx, bool rdenable)
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{
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uint8_t regval = getreg8(HCS12_MEBI_RDRIV);
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if (rdenable)
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{
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regval |= mebi_bits[portndx];
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}
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else
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{
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regval &= ~mebi_bits[portndx];
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}
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putreg8(regval, HCS12_MEBI_RDRIV);
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}
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static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type)
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{
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if (type != HCS12_INT_NONE)
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{
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DEBUGASSERT((HCS12_IE_PORTS & (1 << pin)) != 0);
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gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false);
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gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, ((type & GPIO_INT_POLARITY) != 0));
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}
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else if ((HCS12_IE_PORTS & (1 << pin)) != 0)
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{
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gpio_writebit(HCS12_PIM_PORT_IE(portndx), pin, false);
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}
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}
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/****************************************************************************
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* Name: pim_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin)
|
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{
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/* Sanity checking -- Check if the pin will be enabled as an interrupt
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* (later)
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*/
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DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
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#ifdef CONFIG_DEBUG
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if ((cfgset) & GPIO_INT_ENABLE) != 0)
|
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{
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/* Yes.. then it must not be tagged as an output */
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ASSERT(((cfgset) & GPIO_DIRECTION) != GPIO_OUTPUT);
|
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|
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/* If the pull-driver is also enabled, it must be enabled with a
|
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* compatible priority.
|
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*/
|
||||
|
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if ((cfgset) & GPIO_PULL_ENABLE) != 0)
|
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{
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if ((cfgset) & GPIO_INT_POLARITY) != 0)
|
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{
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ASSERT(((cfgset) & GPIO_PULL_POLARITY) != 0);
|
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}
|
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else
|
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{
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ASSERT(((cfgset) & GPIO_PULL_POLARITY) = 0);
|
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}
|
||||
}
|
||||
}
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#endif
|
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pim_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT));
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pim_opendrain(portndx, pin, (((cfgset) & GPIO_OPENDRAN) != 0));
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pim_pullpin(portndx, pin, HCS12_PULL(cfgset));
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pim_rdpin(portndx, pin, (((cfgset) & GPIO_REDUCED) != 0));
|
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pim_interrupt(portndx, pin, HCS12_INTERRUPT(cfgset));
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}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mebi_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void mebi_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin)
|
||||
{
|
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DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
|
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mebi_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT));
|
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mebi_pullport(portndx, HCS12_PULL(cfgset));
|
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mebi_rdport(portndx, (((cfgset) & GPIO_REDUCED) != 0));
|
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}
|
||||
|
||||
/****************************************************************************
|
||||
* Read/Write Helpers
|
||||
****************************************************************************/
|
||||
|
||||
static inline void pim_gpiowrite(uint8_t portndx, uint8_t pin, bool value)
|
||||
{
|
||||
uint16_t regaddr = HCS12_PIM_PORT_IO(portndx)
|
||||
DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
|
||||
gpio_writebit(regaddr, pin, value);
|
||||
}
|
||||
|
||||
static inline void mebi_gpiowrite(uint8_t portndx, uint8_t pin, bool value)
|
||||
{
|
||||
uint16_t regaddr;
|
||||
DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
|
||||
regaddr = mebi_portaddr[portndx].data;
|
||||
gpio_writebit(regaddr, pin, value);
|
||||
}
|
||||
|
||||
static inline bool pim_gpioread(uint8_t portndx, uint8_t pin)
|
||||
{
|
||||
uint16_t regaddr = HCS12_PIM_PORT_INPUT(portndx)
|
||||
DEBUGASSERT(portndx < HCS12_PIM_NPORTS);
|
||||
return gpio_readbit(regaddr, pin);
|
||||
}
|
||||
|
||||
static inline bool mebi_gpioread(uint8_t portndx, uint8_t pin)
|
||||
{
|
||||
uint16_t regaddr;
|
||||
DEBUGASSERT(portndx < HCS12_MEBI_NPORTS);
|
||||
regaddr = mebi_portaddr[portndx].data;
|
||||
return gpio_readbit(regaddr, pin);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int hcs12_configgpio(uint16_t cfgset)
|
||||
{
|
||||
uint8_t portndx = HCS12_PORTNDX(cfgset);
|
||||
uint8_t pin = HCS12_PIN(cfgset);
|
||||
|
||||
if (HCS12_PIMPORT(cfgset))
|
||||
{
|
||||
pim_configgpio(cfgset, portndx, pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
mebi_configgpio(cfgset, portndx, pin);
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hcs12_gpiowrite(uint16_t pinset, bool value)
|
||||
{
|
||||
uint8_t portndx = HCS12_PORTNDX(pinset);
|
||||
uint8_t pin = HCS12_PIN(pinset);
|
||||
|
||||
DEBUGASSERT((pinset & GPIO_DIRECTION) == GPIO_OUTPUT);
|
||||
if (HCS12_PIMPORT(pinset))
|
||||
{
|
||||
pim_gpiowrite(portndx, pin, value);
|
||||
}
|
||||
else
|
||||
{
|
||||
mebi_gpiowrite(portndx, pin, value);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool hcs12_gpioread(uint16_t pinset)
|
||||
{
|
||||
uint8_t portndx = HCS12_PORTNDX(pinset);
|
||||
uint8_t pin = HCS12_PIN(pinset);
|
||||
|
||||
if (HCS12_PIMPORT(pinset))
|
||||
{
|
||||
return pim_gpioread(portndx, pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
return mebi_gpioread(portndx, pin);
|
||||
}
|
||||
}
|
||||
Executable
+108
@@ -0,0 +1,108 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/m9s12/m9s12_gpioirq.c
|
||||
* arch/arm/src/chip/m9s12_gpioirq.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "m9s12_internal.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_gpioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for
|
||||
* GPIO pins.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hcs12_gpioirqinitialize(void)
|
||||
{
|
||||
#warning "Not implemented"
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hcs12_gpioirqenable(int irq)
|
||||
{
|
||||
#warning "Not implemented"
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hcs12_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hcs12_gpioirqdisable(int irq)
|
||||
{
|
||||
#warning "Not implemented"
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_IRQ */
|
||||
|
||||
@@ -55,7 +55,132 @@
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* GPIO management macros:
|
||||
*
|
||||
* The GPIO configuration is represented by a 16-bit value encoded as follows:
|
||||
*
|
||||
* xxII OUUR DMGG GPPP
|
||||
* || |||| ||| `-Pin number
|
||||
* || |||| || `- Port number
|
||||
* || |||| | `- PIM Ports
|
||||
* || |||| `- Direction
|
||||
* || |||`- Reduced drive
|
||||
* || ||`- Polarity
|
||||
* || |`- Pull up (or down)
|
||||
* || `- Wired OR open drain
|
||||
* |`- Interrupt or rising/falling (polarity)
|
||||
* `- Interrupt
|
||||
*
|
||||
* NOTE: MEBI ports E and K can have special configurations as controlled by
|
||||
* the PEAR and MODE registers. Those special configurations are not managed
|
||||
* by the logic below; that logic is only intended to support general GPIO
|
||||
* pin usage.
|
||||
*/
|
||||
|
||||
/* Interrupts:
|
||||
*
|
||||
* xxII xxxx xxxx xxxx
|
||||
*
|
||||
* For PIM ports G, H, and J. NOTE: If pull up/down is also selected, then
|
||||
* it must be consistent with the selected interrupt edge (because both are
|
||||
* controlled by the same polarity register):
|
||||
*
|
||||
* Rising edge <-> Pull down
|
||||
* Falling Edge <-> Pull up
|
||||
*
|
||||
* Selecting input also selects direction == input (it is unless to specify
|
||||
* GPIO_INPUT and an error if GPIO_OUTPUT is also specified)
|
||||
*/
|
||||
|
||||
#define GPIO_INT_SHIFT (12)
|
||||
#define GPIO_INT_MASK (3 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_INT_POLARITY (1 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_INT_ENABLE (2 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_INT_FALLING (2 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_INT_RISING (3 << GPIO_PULLUP_SHIFT)
|
||||
|
||||
/* Wired OR open-drain:
|
||||
*
|
||||
* xxxx Oxxx xxxx xxxx
|
||||
*
|
||||
* Only PIM ports S and L
|
||||
*/
|
||||
|
||||
#define GPIO_OPENDRAN (1 << 11)
|
||||
|
||||
/* Pull up (or down):
|
||||
*
|
||||
* xxxx xUUx xxxx xxxx
|
||||
*
|
||||
* For PIM ports (T,S,G,H,J,L), selection is per-pin
|
||||
* For MEBI ports (A,B,E,K), selection is per-port, polarity is ignored
|
||||
*/
|
||||
|
||||
#define GPIO_PULLUP_SHIFT (9)
|
||||
#define GPIO_PULLUP_MASK (3 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_PULL_POLARITY (1 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_PULL_ENABLE (2 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_PULLUP (2 << GPIO_PULLUP_SHIFT)
|
||||
# define GPIO_PULLDOWN (3 << GPIO_PULLUP_SHIFT)
|
||||
|
||||
/* Reduced drive:
|
||||
*
|
||||
* xxxx xxxR xxxx xxxx
|
||||
*
|
||||
* For PIM ports (T,S,G,H,J,L), selection is per-pin
|
||||
* For MEBI ports (A,B,E,K), selection is per-port
|
||||
*/
|
||||
|
||||
#define GPIO_REDUCED (1 << 8)
|
||||
|
||||
/* Data direction (All ports -- A,B,E,K,T,S,G,H,J,L)
|
||||
*
|
||||
* xxxx xxxx Dxxx xxxx
|
||||
*
|
||||
*/
|
||||
|
||||
#define GPIO_DIRECTION (1 << 7)
|
||||
# define GPIO_INPUT (0)
|
||||
# define GPIO_OUTPUT GPIO_DIRECTION
|
||||
|
||||
/* Port selection
|
||||
*
|
||||
* xxxx xxxx xGGG Gxxx
|
||||
*
|
||||
* Ports A, B, E, and K reside in the MEBI block
|
||||
* Ports T,S,G,H,J, and L reside in the PIM block.
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT 3
|
||||
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_A (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_B (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_E (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_K (3 << GPIO_PORT_SHIFT)
|
||||
|
||||
# define GPIO_PORT_PIM (8 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_T (8 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_S (9 << GPIO_PORT_SHIFT
|
||||
# define GPIO_PORT_G (10 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_H (11 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_J (12 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT_L (13 << GPIO_PORT_SHIFT)
|
||||
|
||||
/* Pin numbers
|
||||
*
|
||||
* xxxx xxxx xxxx xPPP
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (0)
|
||||
#define GPIO_PIN_MASK (7 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_3 (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_4 (4 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_5 (5 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_6 (6 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PIN_7 (7 << GPIO_PORT_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
@@ -79,6 +204,92 @@ extern "C" {
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_gpioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
EXTERN void hcs12_gpioirqinitialize(void);
|
||||
#else
|
||||
# define hcs12_gpioirqinitialize()
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN int hcs12_configgpio(uint16_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void hcs12_gpiowrite(uint16_t pinset, bool value);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN bool hcs12_gpioread(uint16_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
EXTERN void hcs12_gpioirqenable(int irq);
|
||||
#else
|
||||
# define hcs12_gpioirqenable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: hcs12_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
EXTERN void hcs12_gpioirqdisable(int irq);
|
||||
#else
|
||||
# define hcs12_gpioirqdisable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: hcs12_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the base address of the provided pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
EXTERN int hcs12_dumpgpio(uint16_t pinset, const char *msg);
|
||||
#else
|
||||
# define hcs12_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: hcs12_ethinitialize
|
||||
*
|
||||
|
||||
@@ -83,4 +83,18 @@ void up_irqinitialize(void)
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
current_regs = NULL;
|
||||
|
||||
/* Initialize logic to support a second level of interrupt decoding for
|
||||
* GPIO pins.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc17_gpioirqinitialize();
|
||||
#endif
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
irqrestore(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -98,6 +98,7 @@
|
||||
#define HCS12_PIM_PORT_RDR(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_RDR_OFFSET)
|
||||
#define HCS12_PIM_PORT_PER(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PER_OFFSET)
|
||||
#define HCS12_PIM_PORT_PS(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_PS_OFFSET)
|
||||
#define HCS12_PIM_PORT_WOM(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_WOM_OFFSET)
|
||||
#define HCS12_PIM_PORT_IE(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IE_OFFSET)
|
||||
#define HCS12_PIM_PORT_IF(n) (HCS12_PIM_PORT_BASE(n) + HCS12_PIM_IF_OFFSET)
|
||||
|
||||
|
||||
Reference in New Issue
Block a user