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Move all SAMA5 EHCI interrupt handling to the worker thread
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@@ -386,14 +386,14 @@ config SAMA5_EHCI_NQHS
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default 4
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default 4
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---help---
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---help---
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Configurable number of Queue Head (QH) structures. The default is
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Configurable number of Queue Head (QH) structures. The default is
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one per Root hub port plus one for EP0.
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one per Root hub port plus one for EP0 (4).
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config SAMA5_EHCI_NQTDS
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config SAMA5_EHCI_NQTDS
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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int "Number of Queue Element Transfer Descriptor (qTDs)"
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default 4
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default 6
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---help---
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---help---
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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Configurable number of Queue Element Transfer Descriptor (qTDs).
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The default is one per root hub plus three from EP0.
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The default is one per root hub plus three from EP0 (6).
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config SAMA5_EHCI_BUFSIZE
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config SAMA5_EHCI_BUFSIZE
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int "Size of one request/descriptor buffer"
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int "Size of one request/descriptor buffer"
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+407
-23
File diff suppressed because it is too large
Load Diff
@@ -1166,7 +1166,7 @@ Configurations
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volume when it is removed. But those callbacks are not used in
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volume when it is removed. But those callbacks are not used in
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this configuration.
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this configuration.
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10) Support the USB full-speed OHCI host driver can be enabled by change
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10) Support the USB full-speed OHCI host driver can be enabled by changing
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the NuttX configuration file as follows:
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the NuttX configuration file as follows:
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System Type -> ATSAMA5 Peripheral Support
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System Type -> ATSAMA5 Peripheral Support
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@@ -1193,6 +1193,28 @@ Configurations
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multiple of the 48MHz needed for OHCI. The delay loop calibration
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multiple of the 48MHz needed for OHCI. The delay loop calibration
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values that are used will be off slightly because of this.
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values that are used will be off slightly because of this.
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10) Support the USB high-speed EHCI host driver can be enabled by changing
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the NuttX configuration file as follows:
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System Type -> ATSAMA5 Peripheral Support
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CONFIG_SAMA5_UHPHS=y : USB Host High Speed
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System Type -> USB High Speed Host driver options
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CONFIG_SAMA5_EHCI=y : High-speed EHCI support
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: Defaults for values probably OK
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Device Drivers
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CONFIG_USBHOST=y : Enable USB host support
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Device Drivers -> USB Host Driver Support
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CONFIG_USBHOST_ISOC_DISABLE=y : Isochronous endpoints not used
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CONFIG_USBHOST_MSC=y : Enable the mass storage class driver
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Library Routines
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CONFIG_SCHED_WORKQUEUE : Worker thread support is required
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Application Configuration -> NSH Library
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CONFIG_NSH_ARCHINIT=y : NSH board-initialization
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STATUS:
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STATUS:
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2013-7-19: This configuration (as do the others) run at 396MHz.
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2013-7-19: This configuration (as do the others) run at 396MHz.
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The SAMA5D3 can run at 536MHz. I still need to figure out the
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The SAMA5D3 can run at 536MHz. I still need to figure out the
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@@ -1255,6 +1277,10 @@ Configurations
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d) OHCI will support 3 downstream points, but I currently have only
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d) OHCI will support 3 downstream points, but I currently have only
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one enabled.
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one enabled.
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2013-8-20: Added description to add EHCI to the configuration. At
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present, however, EHCI is still a work in progress and not ready for
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prime time.
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ostest:
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ostest:
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This configuration directory, performs a simple OS test using
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This configuration directory, performs a simple OS test using
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examples/ostest.
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examples/ostest.
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@@ -282,11 +282,11 @@
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#define EHCI_INT_USBINT (1 << 0) /* Bit 0: USB Interrupt */
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#define EHCI_INT_USBINT (1 << 0) /* Bit 0: USB Interrupt */
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#define EHCI_INT_USBERRINT (1 << 1) /* Bit 1: USB Error Interrupt */
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#define EHCI_INT_USBERRINT (1 << 1) /* Bit 1: USB Error Interrupt */
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#define EHCI_INT_PCHG (1 << 2) /* Bit 2: Port Change Detect */
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#define EHCI_INT_PORTSC (1 << 2) /* Bit 2: Port Change Detect */
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#define EHCI_INT_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */
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#define EHCI_INT_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */
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#define EHCI_INT_SYSERROR (1 << 4) /* Bit 4: Host System Error */
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#define EHCI_INT_SYSERROR (1 << 4) /* Bit 4: Host System Error */
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#define EHCI_INT_AAINT (1 << 5) /* Bit 5: Interrupt on Async Advance */
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#define EHCI_INT_AAINT (1 << 5) /* Bit 5: Interrupt on Async Advance */
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#define ECHI_INT_ALLINTS (0x3f) /* Bits 0-5: All interrupts */
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/* Bits 6-11: Reserved */
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/* Bits 6-11: Reserved */
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#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */
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#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */
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#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */
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#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */
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@@ -352,6 +352,9 @@
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#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */
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#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */
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/* Bits 23-31: Reserved */
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/* Bits 23-31: Reserved */
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#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \
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EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME)
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/* Data Structures **************************************************************************/
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/* Data Structures **************************************************************************/
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/* Paragraph 3 */
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/* Paragraph 3 */
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