mirror of
https://github.com/apache/nuttx.git
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boards/arm/stm32/stm32f769i-disco: Add support for external SDRAM
This commit is contained in:
Gustavo Henrique Nihei
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
f5039d0b23
commit
b06722cd7f
+315
-280
File diff suppressed because it is too large
Load Diff
@@ -68,16 +68,16 @@
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#define STM32_FMC_NADDRCONFIGS 22
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#define STM32_FMC_NDATACONFIGS 16
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#define STM32_SDRAM_CLKEN FMC_SDRAM_MODE_CMD_CLK_ENABLE | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_PALL FMC_SDRAM_MODE_CMD_PALL | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_REFRESH FMC_SDRAM_MODE_CMD_AUTO_REFRESH | FMC_SDRAM_CMD_BANK_1 |\
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(7 << FMC_SDRAM_AUTO_REFRESH_SHIFT)
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#define STM32_SDRAM_MODEREG FMC_SDRAM_MODE_CMD_LOAD_MODE | FMC_SDRAM_CMD_BANK_1 |\
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FMC_SDRAM_MODEREG_BURST_LENGTH_1 | \
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FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
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FMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
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FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
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#define STM32_SDRAM_CLKEN FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_CLK_ENABLE
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#define STM32_SDRAM_PALL FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL
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#define STM32_SDRAM_REFRESH FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_AUTO_REFRESH |\
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FMC_SDCMR_NRFS(8)
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#define STM32_SDRAM_MODEREG FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_LOAD_MODE |\
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FMC_SDCMR_MRD_BURST_LENGTH_1 | \
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |\
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FMC_SDCMR_MRD_CAS_LATENCY_3 |\
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |\
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE
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/****************************************************************************
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* Public Data
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@@ -87,8 +87,9 @@
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static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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{
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GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4 , GPIO_FMC_A5,
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GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11,
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GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4,
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GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9,
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GPIO_FMC_A10, GPIO_FMC_A11,
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GPIO_FMC_SDCKE0_1, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0,
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GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
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@@ -97,9 +98,10 @@ static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
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{
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GPIO_FMC_D0, GPIO_FMC_D1 , GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4 , GPIO_FMC_D5,
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GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11,
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GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15
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GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
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GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
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GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14,
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GPIO_FMC_D15
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};
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/****************************************************************************
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@@ -145,19 +147,20 @@ static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
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static void stm32_sdramcommand(uint32_t command)
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{
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uint32_t regval;
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volatile uint32_t timeout = 0xFFFF;
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volatile uint32_t timeout = 0xffff;
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regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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putreg32(command, STM32_FMC_SDCMR);
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timeout = 0xFFFF;
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regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
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timeout = 0xffff;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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}
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@@ -181,7 +184,7 @@ void stm32_enablefmc(void)
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/* Enable AHB clocking to the FMC */
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regval = getreg32( STM32_RCC_AHB3ENR);
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regval = getreg32(STM32_RCC_AHB3ENR);
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regval |= RCC_AHB3ENR_FMCEN;
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putreg32(regval, STM32_RCC_AHB3ENR);
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@@ -192,29 +195,29 @@ void stm32_enablefmc(void)
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* All timings from the datasheet for Speedgrade -6A (=6ns)
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*/
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putreg32(FMC_SDRAM_CR_RPIPE_0 |
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FMC_SDRAM_CR_BURST_READ |
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FMC_SDRAM_CR_SDCLK_2X |
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FMC_SDRAM_CR_CASLAT_3 |
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FMC_SDRAM_CR_BANKS_4 |
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FMC_SDRAM_CR_WIDTH_16 |
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FMC_SDRAM_CR_ROWBITS_12 |
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FMC_SDRAM_CR_COLBITS_8,
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putreg32(FMC_SDCR_RPIPE_0 |
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FMC_SDCR_BURST_READ |
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FMC_SDCR_SDCLK_2X |
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FMC_SDCR_CASLAT_3 |
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FMC_SDCR_BANKS_4 |
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FMC_SDCR_WIDTH_16 |
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FMC_SDCR_ROWBITS_12 |
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FMC_SDCR_COLBITS_8,
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STM32_FMC_SDCR1);
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putreg32((1 << FMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 18ns */
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(1 << FMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 18ns */
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(1 << FMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */
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(6 << FMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 64ns */
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(4 << FMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 46ns */
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(7 << FMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 74ns */
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(1 << FMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */
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putreg32(FMC_SDTR_TRCD(2) | /* tRCD min = 18ns */
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FMC_SDTR_TRP(2) | /* tRP min = 18ns */
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FMC_SDTR_TWR(2) | /* tWR = 2CLK */
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FMC_SDTR_TRC(7) | /* tRC min = 64ns */
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FMC_SDTR_TRAS(5) | /* tRAS min = 46ns */
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FMC_SDTR_TXSR(8) | /* tXSR min = 74ns */
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FMC_SDTR_TMRD(2), /* tMRD = 2CLK */
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STM32_FMC_SDTR1);
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/* SDRAM Initialization sequence */
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stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
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for (count = 0; count < 10000; count++) ; /* Delay */
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for (count = 0; count < 10000; count++) ; /* Delay */
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stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
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stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
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stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
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@@ -63,4 +63,8 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y)
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CSRCS += stm32_sporadic.c
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endif
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ifeq ($(CONFIG_STM32F7_FMC),y)
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CSRCS += stm32_extmem.c
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endif
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include $(TOPDIR)/boards/Board.mk
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@@ -86,7 +86,7 @@ void stm32_boardinitialize(void)
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#ifdef CONFIG_SPORADIC_INSTRUMENTATION
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/* This configuration has been used for evaluating the NuttX sporadic scheduler.
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* The following caqll initializes the sporadic scheduler monitor.
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* The following call initializes the sporadic scheduler monitor.
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*/
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arch_sporadic_initialize();
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@@ -97,6 +97,10 @@ void stm32_boardinitialize(void)
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board_autoled_initialize();
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#endif
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#ifdef CONFIG_STM32F7_FMC
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stm32_sdram_initialize();
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#endif
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}
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/****************************************************************************
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@@ -0,0 +1,322 @@
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/****************************************************************************
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* boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "arm_arch.h"
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#include "stm32_fmc.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "stm32f769i-disco.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_STM32F7_FMC
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# warning "FMC is not enabled"
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#endif
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#if STM32F7_NGPIO < 8
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# error "Required GPIO ports not enabled"
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#endif
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#define STM32_FMC_NADDRCONFIGS 25
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#define STM32_FMC_NDATACONFIGS 32
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#define STM32_SDRAM_CLKEN FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_CLK_ENABLE
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#define STM32_SDRAM_PALL FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL
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#define STM32_SDRAM_REFRESH FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_AUTO_REFRESH |\
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FMC_SDCMR_NRFS(8)
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#define STM32_SDRAM_MODEREG FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_LOAD_MODE |\
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FMC_SDCMR_MRD_BURST_LENGTH_1 | \
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |\
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FMC_SDCMR_MRD_CAS_LATENCY_3 |\
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |\
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* GPIO configurations common to most external memories */
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static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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{
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GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4,
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GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9,
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GPIO_FMC_A10, GPIO_FMC_A11, GPIO_FMC_A12,
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GPIO_FMC_NBL0, GPIO_FMC_NBL1, GPIO_FMC_NBL2, GPIO_FMC_NBL3, GPIO_FMC_BA0,
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GPIO_FMC_BA1, GPIO_FMC_SDNWE_3, GPIO_FMC_SDNCAS, GPIO_FMC_SDNRAS,
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GPIO_FMC_SDNE0_3, GPIO_FMC_SDCKE0_3, GPIO_FMC_SDCLK
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};
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static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
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{
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GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
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GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
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GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14,
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GPIO_FMC_D15, GPIO_FMC_D16, GPIO_FMC_D17, GPIO_FMC_D18, GPIO_FMC_D19,
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GPIO_FMC_D20, GPIO_FMC_D21, GPIO_FMC_D22, GPIO_FMC_D23, GPIO_FMC_D24,
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GPIO_FMC_D25, GPIO_FMC_D26, GPIO_FMC_D27, GPIO_FMC_D28, GPIO_FMC_D29,
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GPIO_FMC_D30, GPIO_FMC_D31
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_fmc_sdram_wait
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*
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* Description:
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* Wait for the SDRAM controller to be ready.
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*
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****************************************************************************/
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static void stm32_fmc_sdram_wait(void)
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{
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int timeout = 0xffff;
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while (timeout > 0)
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{
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if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
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{
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break;
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}
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timeout--;
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}
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DEBUGASSERT(timeout > 0);
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}
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/****************************************************************************
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* Name: stm32_fmc_enable
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*
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* Description:
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* Enable clocking to the FMC.
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*
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****************************************************************************/
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static void stm32_fmc_enable(void)
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{
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modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
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}
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/****************************************************************************
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* Name: stm32_fmc_sdram_set_refresh_rate
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*
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* Description:
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* Set the SDRAM refresh rate.
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*
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****************************************************************************/
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static void stm32_fmc_sdram_set_refresh_rate(int count)
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{
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uint32_t val;
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DEBUGASSERT(count <= 0x1fff && count >= 0x29);
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stm32_fmc_sdram_wait();
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val = getreg32(STM32_FMC_SDRTR);
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val &= ~(0x1fff << 1); /* preserve non-count bits */
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val |= (count << 1);
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putreg32(val, STM32_FMC_SDRTR);
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}
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/****************************************************************************
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* Name: stm32_fmc_sdram_set_timing
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*
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* Description:
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* Set the SDRAM timing parameters.
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*
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****************************************************************************/
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static void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
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{
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uint32_t val;
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uint32_t sdtr;
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DEBUGASSERT((bank == 1) || (bank == 2));
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DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
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sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
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val = getreg32(sdtr);
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val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
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val |= timing;
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putreg32(val, sdtr);
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}
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/****************************************************************************
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* Name: stm32_fmc_sdram_set_control
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*
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* Description:
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* Set the SDRAM control parameters.
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*
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****************************************************************************/
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static void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
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{
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uint32_t val;
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uint32_t sdcr;
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DEBUGASSERT((bank == 1) || (bank == 2));
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DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
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sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
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val = getreg32(sdcr);
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val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
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val |= ctrl;
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putreg32(val, sdcr);
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}
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/****************************************************************************
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* Name: stm32_fmc_sdram_command
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*
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* Description:
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* Send a command to the SDRAM.
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*
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****************************************************************************/
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static void stm32_fmc_sdram_command(uint32_t cmd)
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{
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uint32_t val;
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DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
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/* Wait for the controller to be ready */
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stm32_fmc_sdram_wait();
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val = getreg32(STM32_FMC_SDCMR);
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val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */
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val |= cmd;
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putreg32(val, STM32_FMC_SDCMR);
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}
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/****************************************************************************
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* Name: stm32_extmemgpios
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*
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||||
* Description:
|
||||
* Initialize GPIOs for external memory usage.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure GPIOs */
|
||||
|
||||
for (i = 0; i < ngpios; i++)
|
||||
{
|
||||
stm32_configgpio(gpios[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_sdram_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_bringup to initialize external SDRAM access.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_sdram_initialize(void)
|
||||
{
|
||||
uint32_t val;
|
||||
volatile int count;
|
||||
|
||||
/* Enable GPIOs as FMC / memory pins */
|
||||
|
||||
stm32_extmemgpios(g_addressconfig, STM32_FMC_NADDRCONFIGS);
|
||||
stm32_extmemgpios(g_dataconfig, STM32_FMC_NDATACONFIGS);
|
||||
|
||||
/* Enable AHB clocking to the FMC */
|
||||
|
||||
stm32_fmc_enable();
|
||||
|
||||
/* Configure and enable the SDRAM bank1
|
||||
*
|
||||
* FMC clock = 216MHz/2 = 108MHz
|
||||
* 108MHz = 9,26 ns
|
||||
* All timings from the datasheet for Speedgrade -6A (=6ns)
|
||||
*/
|
||||
|
||||
val = FMC_SDCR_RPIPE_0 | /* rpipe = 0 hclk */
|
||||
FMC_SDCR_BURST_READ | /* enable burst read */
|
||||
FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */
|
||||
FMC_SDCR_CASLAT_3 | /* cas latency = 3 cycles */
|
||||
FMC_SDCR_BANKS_4 | /* 4 internal banks */
|
||||
FMC_SDCR_WIDTH_32 | /* width = 32 bits */
|
||||
FMC_SDCR_ROWBITS_12 | /* numrows = 12 bits */
|
||||
FMC_SDCR_COLBITS_8; /* numcols = 8 bits */
|
||||
stm32_fmc_sdram_set_control(1, val);
|
||||
|
||||
val = FMC_SDTR_TRCD(2) | /* tRCD min = 18ns */
|
||||
FMC_SDTR_TRP(2) | /* tRP min = 18ns */
|
||||
FMC_SDTR_TWR(3) | /* tWR = 3CLK */
|
||||
FMC_SDTR_TRC(7) | /* tRC min = 64ns */
|
||||
FMC_SDTR_TRAS(4) | /* tRAS min = 37ns */
|
||||
FMC_SDTR_TXSR(7) | /* tXSR min = 64ns */
|
||||
FMC_SDTR_TMRD(2); /* tMRD = 2CLK */
|
||||
stm32_fmc_sdram_set_timing(1, val);
|
||||
|
||||
/* SDRAM Initialization sequence */
|
||||
|
||||
stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */
|
||||
|
||||
for (count = 0; count < 10000; count++); /* Delay */
|
||||
|
||||
stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */
|
||||
stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */
|
||||
stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */
|
||||
|
||||
/* Set refresh count
|
||||
*
|
||||
* FMC_CLK = 108MHz
|
||||
* Refresh_Rate = 64ms / 4096 rows = 15.63us
|
||||
* Counter = (FMC_CLK * Refresh_Rate) - 20
|
||||
*/
|
||||
|
||||
stm32_fmc_sdram_set_refresh_rate(1668);
|
||||
}
|
||||
@@ -74,9 +74,11 @@
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTA | GPIO_PIN0)
|
||||
|
||||
/* Sporadic scheduler instrumentation. This configuration has been used for evaluating the NuttX
|
||||
* sporadic scheduler. In this evaluation, two GPIO outputs are used. One indicating the priority
|
||||
* (high or low) of the sporadic thread and one indicating where the thread is running or not.
|
||||
/* Sporadic scheduler instrumentation.
|
||||
* This configuration has been used for evaluating the NuttX sporadic scheduler.
|
||||
* In this evaluation, two GPIO outputs are used. One indicating the priority
|
||||
* (high or low) of the sporadic thread and one indicating where the thread is
|
||||
* running or not.
|
||||
*
|
||||
* There is nothing special about the pin selections:
|
||||
*
|
||||
@@ -157,5 +159,17 @@ void weak_function stm32_spidev_initialize(void);
|
||||
void arch_sporadic_initialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_sdram_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_bringup to initialize external SDRAM access.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_FMC
|
||||
void stm32_sdram_initialize(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H */
|
||||
|
||||
Reference in New Issue
Block a user