nuttx/nuttx を master にマージしました。

2026-05-21 13:13:08 +08:00 · 2017-04-05 19:37:19 +09:00
parent 6f4b8c9e60 38eed0a847
commit b021b0194c
903 changed files with 102002 additions and 12432 deletions
@@ -6694,7 +6694,7 @@
 	* configs/stm3240g-eval/nsh: Configuration converted to use the
 	  kconfig-frontends tools (2014-2-28).
 	* configs/*/ostest:  Removed most OS test configurations (except in a few
-	  cases where there wass some good argument to retain the ostest
+	  cases where there was some good argument to retain the ostest
 	  configuration) (2014-2-28).
 	* configs/stm3240g-eval/nsh2: Configuration converted to use the
 	  kconfig-frontends tools (2014-3-1).
@@ -13475,7 +13475,7 @@
 	  those cases, the release of the pending tasks must be deferred until
 	  those conditions are met (2016-12-26).

-7.20 2017-xx-xx Gregory Nutt <gnutt@nuttx.org>
+7.20 2017-03-08 Gregory Nutt <gnutt@nuttx.org>

 	* i.MX6 SMP/NSH configuration: Enable examples/smp test (2016-12-27).
 	* SMP: There were certain conditions that we must avoid by preventing the
@@ -13526,7 +13526,7 @@
 	  From Alan Carvalho de Assis (2017-01-07).
 	* STM32F429i-DISCO: Enable keyboard input in nxwm configuration
 	  (2017-01-07).
-	* STM32F428i-DISCO:  Change NxWM cursor character from 137 (graphics
+	* STM32F429i-DISCO:  Change NxWM cursor character from 137 (graphics
 	  block) to 95 (underscore).  NxWM is configured to use a 7-bit character
 	  set so 137 is not a valid character code (2017-01-07).
 	* NX server: Correct message queue names.  Should not be at /dev, but
@@ -13568,7 +13568,7 @@
 	* STM32 Oneshot: Fix logic so that it can support multiple oneshot timers
 	  (2017-01-18).
 	* STM32L4:  Port fix for multiple oneshot timers from STM32.  Also fixes a
-	  few issues with original STM32 implementation (2017-01-xx).
+	  few issues with original STM32 implementation (2017-01-18).
 	* SAM3/4: Add support for ATSAM4S4C.  From Wolfgang Reißnegger (2017-01-18).
 	* Math library: Leverage optimized ARM functions from BSD license ARM file
 	  (2017-01-19).
@@ -13608,7 +13608,7 @@
 	* STM32: Add missing STM32_BKP_BASE.  From David Sidrane (2017-01-23).
 	* Configurations that enable OSTEST must not disable signals (2017-01-24).
 	* Add missing sched_note_*() calls to sam4cm SMP functions (2017-01-24).
-	* Fix return falue if x is NaN.  From Aleksandr Vyhovanec (2017-01-25).
+	* Fix return value if x is NaN.  From Aleksandr Vyhovanec (2017-01-25).
 	* MMCSD_SDIO: Only wait for card ejected if card detection is supported.
 	  From Alan Carvalho de Assis (2017-01-26).
 	* LPC43 pinset definitions:  Add more 1 bit to pinset to reach
@@ -13648,7 +13648,7 @@
 	  with STM32F7_; Eliminate CONFIG_SDMMC1/2_DMA altogether.  Does not
 	  appear to be used (2017-01-31).
 	* STM32F429-DISCO:  Move some board initialization logic that is not
-	  usuable because it lacks the configuration options to make it so
+	  usable because it lacks the configuration options to make it so
 	  (2017-01-31).
 	* Cancellation points:  Fix some backward logic in conditional compilation
 	  (2017-02-02).
@@ -13681,7 +13681,7 @@
 	* Added MCG settings that are defiend on the K64 SoC.  Added
 	  BOARD_MCG_C2_FCFTRIM and BOARD_MCG_C2_LOCRE0 to configure the MCG_C2
 	  register cleanup of some comments.  From David Sidrane (2017-02-07).
-	* Better granualarity and erro checking of the board's MCG settings.
+	* Better granualarity and errno checking of the board's MCG settings.
 	  Allow for complete MCG_C2 definition from the boart.h file.  Moved
 	  #ifdef out of code by setting default values.  Allow for individule bit
 	  setting in MCG_C2 for BOARD_EXTCLOCK_MCG_C2, BOARD_MCG_C2_FCFTRIM,
@@ -13695,8 +13695,6 @@
 	* setvbuf: Add support for configuration of line buffering (2017-02-08).
 	* Bamboo-200E: Add netnsh configuration.  From Alan Carvalho de Assis
 	  (2017-02-08).
-	* Remove comment about being based on a Newlib implementation.  That is
-	  not true.  This is an original work (2017-02-08).
 	* USBMSC: Always set LUN readonly flag.  From Wolfgang Reißnegger
 	  (2017-02-08).
 	* drivers/lcd:  ssd1306_configspi() must have global scope (2017-02-09).
@@ -13706,7 +13704,7 @@
 	  enable/disable buffering (2017-02-09).
 	* C Library:  Clean-up buffer selections in Kconfig (2017-02-09).
 	* sem_open():  Fix a compiler error introduced with the setvbuf() changes
-	  (2017-02-xx).
+	  (2017-02-09).
 	* MMC/SD SDIO:  Some drivers need to start DMA before sending CMD24 and
 	  some AFTER.  From Alan Carvalho de Assis (2017-02-09).
 	* Kinetis SDHC driver fixes.  From Marc Rechté (2017-02-09).
@@ -13735,7 +13733,7 @@
 	  which not have Verified MCG configurations.

 	  From David Sidrane (2017-02-09).
-	* Kinetis chip Adding K66 and inlcuding MCG versioning.  This includes
+	* Kinetis chip Adding K66 and including MCG versioning.  This includes
 	  arch/arm/include/kinetis/kinetis_mcg.h to bring in the MCG versioning
 	  and defines the KINETIS_K66 family for the added SoCs:

@@ -13749,14 +13747,6 @@
 	     MK66FX1M0VLQ18  180 MHz 144 LQFP    1.25 MB  1 MB   4 KB  256 KB 100

 	  From David Sidrane (2017-02-09).
-	* Kinetis: MCG defines are based on the MCG feature configuration.   We
-	  define the bits as a common set of names. This means that an index may
-	  be added to a name i.e. LOCK is LOCK0 as that is the superset name.
-	  From David Sidrane (2017-02-09).
-	* Fixes ill defined BOARD_FR_DIV with BOARD_FRDIV from MCG.  Original
-	  BOARD_FR_DIV was never used - that is a good thing because the value was
-	  defined shifted and the code also shifited it.  From David Sidrane
-	  (2017-02-09).
 	* STM32: Fixes the bkp reference counter issue.  From David Sidrane
 	  (2017-02-09).
 	* STM32F7: Fixes the bkp reference counter issue.  From David Sidrane
@@ -13764,7 +13754,7 @@
 	* C Library: Add setbuf() which is a trivial wrapper around setvbuf()
 	  (2017-02-09).
 	* tools/mkconfig.c: Add logic to keep all of the buffering options in sync
-	  (2017-02-xx).
+	  (2017-02-10).
 	* VFS rename: Fix issues with rename to subdirectories and some softlink
 	  issues (2017-02-11).
 	* Add logic to VFS rename:  If target of rename exists and is a directory,
@@ -13777,7 +13767,7 @@
 	  pseudo file system, (2) Fix path naming calculation when the path is the
 	  root directory of a mounted file system, and (3) dont't do the rename if
 	  the source and destination of the rename are the same (2017-02-12).
-	* Add basic fstat() support (2017-02-x12x).
+	* Add basic fstat() support (2017-02-12).
 	* Add fstat support to binfs (2017-02-12).
 	* fstat:  Add fstat() support to romfs (2017-02-12).
 	* fstat:  Add fstat() support to unionfs (2017-02-12).
@@ -13821,8 +13811,8 @@
 	  define secondary access via AIPS1 to these peripherals.  From David
 	  Sidrane (2017-02-14).
 	* Kinetis:  Add support for K66.  From David Sidrane (2017-02-14).
-	* procfs:  stat() left several fields in uninitialized state (2017-02-xx).
-	* hostfs: Add support for fstat() (2017-02-xx).
+	* procfs:  stat() left several fields in uninitialized state (2017-02-14).
+	* hostfs: Add support for fstat() (2017-02-14).
 	* procfs: Add support for fstat() (2017-02-14).
 	* smartfs: Add support for fstat() (2017-02-14).
 	* Kinetis Freedom K66F:  Add Ethernet support.  From David Sidrane
@@ -13839,7 +13829,7 @@
 	* Kinetis PWM:  Add FTM3 to PWM.  From David Sidrane (2017-02-15).
 	* Kinetis:Freedom-K66F uses ENET_1588_CLKIN as RMII clock.   From David
 	  Sidrane (2017-02-15).
-	* Fix for SAMv7 SPI: DLYBS value wass calculated, but never written to any
+	* Fix for SAMv7 SPI: DLYBS value was calculated, but never written to any
 	  registers. This led to incorrect timings on the bus.  From Michael
 	  Spahlinger (2017-02-16).
 	* C library:  Add swab() (2017-02-16).
@@ -13864,7 +13854,7 @@
 	  raiden00 (2017-02-19).
 	* STM32L4 COMP: Port from Motorola MDK (2017-02-19).
 	* Add twr-k64f120m config and fix some ENET related problems.  From Marc
-	  Rechté (2017-02-xx).
+	  Rechté (2017-02-19).
 	* STM32 F7: stm32_allocateheap: allow use DTCM memory for heap.  STM32F7
 	  has up to 128KiB of DTCM memory that is currently left unused.  This
 	  change adds DTCM to main heap if CONFIG_STM32F7_DTCMEXCLUDE is not
@@ -13915,7 +13905,7 @@

 	  The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
 	  CONFIG_ARCH_CHIP_MK20DXxxxVLH7 All K64 and K66 have been verified PMC
-	  configurations.  From David Sidrane (2017-02-xx).
+	  configurations.  From David Sidrane (2017-02-22).
 	* Kinetis: kinetis_clockconfig uses the correct ACKISO. ACKISO is located
 	  in the PMC_REGSC on the majority of the Kinetis SoCs. With the exception
 	  of the MK40DXxxxZVLQ10 where ACKISO is located in LLWU_CS (2017-02-22).
@@ -13933,7 +13923,7 @@
 	* drivers/spi/Kconfig:  There is too much SPI in the configuration menu;
 	  SPI Driver Support menu is empty.  From Maciej Wójcik (2017-02-23).
 	* Kinetis:  SIM add paramiterized SIM_CLKDIVx_xxFRAC|DIV macros. The makes
-	  for cleaner board definitions.  From David Sidrane (2017-02-xx).
+	  for cleaner board definitions.  From David Sidrane (2017-02-23).
 	* kinetis_enet.c add #define for number of loops for auto negotiation to
 	  complete.  From Marc Rechté (2017-02-23).
 	* STM32F4 Discovery: Fix issues with QEncoder support.  From Alan Carvalho
@@ -13944,7 +13934,7 @@
 	  leave_critical_section() must be called in order to manage spinlocks
 	  correctly (2017-02-23).
 	* Fix QEncoder driver, based on STM32L4 driver.  From Alan Carvalho de
-	  Assis (2017-02-xx).
+	  Assis (2017-02-23).
 	* STM32 QEncoder.  Enable clocking to the timer on QE setup; disable clock
 	  on QE teardown (2017-02-23).
 	* Kinetis:  Extend clockconfig to support SOPT2_PLLFLLSEL and
@@ -14007,7 +13997,7 @@
 	  facilitate bring up both UARTs and LPUARTs as devices and a console.
 	  Support ordering and merging of serial devices names.  From David
 	  Sidrane (2017-02-27).
-	* Adapt more drivers to utilize the IRQ argument feature (20167-02-28).
+	* Adapt more drivers to utilize the IRQ argument feature (2107-02-28).
 	* irq_attach() and type xcpt_t.  irq_attach now accepts a argument that
 	  will be provided to the interrupt handler when the interrupt ocurrs.
 	  This affects many files by replace ad hoc parameter passing logic with a
@@ -14023,7 +14013,7 @@
 	  oldhandler is useless after the changes to the interrupt argument.  Also
 	  access an argument for the PHY interrupt.  phy_notify.c driver changed
 	  to exploit new interrupt argument passing (2017-03-02).
-	* STM32/F7/L4: EXOT PVD function no longer returns the xcpt_t oldhandler.
+	* STM32/F7/L4: EXTI PVD function no longer returns the xcpt_t oldhandler.
 	  There value is useless and dangerous after the recent changes to
 	  interrupt argument passing (2017-03-02).
 	* STM3 L4: EXTI COMP function no longer returns the xcpt_t oldhandler.
@@ -14090,6 +14080,16 @@
 	  (2017-03-05).
 	* SAMA5D4-EK:  Eliminate warning.  Correct type of return value
 	  (2017-03-05).
-	* STM32F103 Minimum: Eliminate warning stm32_usbdev.o give twice in same
-	  rule (2017-03-).
+	* STM32F103 Minimum: Eliminate warning stm32_usbdev.o givne twice in same
+	  rule (2017-03-05).
+	* STM32 OTGHS host:  stm32_in_transfer() fails and returns NAK if a
+	  short transfer is received.  This causes problems from class drivers
+	  like CDC/ACM where short packets are expected.  In those protocols,
+	  any transfer may be terminated by sending short or NUL packet.  From
+	  Janne Rosberg.  Adapt Janne Rosberg's patch to STM32 OTGHS host to
+	  OTGFS host, and to similar USB host implementations for STM32 L4 and
+	  F7 (2017-03-07).
+	* usbhost_cdcacm: fix tx outbuffer overflow and remove now invalid
+	  assert.  From Janne Rosberg (2017-03-07).

+7.21 2017-xx-xx Gregory Nutt <gnutt@nuttx.org>
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: December 26, 2016</p>
+      <p>Last Updated: March 8, 2017</p>
    </td>
  </tr>
 </table>
@@ -360,7 +360,7 @@
  <td><br></td>
  <td>
    <p>
-      <li>Loadable kernel modules.</li>
+      <li>Loadable kernel modules; lightweight, embedded shared libraries.</li>
    </p>
  </td>
 </tr>
@@ -1339,11 +1339,11 @@
 <h2>Released Versions</h2>
 <p>
  In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
-  The current release is NuttX 7.19.
-  NuttX 7.19 is the 119<sup>th</sup> release of NuttX.
-  It was released on December 26, 2016, and is available for download from the
+  The current release is NuttX 7.20.
+  NuttX 7.20 is the 120<sup>th</sup> release of NuttX.
+  It was released on March 8, 2016, and is available for download from the
  <a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
-  Note that the release consists of two tarballs:  <code>nuttx-7.19.tar.gz</code> and <code>apps-7.19.tar.gz</code>.
+  Note that the release consists of two tarballs:  <code>nuttx-7.20.tar.gz</code> and <code>apps-7.20.tar.gz</code>.
  Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
 </p>

@@ -1352,7 +1352,7 @@
 <ul>
  <li><b>nuttx</b>.
    <ul><p>
-      Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
+      Release notes for NuttX 7.20 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
      Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
      The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
      The ChangeLog for the current release is at the bottom of that file.
@@ -1360,7 +1360,7 @@
  </li></ul>
  <li><b>apps</b>.
    <ul><p>
-      Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
+      Release notes for NuttX 7.20 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
      Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
      The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
      The ChangeLog for the current release is at the bottom of that file.
@@ -1418,7 +1418,7 @@
      <li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
      <li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
      <li><a href="#armcortexm3">ARM Cortex-M3</a> (35)</li>
-      <li><a href="#armcortexm4">ARM Cortex-M4</a> (32)</li>
+      <li><a href="#armcortexm4">ARM Cortex-M4</a> (34)</li>
      <li><a href="#armcortexm7">ARM Cortex-M7</a> (7)</li>
    </ul>
  <li>Atmel AVR
@@ -1517,20 +1517,7 @@
  </li>
  <li>Expressif
    <ul>
-      <li><a href="#esp32">ESP32</a> <small>(Dual Xtensa LX6)</small</li>
-    </ul>
-  </li>
-  <li>Freescale
-    <ul>
-      <li><a href="#m68hcs12">M68HCS12</a></li>
-      <li><a href="#freescaleimx1">Freescale i.MX1</a> <small>(ARM920-T)</small></li>
-      <li><a href="#freescaleimx6">Freescale i.MX6</a> <small>(ARM Cortex-A9)</small></li>
-      <li><a href="#freescalekl25z">FreeScale KL25Z</a> <small>(ARM Cortex-M0+)</small></li>
-      <li><a href="#freescalekl26z">FreeScale KL26Z</a> <small>(ARM Cortex-M0+)</small></li>
-      <li><a href="#kinetisk20">FreeScale Kinetis K20</a> <small>(ARM Cortex-M4)</small></li>
-      <li><a href="#kinetisk40">FreeScale Kinetis K40</a> <small>(ARM Cortex-M4)</small></li>
-      <li><a href="#kinetisk60">FreeScale Kinetis K60</a> <small>(ARM Cortex-M4)</small></li>
-      <li><a href="#kinetisk64">FreeScale Kinetis K64</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#esp32">ESP32</a> <small>(Dual Xtensa LX6)</small></li>
    </ul>
  </li>
  <li>Host PC based simulations
@@ -1556,14 +1543,32 @@
      <li><a href="#moxart">Moxa NP51x0</a> <small>(ARMv4)</small></li>
    </ul>
  </li>
-  </td>
-  <td bgcolor="#e4e4e4" valign="top" width="33%">
  <li>nuvoTon
    <ul>
      <li><a href="#nuvotonnu120">nuvoTon NUC120</a> <small>(ARM Cortex-M0)</small></li>
    </ul>
  </li>
-  <li>NXP
+  <li>NXP/Freescale
+    <ul>
+      <li><a href="#m68hcs12">M68HCS12</a></li>
+    </ul>
+    <ul>
+      <li><a href="#freescaleimx1">Freescale i.MX1</a> <small>(ARM920-T)</small></li>
+      <li><a href="#freescaleimx6">Freescale i.MX6</a> <small>(ARM Cortex-A9)</small></li>
+    </ul>
+  </li>
+  </td>
+  <td bgcolor="#e4e4e4" valign="top" width="33%">
+  <li>NXP/Freescale (Continued)
+    <ul>
+      <li><a href="#freescalekl25z">FreeScale KL25Z</a> <small>(ARM Cortex-M0+)</small></li>
+      <li><a href="#freescalekl26z">FreeScale KL26Z</a> <small>(ARM Cortex-M0+)</small></li>
+      <li><a href="#kinetisk20">FreeScale Kinetis K20</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#kinetisk40">FreeScale Kinetis K40</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#kinetisk60">FreeScale Kinetis K60</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#kinetisk64">FreeScale Kinetis K64</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#kinetisk66">FreeScale Kinetis K66</a> <small>(ARM Cortex-M4)</small></li>
+    </ul>
    <ul>
      <li><a href="#nxplpc11xx">NXP LPC11xx</a> <small>(Cortex-M0)</small></li>
      <li><a href="#nxplpc214x">NXP LPC214x</a> <small>(ARM7TDMI)</small></li>
@@ -1602,13 +1607,14 @@
      <li><a href="#stm32f207x">STMicro STM32F207x</a> <small>(STM32 F2 family, ARM Cortex-M3)</small></li>
      <li><a href="#stm32302x">STMicro STM32F302x</a> <small>(STM32 F3 family, ARM Cortex-M4)</small></li>
      <li><a href="#stm32303x">STMicro STM32F303x</a> <small>(STM32 F3 family, ARM Cortex-M4)</small></li>
+      <li><a href="#stm32f372x">STMicro STM32 F372/F373</a> <small>(ARM Cortex-M4)</small></li>
+      <li><a href="#stm32f401x">STMicro STM32F401x</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
    </ul>
  </li>
  </td>
  <td bgcolor="#e4e4e4" valign="top" width="33%">
+  <li>STMicroelectronics (Continued)
    <ul>
-      <li><a href="#stm32f372x">STMicro STM32 F372/F373</a> <small>(ARM Cortex-M4)</small></li>
-      <li><a href="#stm32f401x">STMicro STM32F401x</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
      <li><a href="#stm32f407x">STMicro STM32F407x</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
      <li><a href="#stm32f427x">STMicro STM32 F427/F437</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
      <li><a href="#stm32f429x">STMicro STM32 F429</a> <small>(STM32 F4 family, ARM Cortex-M4)</small></li>
@@ -3530,7 +3536,7 @@ nsh>
  <td>
    <p>
      <a name="kinetisk60"><b>FreeScale Kinetis K60</b>.</a>
-      This port uses the Freescale Kinetis TWR-K60N512 tower system.
+      This port uses the <b>Freescale Kinetis TWR-K60N512</b> tower system.
      Refer to the <a href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-K60N512-KIT">Freescale web site</a> for further information about this board.
      The TWR-K60N51 includes with the FreeScale Tower System which provides (among other things) a DBP UART connection.
    </p>
@@ -3550,16 +3556,30 @@ nsh>
    </p>
  </td>
 </tr>
+<tr>
+  <td><br></td>
+  <td><hr></td>
+</tr>
 <tr>
  <td><br></td>
  <td>
    <p>
      <a name="kinetisk64"><b>FreeScale Kinetis K64</b>.</a>
-      Support for the Kinetis K64 family and specifically for the NXP/Freescale Freedom K64F board was added in NuttX 7.17.
+      Support for the Kinetis K64 family and specifically for the <b>NXP/Freescale Freedom K64F</b> board was added in NuttX 7.17.
      Initial release includes two NSH configurations with support for on-board LEDs, buttons, and Ethernet with the on-board KSZ8081 PHY.
      SDHC supported has been integrated, but not verified.
      Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/freedom-k64f/README.txt" target="_blank">README</a> file for further information.
    </p>
+    <p>
+      <b>MK64FN1M0VMD12</b>.
+      Architecture support for the _MK64FN1M0VMD12 was contributed by Maciej Skrzypek in NuttX-7.20.
+    </p>
+    <p>
+      <b>Freescale Kinetis TWR-K64F120M</b>.
+      Support for the Freescale Kinetis TWR-K64F120M was contributed in NuttX-7.20 by Maciej Skrzypek.  Refer to the <a href="http://www.nxp.com/products/sensors/accelerometers/3-axis-accelerometers/kinetis-k64-mcu-tower-system-module:TWR-K64F120M">Freescale web site</a> for further information about this board.
+      The board may be complemented by <a href="http://www.nxp.com/pages/serial-usb-ethernet-can-rs232-485-tower-system-module:TWR-SER">TWR-SER</a> which includes (among other things), an RS232 and Ethernet connections.
+      Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/twr-k64f120m/README.txt" target="_blank">README</a> file for further information.
+    </p>
  </td>
 </tr>
 <tr>
@@ -3591,6 +3611,36 @@ nsh>
  <td><br></td>
  <td><hr></td>
 </tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <a name="kinetisk66"><b>FreeScale Kinetis K66</b>.</a>
+      Support for the Kinetis K64 family and specifically for the <b>NXP/Freescale Freedom K66F</b> board was contributed by David Sidrane in NuttX 7.20.
+      Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/freedom-k66f/README.txt" target="_blank">README</a> file for further information.
+    </p>
+  </td>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>Driver Status</b>.
+    </p>
+    <ul>
+      <li>
+        Most K6x drivers are compatible with the K66.
+      </li>
+      <li>
+        <b>NuttX-7.20</b>.  David Sidrane also contributed support for a serial driver on the K66's LPUART.
+      </li>
+    </ul>
+  </td>
+</tr>
+</tr>
+<tr>
+  <td><br></td>
+  <td><hr></td>
+</tr>
 <tr>
  <td><br></td>
  <td>
@@ -3978,6 +4028,16 @@ nsh>
      <li>Oneshot timer driver.</li>
      <li>Quadrature encode contributed by Sebastien Lorquet.</li>
    </ul>
+    <p>
+      <b>NuttX-7.20</b>.
+      Additional drivers were added:
+    </p>
+    <ul>
+      <li>Serial Audio Interface (SAI).</li>
+      <li>Power Managmement.</li>
+      <li>LPTIM.</li>
+      <li>Comparator (COMP).</li>
+    </ul>
  </td>
 </tr>

@@ -7037,7 +7037,7 @@ interface of the same name.
 <p>
 <pre>
    #include &lt;pthread.h&gt;
-#ifdef CONFIG_MUTEX_TYPES
+#ifdef CONFIG_PTHREAD_MUTEX_TYPES
    int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type);
 #endif
 </pre>
@@ -7072,7 +7072,7 @@ returned to indicate the error:
 <p>
 <pre>
    #include &lt;pthread.h&gt;
-#ifdef CONFIG_MUTEX_TYPES
+#ifdef CONFIG_PTHREAD_MUTEX_TYPES
    int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type);
 #endif
 </pre>
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
-      <p>Last Updated: February 19, 2017</p>
+      <p>Last Updated: March 23, 2017</p>
    </td>
  </tr>
 </table>
@@ -68,6 +68,8 @@ nuttx/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/c5471evm/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- cc3200-launchpad/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cc3200-launchpad/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- clicker2-stm32/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/clicker2-stm32/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- cloudctrl/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cloudctrl/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- demo9s12ne64/
@@ -297,6 +299,8 @@ nuttx/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/us7032evb1/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- viewtool-stm32f107/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/viewtool-stm32f107/README.txt" target="_blank"><b><i>README.txt</i></b></a>
+ |   |- xmc4500-relax/
+ |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xmc4500-relax/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- xtrs/
 |   |   `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/xtrs/README.txt" target="_blank"><b><i>README.txt</i></b></a>
 |   |- z16f2800100zcog/
@@ -118,6 +118,12 @@ ifeq ($(CONFIG_WIRELESS),y)
 NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
 endif

+# Add C++ library
+
+ifeq ($(CONFIG_HAVE_CXX),y)
+NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
+endif
+
 # Export all libraries

 EXPORTLIBS = $(NUTTXLIBS)
@@ -732,6 +732,38 @@ config DEBUG_NET_INFO

 endif # DEBUG_NET

+config DEBUG_WIRELESS
+	bool "Wireless Debug Features"
+	default n
+	depends on WIRELESS || DRIVERS_WIRELESS
+	---help---
+		Enable DEBUG_WIRELESS debug features.
+
+if DEBUG_WIRELESS
+
+config DEBUG_WIRELESS_ERROR
+	bool "Wireless Error Output"
+	default n
+	depends on DEBUG_ERROR
+	---help---
+		Enable wireless error output to SYSLOG.
+
+config DEBUG_WIRELESS_WARN
+	bool "Wireless Warnings Output"
+	default n
+	depends on DEBUG_WARN
+	---help---
+		Enable wireless warning output to SYSLOG.
+
+config DEBUG_WIRELESS_INFO
+	bool "Wireless Informational Output"
+	default n
+	depends on DEBUG_INFO
+	---help---
+		Enable wireless informational output to SYSLOG.
+
+endif # DEBUG_WIRELESS
+
 config DEBUG_SCHED
 	bool "Scheduler Debug Features"
 	default n
@@ -113,6 +113,12 @@ ifeq ($(CONFIG_WIRELESS),y)
 NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
 endif

+# Add C++ library
+
+ifeq ($(CONFIG_HAVE_CXX),y)
+NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
+endif
+
 # Export only the user libraries

 EXPORTLIBS = $(USERLIBS)
@@ -123,6 +123,12 @@ ifeq ($(CONFIG_WIRELESS),y)
 NUTTXLIBS += lib$(DELIM)libwireless$(LIBEXT)
 endif

+# Add C++ library
+
+ifeq ($(CONFIG_HAVE_CXX),y)
+NUTTXLIBS += lib$(DELIM)libcxx$(LIBEXT)
+endif
+
 # Export only the user libraries

 EXPORTLIBS = $(USERLIBS)
@@ -197,6 +197,9 @@ Ubuntu Bash under Windows 10

    C:\Users\Username\AppData\Local\lxss\rootfs

+  However, I am unable to see my files under the rootfs/home directory
+  so this is not very useful.
+
  Install Linux Software.
  -----------------------
  Use "sudo apt-get install <package name>".  As examples, this is how
@@ -461,9 +464,9 @@ Notes about Header Files

    Certain header files, such as setjmp.h, stdarg.h, and math.h, may still
    be needed from your toolchain and your compiler may not, however, be able
-    to find these if you compile NuttX without using standard header file.
-    If that is the case, one solution is to copy those header file from
-    your toolchain into the NuttX include directory.
+    to find these if you compile NuttX without using standard header files
+    (ie., with -nostdinc).  If that is the case, one solution is to copy
+    those header file from your toolchain into the NuttX include directory.

  Duplicated Header Files.

@@ -1453,6 +1456,8 @@ nuttx/
 |   |   `- README.txt
 |   |- cc3200-launchpad/
 |   |   `- README.txt
+ |   |- clicker2-stm32
+ |   |   `- README.txt
 |   |- cloudctrl
 |   |   `- README.txt
 |   |- demo0s12ne64/
@@ -1681,6 +1686,8 @@ nuttx/
 |   |   `- README.txt
 |   |- viewtool-stm32f107/
 |   |   `- README.txt
+ |   |- xmc5400-relax/
+ |   |   `- README.txt
 |   |- xtrs/
 |   |   `- README.txt
 |   |- z16f2800100zcog/
@@ -13085,3 +13085,464 @@ detailed bugfix information):
        every other device driver.
      - examples/ostest: Add some delays to the pthread cancellation test.
        With deferred cancellation enabled, things happen more asynchronously.
+
+NuttX-7.20 Release Notes
+------------------------
+
+The 120th release of NuttX, Version 7.20, was made on March 8, 2017,
+and is available for download from the Bitbucket.org website.  Note
+that release consists of two tarballs:  nuttx-7.20.tar.gz and
+apps-7.20.tar.gz.  These are available from:
+
+    https://bitbucket.org/nuttx/nuttx/downloads
+    https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+    * Core OS:
+
+      - Kernel Modules:  Module initializer may now return a symbol table.
+      - Modules:  Extend the module interface so that we can access symbols
+        exported by the module.
+      - Shared Libraries:  In the FLAT build mode, kernel modules may be
+        used to provide minimal shared library functionality.
+      - Modules/Shared Libraries:  Add support for dependencies between
+        modules.
+      - Module Library:  Add build a configuration logic for a shared module
+        library.
+      - Shared Libraries: Implement module based shared libraries for the
+        PROTECTED mode build.
+      - Interrupt handling:  irq_attach() now includes an argument of type
+        xcpt_t that retained with the handler address.  That argument is
+        then provided to the interrupt handler when the interrupt occurs.
+        The common parameter passing replaces the ad hoc parmater passing
+        implemented in current drivers.  From Mark Schulte.
+      - Adapt many drivers to utilize the IRQ argument feature.
+      - All functions that used to return an xcpt_t old handler value, now
+        return an int error code.  The oldhandler value is no longer useful
+        with the recent changes to the interrupt argument passing.  Some of
+        the functions effected include board_button_irq(), arch_phy_irq(),
+        STM32 EXTI functions (Alarm, COMP, PVD), GPIO interrupt logic like
+        kinetis_pinirq(), stm32_gpiosetevent(), and others.
+      - IRQ subsystem:  Add support for smaller interrupt tables as
+        described at
+        http://www.nuttx.org/doku.php?id=wiki:howtos:smallvectors .  This
+        is partially the work of Mark Schulte.
+
+    * File Systems/Block and MTD Drivers
+
+      - Pseudo File System:  Add support for soft links in the top-level
+        psuedo file system.
+      - Soft links:  Add an implementation of readlink().
+      - Add fstat() support.  Implement fstat() method in binfs, romfs,
+        unionfs, tmpfs, nxffs, nfx, hostfs, procfs, and smartfs.
+      - fstat:  Add fstat() support to FAT.  From Alan Carvalho de Assis.
+
+    * Graphics/Display Drivers:
+
+      - Fonts: Add support for Tom Thumb small mono-space font. From Alan
+        Carvalho de Assis.
+      - Graphics:  Separated of font cache from graphics/nxterm.  Now in
+        libnx/nxfronts where it can be shared with other grapics
+        applications.
+
+    * Networking/Network Drivers:
+
+      - Ethernet drivers:  Add framework for serialization in the case where
+        multiple low-priority work queues are used.
+
+    * Other Common Device Drivers:
+
+      - Add capabilities() method to SDIO interface.  Remove
+        CONFIG_SDIO_WIDTH_D1_ONLY.  That should not be a global propertie,
+        but rather a capability/limitation of single slot when there may be
+        multiple slots.
+      - Removed dmasupported() method from the SDIO interface.  That is now
+        a bit in the capability set.
+      - drivers/sensors: Add driver for the ST L3GD20 3 axis gyro.  From
+        raiden00.
+
+    * Atmel SAM3/4:
+
+      - SAM3/4: Add support for ATSAM4S4C.  From Wolfgang Reißnegger.
+
+    * NXP Freescale i.MX6 Boards:
+
+      - Sabre 6quad:  Enable examples/smp test in i.MX6 SMP/NSH
+        configurations.
+
+    * NXP Freescale Kinetis:
+
+      - Kinetis:  Added support for CHIP_MK60FN1M0VLQ12 chip.  From Maciej
+        Skrzypek.
+      - Kinetis:  Add support for K64/K66 RTC lower half driver. From Neil
+        Hancock.
+      - Kinetis:  Extensive modification of MCG support based feature
+        configuration.  From David Sidrane.
+      - Kinetis:  Add support for K66 family.  From David Sidrane.
+      - Kinetis:  Created a kinetis SIM versioning scheme pulled in by
+        Kinetis chip.h.  From David Sidrane.
+      - Created a kinetis PMC versioning scheme pulled in by Kinetis
+        chip.h.  From David Sidrane.
+      - Kinetis: Extend clock configuration logic.  Refactor
+        implementation.  From David Sidrane.
+
+    * NXP Freescale Kinetis Drivers:
+
+      - Kinetis Ethernet:  Kinetis Support RMII clock source select.  This
+        defined the RMII clock source select bits and allows the selection
+        to be made via Kconfig. From David Sidrane.  Freedom-K66F uses
+        ENET_1588_CLKIN as RMII clock
+      - Kinetis Serial:  Added configurable 1|2 stop bits.
+        HAVE_SERIAL_CONSOLE -> HAVE_UART_CONSOLE to be consistent with
+        HAVE_LPUART_CONSOLE naming. From David Sidrane.
+      - Kinetis LPserial:  Add LPUART serial driver and Clock
+        configuartaion to freedom-k66f board.  From David Sidrane.
+      - Kinetis USB device:  Refactor clocking in kinetis_usbdev.  From
+        David Sidrane.
+
+    * NXP Freescale Kinetis Boards:
+
+      - Add support for NXP Freedom-k66f development board.  From David
+        Sidrane.
+      - Kinetis Freedom K66F:  Add Ethernet support.  From David Sidrane.
+      - Add twr-k64f120m config.  From Marc Rechté.
+
+    * NXP Freescale LPC43xx Boards:
+
+      - Bamboo-200E: Add netnsh configuration.  From Alan Carvalho de Assis.
+      - Add usbnsh config to Bambino 200E board.  From Alan Carvalho de
+        Assis.
+
+    * STMicro STM32:
+
+      - STM32 F7: Allow board to configure HSE clock in bypass-mode. This
+        is needed to enable HSE with Nucleo-F746ZG board.  From Jussi
+        Kivilinna.
+      - STM32 F7: stm32_allocateheap: allow use DTCM memory for heap.
+        STM32F7 has up to 128KiB of DTCM memory that is currently left
+        unused.  This change adds DTCM to main heap if
+        CONFIG_STM32F7_DTCMEXCLUDE is not enabled.  From Jussi Kivilinna.
+      - Add basic support for the STM32F334.  From Mateusz Szafoni.
+      - STM32F33XX DAC, OPAMP, COMP, ADC, HRTIM headers.   From Mateusz
+        Szafoni.
+
+    * STMicro STM32 Drivers:
+
+      - STM32 F7 SDMMC:  Add support for single bit operation on SDMMC2.
+      - STM32 L4:  Port STM32L4 SAI driver from MDK.
+      - STM32 L4:  Bring power management logic from Motrola MDK into NuttX.
+      - STM32 L4:  Bring LPTIM driver in from the Motorola MDK.
+      - STM32 L4 COMP: Port from Motorola MDK.
+
+    * STMicro STM32 Boards:
+
+      - STM32F429i Discovery: Add support for NxWM on STM32F429i-Disco
+        board. From Alan Carvalho de Assis.
+      - STM32F103 Minimum: Add support for nRF24 on STM32F103-Minimum
+        board. From Alan Carvalho de Assis.
+      - Olimex STM32 P407: Add a NSH protected build configuration; Enable
+        procfs/ in all configurations.
+      - Olimex STM32 P407: Add support for on-board microSD slot.
+      - STM32F429i Discovery: add support for the L3GD20 driver.  From
+        raiden00.
+      - STM32F103 Minimum: Add support to QEncoder on STM32F103 Minimum
+        board.   From Alan Carvalho de Assis.
+      - Olimex STM32 P407:  Add external SRAM support.
+      - Add basic support for the Nucleo F334R8 board.  From Mateusz
+        Szafoni.
+      - STM32F103 Minimum: Add SDCard support over SPI on STM32F103-Minimum
+        board.  From Alan Carvalho de Assis.
+      - STM32F103 Minimum: Add support to USB Device on STM32F103-Minimum
+        board.  From Alan Carvalho de Assis.
+
+    * C Library/Header Files:
+
+      - compiler.h: packed_struct replaced by begin_packed_struct and
+        end_packed_struct. Now support IAR style packed structures.  From
+        Aleksandr Vyhovanec.
+      - Math library: Leverage optimized ARMv8-M functions from BSD license
+        ARM file.
+      - Shared libraries:  Add a non-standard dllfnc.h function to set the
+        symbol table.
+      - C Library: Add a support for setvbuf(). This is a collaborative
+        effort.  Alan Carvalho de Assis did the initial prototype.
+      - C Library: Add setbuf() which is a trivial wrapper around setvbuf().
+      - C library:  Add swab().
+      - C library: Add strtoimax and strtoumax.
+      - C library:  Add ffs(), rindex(), an index().  Add strings.h.  Move
+        strcasecmp, strncasecmp, bzero, bcmp, and bcopy to where they
+        belong in strings.h.h, not string.h.  bzero, bcmp, and bcopy are
+        legacy functions; the contemporary counterparts should be used
+        instead.
+      - C library: Add fstatfs().
+      - Update cwchar.  Add cwctype.
+
+    * Build/Configuration System:
+
+      - Add configuration support for builds with Ubuntu under Windows 10.
+
+    * Tools:
+
+      - tools/noteinfo.c: A hack tool that I use to analyze some sched_note
+        output.  Needs a home and may be useful to others.
+      - tools/mkconfig.c: Add logic to keep all of the buffering options in
+        sync.
+
+    * NSH: apps/nshlib:
+
+      - NSH: Add support for the 'ln' command.
+      - NSH ls command: if node is a symobolic link, use readlink() to get
+        and the display the target of the symblic link.
+      - NSH: Add readlink command.
+
+    * Applications: apps/examples:
+
+      - apps/examples/nxtext: Make line spacing configurable.
+      - apps/system/zmodem/host/nuttx/compiler.h synchronized with
+        nuttx/nuttx/include/nuttx/compiler.h.  From Aleksandr Vyhovanec.
+      - apps/examples/sotest:  Add a test for shared libraries.
+      - apps/examples/ostest:  Add a test of setvbuf().
+      - apps/examples/stat:  Add a simple test for stat(), fstat(),
+        statfs(), and fstatfs().
+
+Works-In-Progress:
+
+    * IEEE802.14.5/6LowPAN.  Hooks and framework for this effort were
+      introduced in NuttX-7.15.  Work has continued on this effort on
+      forks from the main repositories, albeit with many interruptions.
+      The completion of this wireless feature will postponed until at
+      least NuttX-7.21.
+
+Bugfixes.  Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+    * Core OS:
+
+      - SMP: There were certain conditions that we must avoid by preventing
+        the release of the pending tasks while withn a critical section.
+        But this logic was incomplete; there was no logic to prevent other
+        CPUs from adding new, running tasks while on CPU is in a critical
+        section.  This commit corrects this.  This is matching logic in
+        sched_addreadytorun to avoid starting new tasks within the critical
+        section (unless the CPU is the holder of the lock).  The holder of
+        the IRQ lock must be permitted to do whatever it needs to do.
+      - SMP: Make checks for CPU lock set more robust.  There are certain
+        conditions early in initialization on during interrupt handling
+        where things need to be done a little differently.
+      - sched_cpulocked:  Avoid use of spinlock.  That has been reported to
+        cause a deadlock (2016-12-28).
+      - SMP: Fix a gap where we may try to make modifications to the task
+        lists without being in a critical sections.  That permits
+        concurrent access to the tasks lists and many subtle problems.
+        This fix just remains in the critical section throughout the
+        operation (and possible until the task is restore in the event of a
+        context switch).  Makes a big difference in stability.
+      - SMP: Fix an error in critical section logic when performing a
+        context switch from an interrupt handler.  The g_cpu_irqset bit was
+        not being set for the CPU so other CPUs did not know about the
+        critical section.
+      - SMP Signals: Fix some SMP signal delivery logic. Was not handling
+        some critical sections correctly and was missing logic to signal
+        tasks running on other CPUs.
+      - SMP:  Fix timer related issues:  Round robin and sporadic
+        scheduling were only being performed for tasks running on the CPU
+        that processes the system timer interrupt.  Similary, CPU load
+        measurements were only be processed for running on the CPU that
+        receives the sampling interrupt.
+      - sched_note: Fix spinlock instrumentation.  From Masayuki Ishikawa.
+      - In all implementations of _exit(), use enter_critical_section() vs.
+        disabling local interrupts.
+      - sigtimedwait:  When timer expires, up_unblock_task() is called.
+        This is okay in the single CPU case because interrupts are disable
+        in the timer interrupt handler.  But it is insufficient in the SMP
+        case.  enter_ and leave_critical_section() must be called in order
+        to manage spinlocks correctly.
+      - Fix a compile error: in sched_cpuload.c:Line136, the variables ts
+        and secs are not defined if CONFIG_CPULOAD_ONESHOT_ENTROPY = 0.
+        However, these variables are used regardless of
+        CONFIG_CPULOAD_ONESHOT_ENTROPY at lines~180:onwards.  From rg.
+      - CPU load: Correct computation of the nominal period to use when the
+        source is a oneshot timer.
+      - Cancellation points:  Fix some backward logic in conditional
+        compilation.
+      - Remove an unused variable when calling sigwaitinfo() and
+        sigtimedwait().  From Masayuki Ishikawa.
+
+    * File System/Block and MTD Drivers:
+
+      - procfs:  Correct to snprintf-related errors in fs_procfsproc.c.
+        Resolves issue #24.
+      - Add logic to VFS rename:  If target of rename exists and is a
+        directory, then the source file should be moved 'under' the target
+        directory. POSIX also requires that if the target is a file, then
+        that old file must be deleted.
+      - Fix open() a block device with
+        CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y. From Masayuki Ishikawa.
+      - File System: Don't build block driver proxy if PSEUDOFS_OPERATIONS
+        are disabled.
+      - sendfile():  Fix error introduced with commit
+        ff73be870e38959b0aaee5961dc47b4b58dc2d86.  Noted by Maciej Wójcik.
+
+    * Graphics/Graphic Drivers:
+
+      - NxWM configurations.  If using a 7-bit character set, then the
+        cursor character cannot be 137 (graphic block).  Use 95
+        (underscore) instead.
+      - NX server: Correct message queue names.  Should not be at /dev,
+        but rather relative to /var/mqueue.
+
+    * Common Drivers:
+
+      - MMCSD_SDIO: Only wait for card ejected if card detection is
+        supported. From Alan Carvalho de Assis.
+      - Typos withim mtd/ with Macronix MX25L.  In
+        NuttX/drivers/mtd/Make.defs letters X between M and 25 are
+        missing.  Noted by Oleg Evseev.
+      - USBMSC: Always set LUN readonly flag.  From Wolfgang Reißnegger.
+      - drivers/lcd:  ssd1306_configspi() must have global scope.
+      - MMC/SD SDIO:  Some drivers need to start DMA before sending CMD24
+        and some AFTER.  From Alan Carvalho de Assis.
+      - drivers/tone.c:  Handle configuration with multiple PWM channels.
+        This resolves issue #30: Audio Tone Generator and PWM Multiple
+        Output Channel options.
+      - drivers/tone.c:  50% duty needs to be expressed a a fixed precision
+        number.
+      - drivers/spi/Kconfig:  There is too much SPI in the configuration
+        menu; SPI Driver Support menu is empty.  From Maciej Wójcik.
+      - option to enable Memory Card debug output was hidden with SD cards
+        connected through SPI.   From Maciej Wójcik.
+      - usbhost_cdcacm: fix tx outbuffer overflow and remove now invalid
+        assert.  From Janne Rosberg.
+
+    * Networking/Network Drivers:
+
+      - Networking: Fixed some issues that prevented IPv6 from working with
+        IPv4 enabled.  From Pascal Speck.
+      - Networking: fixed a nullptr-dereference on iob_clone.  From Pascal
+        Speck.
+      - Ethernet: Need two work structures (minimum) in all Ethernet
+        drivers so that pending poll work is not lost when an interrupt
+        occurs.
+
+    * ARMv7-R:
+
+      - I found an issue inside the cp15_coherent_dcache function:  The
+        "mcr CP15_BPIALLIS(r0)" should only be used with SMP
+        configurationa. In non-SMP configuration this instruction could
+        become undefined.  From Manohara HK.
+
+    * Atmel SAM3/4 Drivers:
+
+      - SAM3/4: GPIO bit numbering typo fixes.  From Wolfgang Reißnegger.
+
+    * Atmel SAM3/4 Boards:
+
+      - Add missing sched_note_*() calls in sam4cm SMP functions.
+
+    * NXP/Freescale Kinetis:
+
+      - Kinetis: Fixed wrong MCG VDIV calculation on new NXP K60.  From
+        Maciej Skrzypek.
+      - Kinetis: Need to set HAVE_UART_DEVICE when UART4 is selected.  From
+        Maciej Skrzypek.
+      - Kinetis MCG: Wrong FRDIV set in MCG_C1.  From Maciej Skrzypek.
+
+    * NXP/Freescale Kinetis Drivers:
+
+      - Kinetis Serial: Fixed compile error when UART5 is selected.  From
+        Maciej Skrzypek.
+      - Kinetis SDHC - Enable clock after selected.  From David Sidrane.
+      - Kinetis:  Correct some SPI and I2C configuration issues.  From
+        David Sidrane.
+      - Kinetis Ethernet:  Add #define for number of loops for auto
+        negotiation to complete.  From Marc Rechté.
+      - Kinetis Werial:  Fixed up_rxint - did not disable the RX
+        interuppts. There was an OR where and AND NOT was needed.  From
+        David Sidrane.
+
+    * NXP/Freescale LPC43xx:
+
+      - LPC43 pinset definitions:  Add more 1 bit to pinset to reach
+        SFSCLK0-SFSCLK3. Remove PINCONFIG_DIGITAL.  From Alan Carvalho de
+        Assis.
+
+    * NXP/Freescale LPC43xx Drivers:
+
+      - LPC43 serial:  Correct conditional logic that selects /dev/ttySN.
+        Problem noted by Alan Carvalho de Assis.
+
+    * NXP/Freescale i.MX6:
+
+      - i.MX6: Fix clearing GPT status register.  From Masayuki Ishikawa.
+
+    * STMicro STM32:
+
+      - STM32, STM32L4 Oneshot: Fix logic so that it can support multiple
+        oneshot timers.
+      - STM32 F7: Added missing ARCH_HAVE_RESET for F7.  From David Sidrane.
+      - STM32:  Add missing STM32_BKP_BASE.  From David Sidrane.
+      - STM32 and STM32F7: Fixes the BKP reference counter issue.  From
+        David Sidrane.
+
+    * STMicro STM32 Drivers:
+
+      - Fix for SAMv7 SPI: DLYBS value was calculated, but never written to
+        any registers. This led to incorrect timings on the bus.  From
+        Michael Spahlinger.
+      - STM32 QEncoder: Fix QEncoder driver, based on STM32L4 driver.  From
+        Alan Carvalho de Assis.
+      - STM32 QEncoder:  Enable clocking to the timer on QE setup; disable
+        clock on QE teardown.
+      - STM32 Ethernet: Need two work structures so that pending poll work
+        is not lost when an interrupt occurs.  This change has also been
+        ported to all all other effected Ethernet drivers.
+      - STM32 OTGHS host:  stm32_in_transfer() fails and returns NAK if a
+        short transfer is received.  This causes problems from class
+        drivers like CDC/ACM where short packets are expected.  In those
+        protocols, any transfer may be terminated by sending short or NUL
+        packet.  From Janne Rosberg.  Adapted Janne Rosberg's patch to
+        STM32 OTGHS host to OTGFS host, and to similar USB host
+        implementations for STM32 L4 and F7.
+
+    * STMicro STM32 Boards:
+
+      - STM32F4 Discovery: Fix issues with QEncoder support.  From Alan
+        Carvalho de Assis.
+
+    * C Library/Header Files:
+
+      - Add debug assertion in libdtoa to catch attempts to use floating
+        point output formats from within an interrupt handler.  That will
+        cause assertions or crashes downstream because __dtoa will attempt
+        to allocate memory.  From Pierre-noel Bouteville.
+      - libc: Fix ARMv7-A/R memcpy assembly.
+      - Fix return value if x is NaN.  From Aleksandr Vyhovanec.
+
+    * apps/nshlib:
+
+      - NSH: Eliminate a warning when all memory inspection commands are disabled.
+
+    * apps/graphics:
+
+      - apps/graphics/traveler/tools: Fix linkage issue. The -lm should
+        come after -o binname.  From Alan Carvalho de Assis.
+
+    * apps/netutils:
+
+      - The CONFIG_NETUTILS_HTTPD_PATH constant is used by httpd_mmap.c and
+        httpd_sendfile.c but It was not present in Kconfig menu.  From
+        Maciej Wójcik.
+
+    * apps/examples:
+
+      - Configurations that enable OSTEST must not disable signals.
+      - apps/examples/ostest:  Was ignoring
+        CONFIG_EXAMPLES_OSTEST_FPUTESTDISABLE.
+      - In apps/examples/mtdpart/mtdpart_main.c where
+        CONFIG_EXAMPLES_MTDPART_NPARTITIONS defining is checked should be
+        #ifndef instead of #ifdef.  Noted by Oleg Evseev.
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated March 4, 2017)
+NuttX TODO List (Last updated March 26, 2017)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -14,12 +14,12 @@ nuttx/:
  (1)  Memory Management (mm/)
  (0)  Power Management (drivers/pm)
  (3)  Signals (sched/signal, arch/)
-  (2)  pthreads (sched/pthread)
+  (4)  pthreads (sched/pthread)
  (0)  Message Queues (sched/mqueue)
  (8)  Kernel/Protected Build
  (3)  C++ Support
  (6)  Binary loaders (binfmt/)
- (13)  Network (net/, drivers/net)
+ (14)  Network (net/, drivers/net)
  (4)  USB (drivers/usbdev, drivers/usbhost)
  (0)  Other drivers (drivers/)
 (12)  Libraries (libc/, libm/)
@@ -346,7 +346,7 @@ o Signals (sched/signal, arch/)
  Priority:    Low. Even if there are only 31 usable signals, that is still a lot.

 o pthreads (sched/pthreads)
-  ^^^^^^^^^^^^^^^^^
+  ^^^^^^^^^^^^^^^^^^^^^^^^^

  Title:       PTHREAD_PRIO_PROTECT
  Description: Extend pthread_mutexattr_setprotocol().  It should support
@@ -448,6 +448,30 @@ o pthreads (sched/pthreads)
  Status:      Not really open.  This is just the way it is.
  Priority:    Nothing additional is planned.

+  Title:       PTHREAD FILES IN WRONG LOCATTION
+  Description: There are many pthread interface functions in files located in
+               sched/pthread.  These should be moved from that location to
+               libc/pthread.  In the flat build, this really does not matter,
+               but in the protected build that location means that system calls
+               are required to access the pthread interface functions.
+  Status:      Open
+  Priority:    Medium-low. Priority may be higher if system call overheade becomes
+               an issue.
+
+  Title:       ROBUST MUTEX ATTRIBUTE NOT SUPPORTED
+  Description: In NuttX, all mutexes are 'robust' in the sense that an attmpt
+               to lock a mutex will return EOWNDERDEAD if the holder of the
+               mutex has died.  Unlocking of a mutex will fail if the caller
+               is not the holder of the mutex.
+
+               POSIX, however, requires that there be a mutex attribute called
+               robust that determines which behavior is supported.  non-robust
+               should be the default.  NuttX does not support this attribute
+               and robust behavior is the default and only supported behavior.
+  Status:      Open
+  Priority:    Low.  The non-robust behavior is dangerous and really should never
+               be used.
+
 o Message Queues (sched/mqueue)
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

@@ -507,7 +531,7 @@ o Kernel/Protected Build
               in the nuttx/ directory.  However, the user interfaces must be
               moved into a NuttX library or into apps/.  Currently
               applications calls to the NxTerm user interfaces are
-               undefined.
+               undefined in the Kernel/Protected builds.
  Status:      Open
  Priority:    Medium

@@ -1065,6 +1089,20 @@ o Network (net/, drivers/net)
  Status:      Open
  Priority:    High if you happen to be using Ethernet in this configuration.

+  Title:       REPARTITION DRIVER FUNCTIONALITY
+  Description: Every network driver performs the first level of packet decoding.
+               It examines the packet header and calls ipv4_input(), ipv6_input().
+               icmp_input(), etc. as appropriate.  This is a maintenance problem
+               because it means that any changes to the network input interfaces
+               affects all drivers.
+
+               A better, more maintainable solution would use a single net_input()
+               function that would receive all incoming packets.  This function
+               would then perform that common packet decoding logic that is
+               currently implemented in every network driver.
+  Status:      Open
+  Priority:    Low.  Really just as aesthetic maintainability issue.
+
 o USB (drivers/usbdev, drivers/usbhost)
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

@@ -1196,7 +1234,7 @@ o USB (drivers/usbdev, drivers/usbhost)
               from being usable:

              - The driver works fine when configured for reduced or bulk-
-                only protocol.
+                only protocol on the Olimex LPC1766STK.

              - Testing has not been performed with the interrupt IN channel
                enabled (ie., I have not enabled FLOW control nor do I have
@@ -1221,6 +1259,32 @@ o USB (drivers/usbdev, drivers/usbhost)
                Apparently the host driver is trashing memory on receipt
                of data.

+                UPDATE:  This behavior needs to be retested with:
+                  commit ce2845c5c3c257d081f624857949a6afd4a4668a
+                  Author: Janne Rosberg <janne.rosberg@offcode.fi>
+                  Date:   Tue Mar 7 06:58:32 2017 -0600
+
+                    usbhost_cdcacm: fix tx outbuffer overflow and remove now
+                    invalid assert
+
+                  commit 3331e9c49aaaa6dcc3aefa6a9e2c80422ffedcd3
+                  Author: Janne Rosberg <janne.rosberg@offcode.fi>
+                  Date:   Tue Mar 7 06:57:06 2017 -0600
+
+                    STM32 OTGHS host:  stm32_in_transfer() fails and returns NAK
+                    if a short transfer is received.  This causes problems from
+                    class drivers like CDC/ACM where short packets are expected.
+                    In those protocols, any transfer may be terminated by sending
+                    short or NUL packet.
+
+                  commit 0631c1aafa76dbaa41b4c37e18db98be47b60481
+                  Author: Gregory Nutt <gnutt@nuttx.org>
+                  Date:   Tue Mar 7 07:17:24 2017 -0600
+
+                    STM32 OTGFS, STM32 L4 and F7: Adapt Janne Rosberg's patch to
+                    STM32 OTGHS host to OTGFS host, and to similar implements for
+                    L4 and F7.
+
              - The SAMA5D EHCI and the LPC31 EHCI drivers both take semaphores
                in the cancel method.  The current CDC/ACM class driver calls
                the cancel() method from an interrupt handler.  This will
@@ -1234,9 +1298,12 @@ o USB (drivers/usbdev, drivers/usbhost)
               configurations if you use it.

               That all being said, I know of know no issues with the current
-               CDC/ACM driver if the interrupt IN endpoint is not used, i.e.,
-               in "reduced" mode.  The only loss of functionality is output
-               flow control.
+               CDC/ACM driver on the Olimex LPC1766STK platform if the interrupt
+               IN endpoint is not used, i.e., in "reduced" mode.  The only loss
+               of functionality is output flow control.
+
+               UPDATE: The CDC/ACM class driver may also now be functional on
+               the STM32.  That needs to be verified.

  Status:      Open
  Priority:    Medium-Low unless you really need host CDC/ACM support.
@@ -151,12 +151,20 @@ config ARCH_CHIP_LPC43XX
 	---help---
 		NPX LPC43XX architectures (ARM Cortex-M4).

+config ARCH_CHIP_MOXART
+	bool "MoxART"
+	select ARCH_ARM7TDMI
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_SERIAL_TERMIOS
+	---help---
+		MoxART family
+
 config ARCH_CHIP_NUC1XX
 	bool "Nuvoton NUC100/120"
 	select ARCH_CORTEXM0
 	select ARCH_HAVE_CMNVECTOR
 	---help---
-		NPX LPC43XX architectures (ARM Cortex-M4).
+		Nuvoton NUC100/120 architectures (ARM Cortex-M0).

 config ARCH_CHIP_SAMA5
 	bool "Atmel SAMA5"
@@ -270,13 +278,18 @@ config ARCH_CHIP_TMS570
 	---help---
 		TI TMS570 family

-config ARCH_CHIP_MOXART
-	bool "MoxART"
-	select ARCH_ARM7TDMI
-	select ARCH_HAVE_RESET
-	select ARCH_HAVE_SERIAL_TERMIOS
+config ARCH_CHIP_XMC4
+	bool "Infineon XMC4xxx"
+	select ARCH_HAVE_CMNVECTOR
+	select ARCH_CORTEXM4
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_RAMFUNCS
+	select ARCH_HAVE_I2CRESET
+	select ARM_HAVE_MPU_UNIFIED
+	select ARMV7M_CMNVECTOR
+	select ARMV7M_HAVE_STACKCHECK
 	---help---
-		MoxART family
+		Infineon XMC4xxx(ARM Cortex-M4) architectures

 endchoice

@@ -421,6 +434,7 @@ config ARCH_CHIP
 	default "lpc2378"	if ARCH_CHIP_LPC2378
 	default "lpc31xx"	if ARCH_CHIP_LPC31XX
 	default "lpc43xx"	if ARCH_CHIP_LPC43XX
+	default "moxart"	if ARCH_CHIP_MOXART
 	default "nuc1xx"	if ARCH_CHIP_NUC1XX
 	default "sama5"		if ARCH_CHIP_SAMA5
 	default "samdl"		if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
@@ -431,7 +445,7 @@ config ARCH_CHIP
 	default "stm32l4"	if ARCH_CHIP_STM32L4
 	default "str71x"	if ARCH_CHIP_STR71X
 	default "tms570"	if ARCH_CHIP_TMS570
-	default "moxart"	if ARCH_CHIP_MOXART
+	default "xmc4"		if ARCH_CHIP_XMC4

 config ARM_TOOLCHAIN_IAR
 	bool
@@ -662,6 +676,9 @@ endif
 if ARCH_CHIP_LPC43XX
 source arch/arm/src/lpc43xx/Kconfig
 endif
+if ARCH_CHIP_MOXART
+source arch/arm/src/moxart/Kconfig
+endif
 if ARCH_CHIP_NUC1XX
 source arch/arm/src/nuc1xx/Kconfig
 endif
@@ -692,8 +709,8 @@ endif
 if ARCH_CHIP_TMS570
 source arch/arm/src/tms570/Kconfig
 endif
-if ARCH_CHIP_MOXART
-source arch/arm/src/moxart/Kconfig
+if ARCH_CHIP_XMC4
+source arch/arm/src/xmc4/Kconfig
 endif

 endif # ARCH_ARM
@@ -347,6 +347,32 @@
 #  define LPC43_NADC10             (2)         /* Two 10-bit ADC controllers */
 #  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
 #  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
+#elif defined(CONFIG_ARCH_CHIP_LPC4337FET256)
+#  define LPC43_FLASH_BANKA_SIZE   (512*1024)  /* 1024Kb FLASH */
+#  define LPC43_FLASH_BANKB_SIZE   (512*1024)
+#  define LPC43_LOCSRAM_BANK0_SIZE (32*1024)   /* 72Kb Local SRAM */
+#  define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
+#  define LPC43_AHBSRAM_BANK0_SIZE (48*1024)   /* 64Kb AHB SRAM */
+#  define LPC43_AHBSRAM_BANK1_SIZE (0)
+#  define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
+#  define LPC43_EEPROM_SIZE        (16*1024)   /* 16Kb EEPROM */
+#  undef  LPC43_NLCD                           /* No LCD controller */
+#  define LPC43_ETHERNET           (1)         /* One Ethernet controller */
+#  define LPC43_USB0               (1)         /* Have USB0 (Host, Device, OTG) */
+#  define LPC43_USB1               (1)         /* Have USB1 (Host, Device) */
+#  define LPC43_USB1_ULPI          (1)         /* Have USB1 (Host, Device) with ULPI I/F */
+#  define LPC43_MCPWM              (1)         /* One PWM interface */
+#  define LPC43_QEI                (1)         /* One Quadrature Encoder interface */
+#  define LPC43_NUSARTS            (4)         /* Three USARTs + 1 UART */
+#  define LPC43_NSSP               (2)         /* Two SSP controllers */
+#  define LPC43_NTIMERS            (4)         /* Four Timers */
+#  define LPC43_NI2C               (2)         /* Two I2C controllers */
+#  define LPC43_NI2S               (2)         /* Two I2S controllers */
+#  define LPC43_NCAN               (2)         /* Two CAN controllers */
+#  define LPC43_NDAC               (1)         /* One 10-bit DAC */
+#  define LPC43_NADC10             (2)         /* Two 10-bit ADC controllers */
+#  define LPC43_NADC10_CHANNELS    (8)         /* Eight ADC channels */
+#  undef  LPC43_NADC12                         /* No 12-bit ADC controllers */
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
 #  define LPC43_FLASH_BANKA_SIZE   (0)         /* Flashless */
 #  define LPC43_FLASH_BANKB_SIZE   (0)
@@ -64,12 +64,16 @@
 * STM32L15XCX -- 48-pins
 * STM32L15XRX -- 64-pins
 * STM32L15XVX -- 100-pins
+ * STM32L15XZX -- 144-pins
 *
 * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
 * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
 * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
 *
 * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
+ *
+ * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density)
+ * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density)
 */

 #if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
@@ -320,7 +324,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
 #  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
-#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite vamily */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
                                              * and STM32L15xxx */
@@ -331,6 +335,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
 #  define STM32_NATIM                    0   /* No advanced timers */
@@ -358,17 +363,18 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
 #  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
-#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite vamily */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
                                              * and STM32L15xxx */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
-#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes, STM32L16x w/ 48/384 Kbytes. */
+#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32L16xD w/ 48/384 Kbytes. */
 #  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    1   /* FSMC */
 #  define STM32_NATIM                    0   /* No advanced timers */
@@ -395,6 +401,48 @@
 #  define STM32_NRNG                     0   /* No random number generator (RNG) */
 #  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */

+#elif defined(CONFIG_ARCH_CHIP_STM32L162VE)
+#  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
+                                              * and STM32L15xxx */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32L16xE w/ 80/512 Kbytes. */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
+#  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
+#  define STM32_NFSMC                    0   /* No FSMC */
+#  define STM32_NATIM                    0   /* No advanced timers */
+#  define STM32_NGTIM                    4   /* 16-bit general timers TIM2-4 with DMA
+                                              * 32-bit general timer TIM5 with DMA */
+#  define STM32_NGTIMNDMA                3   /* 16-bit general timers TIM9-11 without DMA */
+#  define STM32_NBTIM                    2   /* 2 basic timers: TIM6, TIM7 with DMA */
+#  define STM32_NDMA                     2   /* DMA1, 12-channels */
+#  define STM32_NSPI                     3   /* SPI1-3 */
+#  define STM32_NI2S                     2   /* I2S1-2, overlapping with SPI2-3 */
+#  define STM32_NUSART                   5   /* USART1-3, UART4-5 */
+#  define STM32_NI2C                     2   /* I2C1-2 */
+#  define STM32_NCAN                     0   /* No CAN */
+#  define STM32_NSDIO                    0   /* No SDIO */
+#  define STM32_NLCD                     1   /* LCD 4x44, 8x40*/
+#  define STM32_NUSBOTG                  1   /* USB OTG FS/HS (only USB 2.0 device) */
+#  define STM32_NGPIO                    83  /* GPIOA-G,H */
+
+#  define STM32_NADC                     1   /* ADC1, up to 40-channels (medium+ and high density). See for more information RM0038 Reference manual  */
+#  define STM32_NDAC                     1   /* DAC 1, 2 channels. See for more information RM0038 Reference manual */
+                                             /* (2) Comparators */
+#  define STM32_NCAPSENSE                23  /* Capacitive sensing channels */
+#  define STM32_NCRC                     1   /* CRC */
+#  define STM32_NETHERNET                0   /* No ethernet */
+#  define STM32_NRNG                     0   /* No random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */
+
+
 /* STM32 F100 Value Line ************************************************************/

 #elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
@@ -562,7 +610,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  define CONFIG_STM32_STM32F10XX        1   /* STM32F10xx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  define CONFIG_STM32_MEDIUMDENSITY     1   /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -1129,7 +1177,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -1668,7 +1716,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -0,0 +1,139 @@
+/************************************************************************************
+ * arch/arm/include/xmc4/chip.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_XMC4_CHIP_H
+#define __ARCH_ARM_INCLUDE_XMC4_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip */
+
+#if defined(CONFIG_ARCH_CHIP_XMC4500)
+#  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
+#  undef  XMC4_SCU_GATING                /* No clock gating registers */
+#  define XMC4_NECAT          0          /* No EtherCAT support */
+#elif defined(CONFIG_ARCH_CHIP_XMC4700)
+#  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
+#  define XMC4_SCU_GATING     1          /* Has clock gating registers */
+#  define XMC4_NECAT          0          /* No EtherCAT support */
+#elif defined(CONFIG_ARCH_CHIP_XMC4800)
+#  define XMC4_NUSIC          3          /* Three USIC modules: USCI0-2 */
+#  define XMC4_SCU_GATING     1          /* Has clock gating registers */
+#  define XMC4_NECAT          1          /* One EtherCAT module */
+#else
+#  error "Unsupported XMC4xxx chip"
+#endif
+
+/* NVIC priority levels *************************************************************/
+/* Each priority field holds a priority value.  The lower the value, the greater the
+ * priority of the corresponding interrupt.  The XMC4500 implements only bits[7:2]
+ * of this field, bits[1:0] read as zero and ignore writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN     0xfc /* All bits[7:2] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP    0x04 /* Steps between supported priority values */
+
+/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
+ * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
+ * interrupts will not have execution priority.  SVCall must have execution
+ * priority in all cases.
+ *
+ * In the normal cases, interrupts are not nest-able and all interrupts run
+ * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
+ * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
+ *
+ * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
+ * high priority interrupts are supported.  These are not "nested" in the
+ * normal sense of the word.  These high priority interrupts can interrupt
+ * normal processing but execute outside of OS (although they can "get back
+ * into the game" via a PendSV interrupt).
+ *
+ * In the normal course of things, interrupts must occasionally be disabled
+ * using the up_irq_save() inline function to prevent contention in use of
+ * resources that may be shared between interrupt level and non-interrupt
+ * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
+ * do we disable all interrupts (except SVCall), or do we only disable the
+ * "normal" interrupts.  Since the high priority interrupts cannot interact
+ * with the OS, you may want to permit the high priority interrupts even if
+ * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
+ * used to select either behavior:
+ *
+ *   ----------------------------+--------------+----------------------------
+ *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
+ *   ----------------------------+--------------+--------------+-------------
+ *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
+ *   ----------------------------+--------------+--------------+-------------
+ *                               |              |              |    SVCall
+ *                               |    SVCall    |    SVCall    |    HIGH
+ *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
+ *                               |              |    MAXNORMAL |
+ *   ----------------------------+--------------+--------------+-------------
+ */
+
+#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#else
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_XMC4_CHIP_H */
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/arm/include/xmc4/irq.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H
+#define __ARCH_ARM_INCLUDE_XMC4_IRQ_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define XMC4_IRQ_RESERVED      (0)   /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+                                     /* Vector  0: Reset stack pointer value */
+                                     /* Vector  1: Reset (not handler as an IRQ) */
+#define XMC4_IRQ_NMI           (2)   /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define XMC4_IRQ_HARDFAULT     (3)   /* Vector  3: Hard fault */
+#define XMC4_IRQ_MEMFAULT      (4)   /* Vector  4: Memory management (MPU) */
+#define XMC4_IRQ_BUSFAULT      (5)   /* Vector  5: Bus fault */
+#define XMC4_IRQ_USAGEFAULT    (6)   /* Vector  6: Usage fault */
+                                     /* Vectors 7-10: Reserved */
+#define XMC4_IRQ_SVCALL        (11)  /* Vector 11: SVC call */
+#define XMC4_IRQ_DBGMONITOR    (12)  /* Vector 12: Debug Monitor */
+                                     /* Vector 13: Reserved */
+#define XMC4_IRQ_PENDSV        (14)  /* Vector 14: Pendable system service request */
+#define XMC4_IRQ_SYSTICK       (15)  /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16).  These definitions are chip-specific */
+
+#define XMC4_IRQ_FIRST         (16)  /* Vector number of the first external interrupt */
+
+#if defined(CONFIG_ARCH_CHIP_XMC4500)
+#  include <arch/xmc4/xmc4500_irq.h>
+#else
+  /* The interrupt vectors for other parts are defined in other documents and may or
+   * may not be the same as above (the family members are all very similar)  This
+   * error just means that you have to look at the document and determine for yourself
+   * if the vectors are the same.
+   */
+
+#  error "No IRQ numbers for this XMC4xxx part"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */
+
@@ -0,0 +1,225 @@
+/*****************************************************************************
+ * arch/arm/include/xmc4/xmc4500_.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
+#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15).  These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * Acronyms:
+ *  ADC   - Analog to Digital Converter
+ *  CCU   - Capture Compare Unit
+ *  DAC   - Digital to Analog Converter
+ *  DSD   - Delta Sigmoid Demodulator
+ *  ERU   - External Request Unit
+ *  FCE   - Flexible CRC Engine
+ *  GPDMA - General Purpose DMA
+ *  LEDTS - LED and Touch Sense Control Unit
+ *  PMU   - Program Management Unit
+ *  POSIF - Position Interface
+ *  SDMMC - Multi Media Card Interface
+ *  USB   - Universal Serial Bus
+ *  USCI  - Universal Serial Interface
+ */
+
+#define XMC4_IRQ_SCU        (XMC4_IRQ_FIRST+0)   /*   0: System Control */
+#define XMC4_IRQ_ERU0_SR0   (XMC4_IRQ_FIRST+1)   /*   1: ERU0, SR0 */
+#define XMC4_IRQ_ERU0_SR1   (XMC4_IRQ_FIRST+2)   /*   2: ERU0, SR1 */
+#define XMC4_IRQ_ERU0_SR2   (XMC4_IRQ_FIRST+3)   /*   3: ERU0, SR2 */
+#define XMC4_IRQ_ERU0_SR3   (XMC4_IRQ_FIRST+4)   /*   4: ERU0, SR3 */
+#define XMC4_IRQ_ERU1_SR0   (XMC4_IRQ_FIRST+5)   /*   5: ERU1, SR0 */
+#define XMC4_IRQ_ERU1_SR1   (XMC4_IRQ_FIRST+6)   /*   6: ERU1, SR1 */
+#define XMC4_IRQ_ERU1_SR2   (XMC4_IRQ_FIRST+7)   /*   7: ERU1, SR2 */
+#define XMC4_IRQ_ERU1_SR3   (XMC4_IRQ_FIRST+8)   /*   8: ERU1, SR3 */
+#define XMC4_IRQ_RESVD009   (XMC4_IRQ_FIRST+9)   /*   9: Reserved */
+#define XMC4_IRQ_RESVD010   (XMC4_IRQ_FIRST+10)  /*  10: Reserved */
+#define XMC4_IRQ_RESVD011   (XMC4_IRQ_FIRST+11)  /*  11: Reserved */
+#define XMC4_IRQ_PMU1_SR0   (XMC4_IRQ_FIRST+12)  /*  12: PMU, SR0 */
+#define XMC4_IRQ_RESVD011   (XMC4_IRQ_FIRST+13)  /*  13: Reserved */
+#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14)  /*  14: ADC Common Block 0 */
+#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15)  /*  15: ADC Common Block 1 */
+#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16)  /*  16: ADC Common Block 2 */
+#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17)  /*  17: ADC Common Block 3 */
+#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18)  /*  18: ADC Group 0, SR0 */
+#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19)  /*  19: ADC Group 0, SR1 */
+#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20)  /*  20: ADC Group 0, SR2 */
+#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21)  /*  21: ADC Group 0, SR3 */
+#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22)  /*  22: ADC Group 1, SR0 */
+#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23)  /*  23: ADC Group 1, SR1 */
+#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24)  /*  24: ADC Group 1, SR2 */
+#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25)  /*  25: ADC Group 1, SR3 */
+#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26)  /*  26: ADC Group 2, SR0 */
+#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27)  /*  27: ADC Group 2, SR1 */
+#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28)  /*  28: ADC Group 2, SR2 */
+#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29)  /*  29: ADC Group 2, SR3 */
+#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30)  /*  30: ADC Group 3, SR0 */
+#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31)  /*  31: ADC Group 3, SR1 */
+#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32)  /*  32: ADC Group 3, SR2 */
+#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33)  /*  33: ADC Group 3, SR3 */
+#define XMC4_IRQ_DSD_SRM0   (XMC4_IRQ_FIRST+34)  /*  34: DSD Main, SRM0 */
+#define XMC4_IRQ_DSD_SRM1   (XMC4_IRQ_FIRST+35)  /*  35: DSD Main, SRM1 */
+#define XMC4_IRQ_DSD_SRM2   (XMC4_IRQ_FIRST+36)  /*  36: DSD Main, SRM2 */
+#define XMC4_IRQ_DSD_SRM3   (XMC4_IRQ_FIRST+37)  /*  37: DSD Main, SRM3 */
+#define XMC4_IRQ_DSD_SRA0   (XMC4_IRQ_FIRST+38)  /*  38: DSD Auxiliary, SRA0 */
+#define XMC4_IRQ_DSD_SRA1   (XMC4_IRQ_FIRST+39)  /*  39: DSD Auxiliary, SRA1 */
+#define XMC4_IRQ_DSD_SRA2   (XMC4_IRQ_FIRST+40)  /*  40: DSD Auxiliary, SRA2 */
+#define XMC4_IRQ_DSD_SRA3   (XMC4_IRQ_FIRST+41)  /*  41: DSD Auxiliary, SRA3 */
+#define XMC4_IRQ_DAC_SR0    (XMC4_IRQ_FIRST+42)  /*  42: DAC, SR0 */
+#define XMC4_IRQ_DAC_SR1    (XMC4_IRQ_FIRST+43)  /*  43: DAC, SR1 */
+#define XMC4_IRQ_CCU40_SR0  (XMC4_IRQ_FIRST+44)  /*  44: CCU4 Module 0, SR0 */
+#define XMC4_IRQ_CCU40_SR1  (XMC4_IRQ_FIRST+45)  /*  45: CCU4 Module 0, SR1 */
+#define XMC4_IRQ_CCU40_SR2  (XMC4_IRQ_FIRST+46)  /*  46: CCU4 Module 0, SR2 */
+#define XMC4_IRQ_CCU40_SR3  (XMC4_IRQ_FIRST+47)  /*  47: CCU4 Module 0, SR3 */
+#define XMC4_IRQ_CCU41_SR0  (XMC4_IRQ_FIRST+48)  /*  48: CCU4 Module 1, SR0 */
+#define XMC4_IRQ_CCU41_SR1  (XMC4_IRQ_FIRST+49)  /*  49: CCU4 Module 1, SR1 */
+#define XMC4_IRQ_CCU41_SR2  (XMC4_IRQ_FIRST+50)  /*  50: CCU4 Module 1, SR2 */
+#define XMC4_IRQ_CCU41_SR3  (XMC4_IRQ_FIRST+51)  /*  51: CCU4 Module 1, SR3 */
+#define XMC4_IRQ_CCU42_SR0  (XMC4_IRQ_FIRST+52)  /*  52: CCU4 Module 2, SR0 */
+#define XMC4_IRQ_CCU42_SR1  (XMC4_IRQ_FIRST+53)  /*  53: CCU4 Module 2, SR1 */
+#define XMC4_IRQ_CCU42_SR2  (XMC4_IRQ_FIRST+54)  /*  54: CCU4 Module 2, SR2 */
+#define XMC4_IRQ_CCU42_SR3  (XMC4_IRQ_FIRST+55)  /*  55: CCU4 Module 2, SR3 */
+#define XMC4_IRQ_CCU43_SR0  (XMC4_IRQ_FIRST+56)  /*  56: CCU4 Module 3, SR0 */
+#define XMC4_IRQ_CCU43_SR1  (XMC4_IRQ_FIRST+57)  /*  57: CCU4 Module 3, SR1 */
+#define XMC4_IRQ_CCU43_SR2  (XMC4_IRQ_FIRST+58)  /*  58: CCU4 Module 3, SR2 */
+#define XMC4_IRQ_CCU43_SR3  (XMC4_IRQ_FIRST+59)  /*  59: CCU4 Module 3, SR3 */
+#define XMC4_IRQ_CCU80_SR0  (XMC4_IRQ_FIRST+60)  /*  60: CCU8 Module 0, SR0 */
+#define XMC4_IRQ_CCU80_SR1  (XMC4_IRQ_FIRST+61)  /*  61: CCU8 Module 0, SR1 */
+#define XMC4_IRQ_CCU80_SR2  (XMC4_IRQ_FIRST+62)  /*  62: CCU8 Module 0, SR2 */
+#define XMC4_IRQ_CCU80_SR3  (XMC4_IRQ_FIRST+63)  /*  63: CCU8 Module 0, SR3 */
+#define XMC4_IRQ_CCU81_SR0  (XMC4_IRQ_FIRST+64)  /*  64: CCU8 Module 1, SR0 */
+#define XMC4_IRQ_CCU81_SR1  (XMC4_IRQ_FIRST+65)  /*  65: CCU8 Module 1, SR1 */
+#define XMC4_IRQ_CCU81_SR2  (XMC4_IRQ_FIRST+66)  /*  66: CCU8 Module 1, SR2 */
+#define XMC4_IRQ_CCU81_SR3  (XMC4_IRQ_FIRST+67)  /*  67: CCU8 Module 1, SR3 */
+#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68)  /*  68: POSIF Module 0, SR0 */
+#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69)  /*  69: POSIF Module 0, SR1 */
+#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70)  /*  70: POSIF Module 1, SR0 */
+#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71)  /*  71: POSIF Module 1, SR1 */
+#define XMC4_IRQ_RESVD072   (XMC4_IRQ_FIRST+72)  /*  72: Reserved */
+#define XMC4_IRQ_RESVD073   (XMC4_IRQ_FIRST+73)  /*  73: Reserved */
+#define XMC4_IRQ_RESVD074   (XMC4_IRQ_FIRST+74)  /*  74: Reserved */
+#define XMC4_IRQ_RESVD075   (XMC4_IRQ_FIRST+75)  /*  75: Reserved */
+#define XMC4_IRQ_CAN_SR0    (XMC4_IRQ_FIRST+76)  /*  76: MultiCAN, SR0 */
+#define XMC4_IRQ_CAN_SR1    (XMC4_IRQ_FIRST+77)  /*  77: MultiCAN, SR1 */
+#define XMC4_IRQ_CAN_SR2    (XMC4_IRQ_FIRST+78)  /*  78: MultiCAN, SR2 */
+#define XMC4_IRQ_CAN_SR3    (XMC4_IRQ_FIRST+79)  /*  79: MultiCAN, SR3 */
+#define XMC4_IRQ_CAN_SR4    (XMC4_IRQ_FIRST+80)  /*  80: MultiCAN, SR4 */
+#define XMC4_IRQ_CAN_SR5    (XMC4_IRQ_FIRST+81)  /*  81: MultiCAN, SR5 */
+#define XMC4_IRQ_CAN_SR6    (XMC4_IRQ_FIRST+82)  /*  82: MultiCAN, SR6 */
+#define XMC4_IRQ_CAN_SR7    (XMC4_IRQ_FIRST+83)  /*  83: MultiCAN, SR7 */
+#define XMC4_IRQ_USIC0_SR0  (XMC4_IRQ_FIRST+84)  /*  84: USIC0 Channel, SR0 */
+#define XMC4_IRQ_USIC0_SR1  (XMC4_IRQ_FIRST+85)  /*  85: USIC0 Channel, SR1 */
+#define XMC4_IRQ_USIC0_SR2  (XMC4_IRQ_FIRST+86)  /*  86: USIC0 Channel, SR2 */
+#define XMC4_IRQ_USIC0_SR3  (XMC4_IRQ_FIRST+87)  /*  87: USIC0 Channel, SR3 */
+#define XMC4_IRQ_USIC0_SR4  (XMC4_IRQ_FIRST+88)  /*  88: USIC0 Channel, SR4 */
+#define XMC4_IRQ_USIC0_SR5  (XMC4_IRQ_FIRST+89)  /*  89: USIC0 Channel, SR5 */
+#define XMC4_IRQ_USIC1_SR0  (XMC4_IRQ_FIRST+90)  /*  90: USIC1 Channel, SR0 */
+#define XMC4_IRQ_USIC1_SR1  (XMC4_IRQ_FIRST+91)  /*  91: USIC1 Channel, SR1 */
+#define XMC4_IRQ_USIC1_SR2  (XMC4_IRQ_FIRST+92)  /*  92: USIC1 Channel, SR2 */
+#define XMC4_IRQ_USIC1_SR3  (XMC4_IRQ_FIRST+93)  /*  93: USIC1 Channel, SR3 */
+#define XMC4_IRQ_USIC1_SR4  (XMC4_IRQ_FIRST+94)  /*  94: USIC1 Channel, SR4 */
+#define XMC4_IRQ_USIC1_SR5  (XMC4_IRQ_FIRST+95)  /*  95: USIC1 Channel, SR5 */
+#define XMC4_IRQ_USIC2_SR0  (XMC4_IRQ_FIRST+96)  /*  96: USIC1 Channel, SR0 */
+#define XMC4_IRQ_USIC2_SR1  (XMC4_IRQ_FIRST+97)  /*  97: USIC1 Channel, SR1 */
+#define XMC4_IRQ_USIC2_SR2  (XMC4_IRQ_FIRST+98)  /*  98: USIC1 Channel, SR2 */
+#define XMC4_IRQ_USIC2_SR3  (XMC4_IRQ_FIRST+99)  /*  99: USIC1 Channel, SR3 */
+#define XMC4_IRQ_USIC2_SR4  (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */
+#define XMC4_IRQ_USIC2_SR5  (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */
+#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */
+#define XMC4_IRQ_RESVD103   (XMC4_IRQ_FIRST+103) /* 103: Reserved */
+#define XMC4_IRQ_FCR_SR0    (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */
+#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */
+#define XMC4_IRQ_SDMMC_SR0  (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
+#define XMC4_IRQ_USB0_SR0   (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
+#define XMC4_IRQ_ETH0_SR0   (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
+#define XMC4_IRQ_ECAT0_SR0  (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */
+#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
+#define XMC4_IRQ_RESVD111   (XMC4_IRQ_FIRST+111) /* 111: Reserved */
+
+#define NR_INTERRUPTS       112                  /* 112 Non core IRQs*/
+#define NR_VECTORS          (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */
+
+/* GPIO IRQ interrupts -- To be provided */
+
+#define NR_IRQS             NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */
@@ -159,16 +159,6 @@ void up_irqinitialize(void)
      (void)getreg32(A1X_INTC_IRQ_PEND(i));   /* Reading status clears pending interrupts */
    }

-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Set the interrupt base address to zero.  We do not use the vectored
   * interrupts.
   */
@@ -323,7 +323,7 @@ exception_common:
 	.global	g_intstackbase
 	.align	8
 g_intstackalloc:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~7)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.size	g_intstackalloc, .-g_intstackalloc
 #endif
@@ -235,7 +235,7 @@ exception_common:
 	 *
 	 * Here:
 	 *   r0 = Address of the register save area
-	
+	 *
 	 * NOTE: It is a requirement that up_restorefpu() preserve the value of
 	 * r0!
 	 */
@@ -355,7 +355,7 @@ exception_common:
 	.global	g_intstackbase
 	.align	8
 g_intstackalloc:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~7)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.size	g_intstackalloc, .-g_intstackalloc
 #endif
@@ -66,22 +66,11 @@
 #  define HAVE_KERNEL_HEAP 1
 #endif

-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
 */

-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-#  ifdef __ARM_EABI__
-#    define CONFIG_STACK_ALIGNMENT 8
-#  else
-#    define CONFIG_STACK_ALIGNMENT 4
-#  endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8

 /* Stack alignment macros */

@@ -233,9 +222,9 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)

      top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;

-      /* The ARM stack must be aligned; 4 byte alignment for OABI and
-       * 8-byte alignment for EABI. If necessary top_of_stack must be
-       * rounded down to the next boundary
+      /* The ARM stack must be aligned to 8-byte alignment for EABI.
+       * If necessary top_of_stack must be rounded down to the next 
+       * boundary
       */

      top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
@@ -53,22 +53,11 @@
 * Pre-processor Macros
 ****************************************************************************/

-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
 */

-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-#  ifdef __ARM_EABI__
-#    define CONFIG_STACK_ALIGNMENT 8
-#  else
-#    define CONFIG_STACK_ALIGNMENT 4
-#  endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8

 /* Stack alignment macros */

@@ -56,22 +56,11 @@
 * Pre-processor Macros
 ****************************************************************************/

-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
 */

-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-#  ifdef __ARM_EABI__
-#    define CONFIG_STACK_ALIGNMENT 8
-#  else
-#    define CONFIG_STACK_ALIGNMENT 4
-#  endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8

 /* Stack alignment macros */

@@ -143,9 +132,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)

  top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;

-  /* The ARM stack must be aligned; 4 byte alignment for OABI and 8-byte
-   * alignment for EABI. If necessary top_of_stack must be rounded down
-   * to the next boundary
+  /* The ARM stack must be aligned to 8-byte alignment for EABI.
+   * If necessary top_of_stack must be rounded down to the next 
+   * boundary
   */

  top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
@@ -56,22 +56,11 @@
 * Pre-processor Definitions
 ****************************************************************************/

-/* ARM requires at least a 4-byte stack alignment.  For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
 */

-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol  __ARM_EABI__ is defined by GCC if EABI is being used.  If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-#  ifdef __ARM_EABI__
-#    define CONFIG_STACK_ALIGNMENT 8
-#  else
-#    define CONFIG_STACK_ALIGNMENT 4
-#  endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8

 /****************************************************************************
 * Public Functions
@@ -319,16 +319,6 @@ void up_irqinitialize(void)
      putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
    }

-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  /* Colorize the interrupt stack for debug purposes */
-
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -93,16 +93,6 @@ void up_irqinitialize(void)
   * access to the GIC.
   */

-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Initialize the Generic Interrupt Controller (GIC) for CPU0 */

  arm_gic0_initialize();  /* Initialization unique to CPU0 */
@@ -52,7 +52,7 @@

 /* If the common ARMv7-M vector handling logic is used, then it expects the
 * following definition in this file that provides the number of supported external
- * interrupts which, for this architecture, is provided in the arch/stm32f7/chip.h
+ * interrupts which, for this architecture, is provided in the arch/kinetis/chip.h
 * header file.
 */

@@ -133,8 +133,8 @@
 #define GPIO_OUTPUT            (_PIN_MODE_GPIO | _PIN_OUTPUT)
 #define GPIO_FAST              (_PIN_MODE_GPIO | _PIN_OUTPUT_FAST)
 #define GPIO_SLOW              (_PIN_MODE_GPIO | _PIN_OUTPUT_SLOW)
-#define GPIO_OPENDRAIN         (_PIN_MODE_GPIO | _PIN_OUTPUT_LOWDRIVE)
-#define GPIO_LOWDRIVE          (_PIN_MODE_GPIO | _PIN_OUTPUT_OPENDRAIN)
+#define GPIO_OPENDRAIN         (_PIN_MODE_GPIO | _PIN_OUTPUT_OPENDRAIN)
+#define GPIO_LOWDRIVE          (_PIN_MODE_GPIO | _PIN_OUTPUT_LOWDRIVE)
 #define GPIO_HIGHDRIVE         (_PIN_MODE_GPIO | _PIN_OUTPUT_HIGHDRIVE)

 #define PIN_ALT2               _PIN_MODE_ALT2
@@ -155,8 +155,8 @@
 #define PIN_ALT3_OUTPUT        (_PIN_MODE_ALT3 | _PIN_OUTPUT)
 #define PIN_ALT3_FAST          (_PIN_MODE_ALT3 | _PIN_OUTPUT_FAST)
 #define PIN_ALT3_SLOW          (_PIN_MODE_ALT3 | _PIN_OUTPUT_SLOW)
-#define PIN_ALT3_OPENDRAIN     (_PIN_MODE_ALT3 | _PIN_OUTPUT_LOWDRIVE)
-#define PIN_ALT3_LOWDRIVE      (_PIN_MODE_ALT3 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT3_OPENDRAIN     (_PIN_MODE_ALT3 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT3_LOWDRIVE      (_PIN_MODE_ALT3 | _PIN_OUTPUT_LOWDRIVE)
 #define PIN_ALT3_HIGHDRIVE     (_PIN_MODE_ALT3 | _PIN_OUTPUT_HIGHDRIVE)

 #define PIN_ALT4               _PIN_MODE_ALT4
@@ -166,8 +166,8 @@
 #define PIN_ALT4_OUTPUT        (_PIN_MODE_ALT4 | _PIN_OUTPUT)
 #define PIN_ALT4_FAST          (_PIN_MODE_ALT4 | _PIN_OUTPUT_FAST)
 #define PIN_ALT4_SLOW          (_PIN_MODE_ALT4 | _PIN_OUTPUT_SLOW)
-#define PIN_ALT4_OPENDRAIN     (_PIN_MODE_ALT4 | _PIN_OUTPUT_LOWDRIVE)
-#define PIN_ALT4_LOWDRIVE      (_PIN_MODE_ALT4 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT4_OPENDRAIN     (_PIN_MODE_ALT4 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT4_LOWDRIVE      (_PIN_MODE_ALT4 | _PIN_OUTPUT_LOWDRIVE)
 #define PIN_ALT4_HIGHDRIVE     (_PIN_MODE_ALT4 | _PIN_OUTPUT_HIGHDRIVE)

 #define PIN_ALT5               _PIN_MODE_ALT5
@@ -177,8 +177,8 @@
 #define PIN_ALT5_OUTPUT        (_PIN_MODE_ALT5 | _PIN_OUTPUT)
 #define PIN_ALT5_FAST          (_PIN_MODE_ALT5 | _PIN_OUTPUT_FAST)
 #define PIN_ALT5_SLOW          (_PIN_MODE_ALT5 | _PIN_OUTPUT_SLOW)
-#define PIN_ALT5_OPENDRAIN     (_PIN_MODE_ALT5 | _PIN_OUTPUT_LOWDRIVE)
-#define PIN_ALT5_LOWDRIVE      (_PIN_MODE_ALT5 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT5_OPENDRAIN     (_PIN_MODE_ALT5 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT5_LOWDRIVE      (_PIN_MODE_ALT5 | _PIN_OUTPUT_LOWDRIVE)
 #define PIN_ALT5_HIGHDRIVE     (_PIN_MODE_ALT5 | _PIN_OUTPUT_HIGHDRIVE)

 #define PIN_ALT6               _PIN_MODE_ALT6
@@ -188,8 +188,8 @@
 #define PIN_ALT6_OUTPUT        (_PIN_MODE_ALT6 | _PIN_OUTPUT)
 #define PIN_ALT6_FAST          (_PIN_MODE_ALT6 | _PIN_OUTPUT_FAST)
 #define PIN_ALT6_SLOW          (_PIN_MODE_ALT6 | _PIN_OUTPUT_SLOW)
-#define PIN_ALT6_OPENDRAIN     (_PIN_MODE_ALT6 | _PIN_OUTPUT_LOWDRIVE)
-#define PIN_ALT6_LOWDRIVE      (_PIN_MODE_ALT6 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT6_OPENDRAIN     (_PIN_MODE_ALT6 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT6_LOWDRIVE      (_PIN_MODE_ALT6 | _PIN_OUTPUT_LOWDRIVE)
 #define PIN_ALT6_HIGHDRIVE     (_PIN_MODE_ALT6 | _PIN_OUTPUT_HIGHDRIVE)

 #define PIN_ALT7               _PIN_MODE_ALT7
@@ -199,8 +199,8 @@
 #define PIN_ALT7_OUTPUT        (_PIN_MODE_ALT7 | _PIN_OUTPUT)
 #define PIN_ALT7_FAST          (_PIN_MODE_ALT7 | _PIN_OUTPUT_FAST)
 #define PIN_ALT7_SLOW          (_PIN_MODE_ALT7 | _PIN_OUTPUT_SLOW)
-#define PIN_ALT7_OPENDRAIN     (_PIN_MODE_ALT7 | _PIN_OUTPUT_LOWDRIVE)
-#define PIN_ALT7_LOWDRIVE      (_PIN_MODE_ALT7 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT7_OPENDRAIN     (_PIN_MODE_ALT7 | _PIN_OUTPUT_OPENDRAIN)
+#define PIN_ALT7_LOWDRIVE      (_PIN_MODE_ALT7 | _PIN_OUTPUT_LOWDRIVE)
 #define PIN_ALT7_HIGHDRIVE     (_PIN_MODE_ALT7 | _PIN_OUTPUT_HIGHDRIVE)

 /* The initial value for GPIO (Alternative 1 outputs):
@@ -1,6 +1,5 @@
 /****************************************************************************
 * arch/arm/src/kinetis/kinetis_clrpend.c
- * arch/arm/src/chip/kinetis_clrpend.c
 *
 *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -92,6 +92,18 @@
 #  undef CONFIG_SDIO_XFRDEBUG
 #endif

+/* Enable pull-up resistors
+ *
+ * Kinetis does not have pullups on all their development boards
+ * So allow the the board config to enable them.
+ */
+
+#if defined(BOARD_SDHC_ENABLE_PULLUPS)
+#  define BOARD_SDHC_PULLUP_ENABLE _PIN_INPUT_PULLUP
+#else
+#  define BOARD_SDHC_PULLUP_ENABLE 0
+#endif
+
 /* SDCLK frequencies corresponding to various modes of operation.  These
 * values may be provided in either the NuttX configuration file or in
 * the board.h file
@@ -2844,29 +2856,29 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
 #ifndef CONFIG_SDIO_MUXBUS
  /* Data width 1, 4 or 8 */

-  kinetis_pinconfig(PIN_SDHC0_D0);
+  kinetis_pinconfig(PIN_SDHC0_D0 | BOARD_SDHC_PULLUP_ENABLE);

  /* Data width 4 or 8 */

 #ifndef CONFIG_KINETIS_SDHC_WIDTH_D1_ONLY
-  kinetis_pinconfig(PIN_SDHC0_D1);
-  kinetis_pinconfig(PIN_SDHC0_D2);
-  kinetis_pinconfig(PIN_SDHC0_D3);
+  kinetis_pinconfig(PIN_SDHC0_D1 | BOARD_SDHC_PULLUP_ENABLE);
+  kinetis_pinconfig(PIN_SDHC0_D2 | BOARD_SDHC_PULLUP_ENABLE);
+  kinetis_pinconfig(PIN_SDHC0_D3 | BOARD_SDHC_PULLUP_ENABLE);

  /* Data width 8 (not supported) */

 #if 0
-  kinetis_pinconfig(PIN_SDHC0_D4);
-  kinetis_pinconfig(PIN_SDHC0_D5);
-  kinetis_pinconfig(PIN_SDHC0_D6);
-  kinetis_pinconfig(PIN_SDHC0_D7);
+  kinetis_pinconfig(PIN_SDHC0_D4 | BOARD_SDHC_PULLUP_ENABLE);
+  kinetis_pinconfig(PIN_SDHC0_D5 | BOARD_SDHC_PULLUP_ENABLE);
+  kinetis_pinconfig(PIN_SDHC0_D6 | BOARD_SDHC_PULLUP_ENABLE);
+  kinetis_pinconfig(PIN_SDHC0_D7 | BOARD_SDHC_PULLUP_ENABLE);
 #endif
 #endif

  /* Clocking and CMD pins (all data widths) */

  kinetis_pinconfig(PIN_SDHC0_DCLK);
-  kinetis_pinconfig(PIN_SDHC0_CMD);
+  kinetis_pinconfig(PIN_SDHC0_CMD | BOARD_SDHC_PULLUP_ENABLE);
 #endif

  /* Reset the card and assure that it is in the initial, unconfigured
@@ -2916,6 +2928,8 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
      priv->cdstatus &= ~SDIO_STATUS_PRESENT;
    }

+  leave_critical_section(flags);
+
  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);

  /* Perform any requested callback if the status has changed */
@@ -2924,8 +2938,6 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
    {
      kinetis_callback(priv);
    }
-
-  leave_critical_section(flags);
 }

 /****************************************************************************
@@ -1,6 +1,5 @@
 /****************************************************************************
 * arch/arm/src/kinetis/kinetis_start.c
- * arch/arm/src/chip/kinetis_start.c
 *
 *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
@@ -327,6 +326,7 @@ void __start(void)
   * can get debug output as soon as possible (This depends on clock
   * configuration).
   */
+
  kinetis_fpuconfig();
  kinetis_lowsetup();
 #ifdef USE_EARLYSERIALINIT
@@ -484,7 +484,7 @@ exception_common:
 	.global	g_intstackbase
 	.align	8
 g_intstackalloc:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~7)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.size	g_intstackalloc, .-g_intstackalloc
 #endif
@@ -122,8 +122,8 @@ config ADC0_AVERAGE
 	default 200

 config ADC0_MASK
-	int "ADC0 mask"
-	default 1
+	hex "ADC0 mask"
+	default 0x01

 config ADC0_SPS
 	int "ADC0 SPS"
@@ -489,8 +489,8 @@ config ADC0_AVERAGE
 	default 200

 config ADC0_MASK
-	int "ADC0 mask"
-	default 1
+	hex "ADC0 mask"
+	default 0x01

 config ADC0_SPS
 	int "ADC0 SPS"
@@ -348,7 +348,7 @@ exception_common:
 	 *
 	 * Here:
 	 *   r0 = Address of the register save area
-	
+	 *
 	 * NOTE: It is a requirement that up_restorefpu() preserve the value of
 	 * r0!
 	 */
@@ -468,7 +468,7 @@ exception_common:
 	.global	g_intstackbase
 	.align	8
 g_intstackalloc:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~7)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.size	g_intstackalloc, .-g_intstackalloc
 #endif
@@ -40,6 +40,9 @@ config ARCH_CHIP_LPC4337JBD144
 config ARCH_CHIP_LPC4337JET100
 	bool "LPC4337JET100"

+config ARCH_CHIP_LPC4337FET256
+	bool "LPC4337FET256"
+
 config ARCH_CHIP_LPC4350FBD208
 	bool "LPC4350FBD208"

@@ -91,7 +94,7 @@ config ARCH_FAMILY_LPC4330

 config ARCH_FAMILY_LPC4337
 	bool
-	default y if ARCH_CHIP_LPC4337JBD144
+	default y if ARCH_CHIP_LPC4337JBD144 || ARCH_CHIP_LPC4337FET256
 	select ARCH_HAVE_TICKLESS
 	select ARCH_HAVE_AHB_SRAM_BANK1

@@ -335,6 +338,19 @@ config LPC43_WWDT

 endmenu # LPC43xx Peripheral Support

+menu "ADC driver options"
+	depends on LPC43_ADC0 || LPC43_ADC1
+
+config ADC0_MASK
+	hex "ADC0 mask"
+	default 0x01
+
+config ADC0_FREQ
+	int "ADC0 frequency"
+	default 4500000
+
+endmenu # ADC driver options
+
 config LPC43_GPIO_IRQ
 	bool "GPIO interrupt support"
 	default n
@@ -101,6 +101,10 @@
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
 #  include "chip/lpc435357_memorymap.h"
 #  include "chip/lpc4357fet256_pinconfig.h"
+#elif defined(CONFIG_ARCH_CHIP_LPC4337FET256)
+#  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
+#  include "chip/lpc435357_memorymap.h"
+#  include "chip/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
 #  include "chip/lpc4310203050_memorymap.h"
@@ -473,10 +473,10 @@
 #define PINCONF_GP_CLKIN_2       (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_0)
 #define PINCONF_GP_CLKIN_3       (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_4)

-#define PINCONF_I2C1_SCL_1       (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_4)
-#define PINCONF_I2C1_SCL_2       (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_15)
-#define PINCONF_I2C1_SDA_1       (PINCONF_FUNC1|PINCONF_PINS2|PINCONF_PIN_3)
-#define PINCONF_I2C1_SDA_2       (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_I2C1_SCL_1       (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_I2C1_SCL_2       (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_I2C1_SDA_1       (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_I2C1_SDA_2       (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_13)

 #define PINCONF_I2S0_RX_MCLK_1   (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_0)
 #define PINCONF_I2S0_RX_MCLK_2   (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_0)
@@ -634,78 +634,78 @@
 #define PINCONF_SD_WP_1          (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_15)
 #define PINCONF_SD_WP_2          (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_10)

-#define PINCONF_SGPIO0_1         (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_0)
-#define PINCONF_SGPIO0_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_0)
-#define PINCONF_SGPIO0_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_1)
-#define PINCONF_SGPIO1_1         (PINCONF_FUNC3|PINCONF_PINS0|PINCONF_PIN_1)
-#define PINCONF_SGPIO1_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_1)
-#define PINCONF_SGPIO1_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_2)
-#define PINCONF_SGPIO2_1         (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_15)
-#define PINCONF_SGPIO2_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_2)
-#define PINCONF_SGPIO2_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_3)
-#define PINCONF_SGPIO3_1         (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_16)
-#define PINCONF_SGPIO3_2         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_5)
-#define PINCONF_SGPIO3_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_9)
-#define PINCONF_SGPIO4_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_0)
-#define PINCONF_SGPIO4_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_3)
-#define PINCONF_SGPIO4_3         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_4)
-#define PINCONF_SGPIO4_4         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_5)
-#define PINCONF_SGPIO4_5         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_0)
-#define PINCONF_SGPIO4_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_0)
-#define PINCONF_SGPIO5_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_1)
-#define PINCONF_SGPIO5_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_6)
-#define PINCONF_SGPIO5_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_6)
-#define PINCONF_SGPIO5_4         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_1)
-#define PINCONF_SGPIO5_5         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_1)
-#define PINCONF_SGPIO6_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_2)
-#define PINCONF_SGPIO6_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_7)
-#define PINCONF_SGPIO6_3         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_7)
-#define PINCONF_SGPIO6_4         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_2)
-#define PINCONF_SGPIO6_5         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_2)
-#define PINCONF_SGPIO7_1         (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_6)
-#define PINCONF_SGPIO7_2         (PINCONF_FUNC2|PINCONF_PINS6|PINCONF_PIN_8)
-#define PINCONF_SGPIO7_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_0)
-#define PINCONF_SGPIO7_4         (PINCONF_FUNC6|PINCONF_PINSF|PINCONF_PIN_8)
-#define PINCONF_SGPIO7_5         (PINCONF_FUNC7|PINCONF_PINS7|PINCONF_PIN_7)
-#define PINCONF_SGPIO7_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_3)
-#define PINCONF_SGPIO8_1         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_1)
-#define PINCONF_SGPIO8_2         (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_0)
-#define PINCONF_SGPIO8_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_12)
-#define PINCONF_SGPIO8_4         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_6)
-#define PINCONF_SGPIO8_5         (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_2)
-#define PINCONF_SGPIO8_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_4)
-#define PINCONF_SGPIO9_1         (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_2)
-#define PINCONF_SGPIO9_2         (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_1)
-#define PINCONF_SGPIO9_3         (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_13)
-#define PINCONF_SGPIO9_4         (PINCONF_FUNC6|PINCONF_PINS9|PINCONF_PIN_3)
-#define PINCONF_SGPIO9_5         (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_3)
-#define PINCONF_SGPIO9_6         (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_5)
-#define PINCONF_SGPIO10_1        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_3)
-#define PINCONF_SGPIO10_2        (PINCONF_FUNC4|PINCONF_PINS8|PINCONF_PIN_2)
-#define PINCONF_SGPIO10_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_14)
-#define PINCONF_SGPIO10_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_4)
-#define PINCONF_SGPIO10_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_6)
-#define PINCONF_SGPIO11_1        (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_4)
-#define PINCONF_SGPIO11_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_12)
-#define PINCONF_SGPIO11_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_17)
-#define PINCONF_SGPIO11_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_5)
-#define PINCONF_SGPIO11_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_7)
-#define PINCONF_SGPIO12_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_3)
-#define PINCONF_SGPIO12_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_13)
-#define PINCONF_SGPIO12_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_18)
-#define PINCONF_SGPIO12_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_6)
-#define PINCONF_SGPIO12_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_8)
-#define PINCONF_SGPIO13_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_4)
-#define PINCONF_SGPIO13_2        (PINCONF_FUNC5|PINCONF_PINSC|PINCONF_PIN_14)
-#define PINCONF_SGPIO13_3        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_20)
-#define PINCONF_SGPIO13_4        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_8)
-#define PINCONF_SGPIO13_5        (PINCONF_FUNC7|PINCONF_PINSD|PINCONF_PIN_9)
-#define PINCONF_SGPIO14_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_5)
-#define PINCONF_SGPIO14_2        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_6)
-#define PINCONF_SGPIO14_3        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_9)
-#define PINCONF_SGPIO15_1        (PINCONF_FUNC0|PINCONF_PINS2|PINCONF_PIN_8)
-#define PINCONF_SGPIO15_2        (PINCONF_FUNC6|PINCONF_PINS1|PINCONF_PIN_5)
-#define PINCONF_SGPIO15_3        (PINCONF_FUNC7|PINCONF_PINS4|PINCONF_PIN_10)
+#define PINCONF_SGPIO0_1         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_SGPIO0_2         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_0)
+#define PINCONF_SGPIO0_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_1         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_2         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_SGPIO1_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_SGPIO2_1         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_15)
+#define PINCONF_SGPIO2_2         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_2)
+#define PINCONF_SGPIO2_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_SGPIO3_1         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_SGPIO3_2         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_5)
+#define PINCONF_SGPIO3_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_9)
+#define PINCONF_SGPIO4_1         (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_SGPIO4_2         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_SGPIO4_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_SGPIO4_4         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_5)
+#define PINCONF_SGPIO4_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_0)
+#define PINCONF_SGPIO4_6         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_SGPIO5_1         (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_SGPIO5_2         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_SGPIO5_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_SGPIO5_4         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_1)
+#define PINCONF_SGPIO5_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_SGPIO6_1         (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_SGPIO6_2         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_SGPIO6_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_7)
+#define PINCONF_SGPIO6_4         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_SGPIO6_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_SGPIO7_1         (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_SGPIO7_2         (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_SGPIO7_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_SGPIO7_4         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_8)
+#define PINCONF_SGPIO7_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_7)
+#define PINCONF_SGPIO7_6         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_SGPIO8_1         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_SGPIO8_2         (PINCONF_FUNC4|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_0)
+#define PINCONF_SGPIO8_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_SGPIO8_4         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_6)
+#define PINCONF_SGPIO8_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_SGPIO8_6         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_SGPIO9_1         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_SGPIO9_2         (PINCONF_FUNC4|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_1)
+#define PINCONF_SGPIO9_3         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_SGPIO9_4         (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_3)
+#define PINCONF_SGPIO9_5         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_3)
+#define PINCONF_SGPIO9_6         (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_SGPIO10_1        (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_SGPIO10_2        (PINCONF_FUNC4|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS8|PINCONF_PIN_2)
+#define PINCONF_SGPIO10_3        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_SGPIO10_4        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_4)
+#define PINCONF_SGPIO10_5        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_SGPIO11_1        (PINCONF_FUNC2|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_SGPIO11_2        (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_12)
+#define PINCONF_SGPIO11_3        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_17)
+#define PINCONF_SGPIO11_4        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_5)
+#define PINCONF_SGPIO11_5        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_SGPIO12_1        (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_3)
+#define PINCONF_SGPIO12_2        (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_13)
+#define PINCONF_SGPIO12_3        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18)
+#define PINCONF_SGPIO12_4        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_6)
+#define PINCONF_SGPIO12_5        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_SGPIO13_1        (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_SGPIO13_2        (PINCONF_FUNC5|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSC|PINCONF_PIN_14)
+#define PINCONF_SGPIO13_3        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_20)
+#define PINCONF_SGPIO13_4        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_8)
+#define PINCONF_SGPIO13_5        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_SGPIO14_1        (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_5)
+#define PINCONF_SGPIO14_2        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_SGPIO14_3        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_9)
+#define PINCONF_SGPIO15_1        (PINCONF_FUNC0|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_SGPIO15_2        (PINCONF_FUNC6|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_SGPIO15_3        (PINCONF_FUNC7|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_10)

 #define PINCONF_SPIFI_CS         (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_PINS3|PINCONF_PIN_8)
 #define PINCONF_SPIFI_MISO       (PINCONF_FUNC3|PINCONF_SLEW_FAST|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS3|PINCONF_PIN_6)
@@ -719,11 +719,11 @@
 #define PINCONF_SPI_SCK          (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_3)
 #define PINCONF_SPI_SSEL         (PINCONF_FUNC1|PINCONF_PINS3|PINCONF_PIN_8)

-#define PINCONF_SSP0_MISO_1      (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_7)
-#define PINCONF_SSP0_MISO_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_2)
-#define PINCONF_SSP0_MISO_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_1)
-#define PINCONF_SSP0_MISO_4      (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_6)
-#define PINCONF_SSP0_MISO_5      (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_1)
+#define PINCONF_SSP0_MISO_1      (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_7)
+#define PINCONF_SSP0_MISO_2      (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_2)
+#define PINCONF_SSP0_MISO_3      (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_SSP0_MISO_4      (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_6)
+#define PINCONF_SSP0_MISO_5      (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_1)
 #define PINCONF_SSP0_MOSI_1      (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_8)
 #define PINCONF_SSP0_MOSI_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_3)
 #define PINCONF_SSP0_MOSI_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_2)
@@ -738,9 +738,9 @@
 #define PINCONF_SSP0_SSEL_4      (PINCONF_FUNC5|PINCONF_PINS3|PINCONF_PIN_8)
 #define PINCONF_SSP0_SSEL_5      (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_0)

-#define PINCONF_SSP1_MISO_1      (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_0)
-#define PINCONF_SSP1_MISO_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_6)
-#define PINCONF_SSP1_MISO_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_SSP1_MISO_1      (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINS0|PINCONF_PIN_0)
+#define PINCONF_SSP1_MISO_2      (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_6)
+#define PINCONF_SSP1_MISO_3      (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_3)
 #define PINCONF_SSP1_MOSI_1      (PINCONF_FUNC1|PINCONF_PINS0|PINCONF_PIN_1)
 #define PINCONF_SSP1_MOSI_2      (PINCONF_FUNC2|PINCONF_PINSF|PINCONF_PIN_7)
 #define PINCONF_SSP1_MOSI_3      (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_4)
@@ -866,10 +866,10 @@

 #define PINCONF_U2_DIR_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_18)
 #define PINCONF_U2_DIR_2         (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_13)
-#define PINCONF_U2_RXD_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_16)
-#define PINCONF_U2_RXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_11)
-#define PINCONF_U2_RXD_3         (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_2)
-#define PINCONF_U2_RXD_4         (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_2)
+#define PINCONF_U2_RXD_1         (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_16)
+#define PINCONF_U2_RXD_2         (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_U2_RXD_3         (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_2)
+#define PINCONF_U2_RXD_4         (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_2)
 #define PINCONF_U2_TXD_1         (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_15)
 #define PINCONF_U2_TXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_10)
 #define PINCONF_U2_TXD_3         (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_1)
@@ -883,10 +883,10 @@
 #define PINCONF_U3_DIR_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_6)
 #define PINCONF_U3_DIR_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_8)
 #define PINCONF_U3_DIR_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_4)
-#define PINCONF_U3_RXD_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_3)
-#define PINCONF_U3_RXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_4)
-#define PINCONF_U3_RXD_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_2)
-#define PINCONF_U3_RXD_4         (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_4)
+#define PINCONF_U3_RXD_1         (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_3)
+#define PINCONF_U3_RXD_2         (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4)
+#define PINCONF_U3_RXD_3         (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_2)
+#define PINCONF_U3_RXD_4         (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_4)
 #define PINCONF_U3_TXD_1         (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_2)
 #define PINCONF_U3_TXD_2         (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_3)
 #define PINCONF_U3_TXD_3         (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_1)
@@ -59,7 +59,7 @@
 #define LPC43_GPDMA_SOFTSREQ_OFFSET       0x0024 /* DMA Software Single Request Register */
 #define LPC43_GPDMA_SOFTLBREQ_OFFSET      0x0028 /* DMA Software Last Burst Request Register */
 #define LPC43_GPDMA_SOFTLSREQ_OFFSET      0x002c /* DMA Software Last Single Request Register */
-#define LPC43_GPDMA_CONFIG_OFFSET         0x0030 /* DMA Configuration Register */
+#define LPC43_GPDMA_GLOBAL_CONFIG_OFFSET  0x0030 /* DMA Configuration Register */
 #define LPC43_GPDMA_SYNC_OFFSET           0x0034 /* DMA Synchronization Register */

 /* Channel registers */
@@ -139,7 +139,7 @@
 #define LPC43_GPDMA_SOFTSREQ              (LPC43_DMA_BASE+LPC43_GPDMA_SOFTSREQ_OFFSET)
 #define LPC43_GPDMA_SOFTLBREQ             (LPC43_DMA_BASE+LPC43_GPDMA_SOFTLBREQ_OFFSET)
 #define LPC43_GPDMA_SOFTLSREQ             (LPC43_DMA_BASE+LPC43_GPDMA_SOFTLSREQ_OFFSET)
-#define LPC43_GPDMA_CONFIG                (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET)
+#define LPC43_GPDMA_GLOBAL_CONFIG         (LPC43_DMA_BASE+LPC43_GPDMA_GLOBAL_CONFIG_OFFSET)
 #define LPC43_GPDMA_SYNC                  (LPC43_DMA_BASE+LPC43_GPDMA_SYNC_OFFSET)

 /* Channel registers */
@@ -261,9 +261,9 @@
                                                     /* Bits 16-31: Reserved */
 /* DMA Configuration Register */

-#define GPDMA_CONFIG_ENA                  (1 << 0)  /* Bit 0:  DMA Controller enable */
-#define GPDMA_CONFIG_M0                   (1 << 1)  /* Bit 1:  AHB Master 0 endianness configuration */
-#define GPDMA_CONFIG_M1                   (1 << 2)  /* Bit 2:  M1 AHB Master 1 endianness configuration */
+#define GPDMA_GLOBAL_CONFIG_ENA           (1 << 0)  /* Bit 0:  DMA Controller enable */
+#define GPDMA_GLOBAL_CONFIG_M0            (1 << 1)  /* Bit 1:  AHB Master 0 endianness configuration */
+#define GPDMA_GLOBAL_CONFIG_M1            (1 << 2)  /* Bit 2:  M1 AHB Master 1 endianness configuration */
                                                    /* Bits 3-31: Reserved */
 /* DMA Synchronization Register */

@@ -283,15 +283,15 @@
 #define GPDMA_CONTROL_XFRSIZE_SHIFT      (0)       /* Bits 0-11: Transfer size in number of transfers */
 #define GPDMA_CONTROL_XFRSIZE_MASK       (0xfff << GPDMA_CONTROL_XFRSIZE_SHIFT)
 #define GPDMA_CONTROL_SBSIZE_SHIFT       (12)      /* Bits 12-14: Source burst size */
-#define GPDMA_CONTROL_SBSIZE_MASK        (7 << GPDMA_CONTROL_XFRSIZE_MASK)
-#  define GPDMA_CONTROL_SBSIZE_1         (0 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 1 */
-#  define GPDMA_CONTROL_SBSIZE_4         (1 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 4 */
-#  define GPDMA_CONTROL_SBSIZE_8         (2 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 8 */
-#  define GPDMA_CONTROL_SBSIZE_16        (3 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 16 */
-#  define GPDMA_CONTROL_SBSIZE_32        (4 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 32 */
-#  define GPDMA_CONTROL_SBSIZE_64        (5 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 64 */
-#  define GPDMA_CONTROL_SBSIZE_128       (6 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 128 */
-#  define GPDMA_CONTROL_SBSIZE_256       (7 << GPDMA_CONTROL_XFRSIZE_MASK) /* Source burst size = 256 */
+#define GPDMA_CONTROL_SBSIZE_MASK        (7 << GPDMA_CONTROL_SBSIZE_SHIFT)
+#  define GPDMA_CONTROL_SBSIZE_1         (0 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 1 */
+#  define GPDMA_CONTROL_SBSIZE_4         (1 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 4 */
+#  define GPDMA_CONTROL_SBSIZE_8         (2 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 8 */
+#  define GPDMA_CONTROL_SBSIZE_16        (3 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 16 */
+#  define GPDMA_CONTROL_SBSIZE_32        (4 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 32 */
+#  define GPDMA_CONTROL_SBSIZE_64        (5 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 64 */
+#  define GPDMA_CONTROL_SBSIZE_128       (6 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 128 */
+#  define GPDMA_CONTROL_SBSIZE_256       (7 << GPDMA_CONTROL_SBSIZE_SHIFT) /* Source burst size = 256 */
 #define GPDMA_CONTROL_DBSIZE_SHIFT       (15)      /* Bits 15-17: Destination burst size */
 #define GPDMA_CONTROL_DBSIZE_MASK        (7 << GPDMA_CONTROL_DBSIZE_SHIFT)
 #  define GPDMA_CONTROL_DBSIZE_1         (0 << GPDMA_CONTROL_DBSIZE_SHIFT) /* Destination burst size = 1 */
@@ -312,8 +312,12 @@
 #  define GPDMA_CONTROL_DWIDTH_BYTE      (0 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Byte (8-bit) */
 #  define GPDMA_CONTROL_DWIDTH_HWORD     (1 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Halfword (16-bit) */
 #  define GPDMA_CONTROL_DWIDTH_WORD      (2 << GPDMA_CONTROL_DWIDTH_SHIFT) /* Word (32-bit) */
-#define GPDMA_CONTROL_SS                 (1 << 24) /* Bit 24: Source AHB master select */
-#define GPDMA_CONTROL_DS                 (1 << 25) /* Bit 25: Destination AHB master select */
+#define GPDMA_CONTROL_S_SHIFT            (24) /* Bit 24: Source AHB master select */
+# define GPDMA_CONTROL_S0                (0 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 0 selected for source transfer. */
+# define GPDMA_CONTROL_S1                (1 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 1 selected for source transfer. */
+#define GPDMA_CONTROL_D_SHIFT            (25) /* Bit 25: Destination AHB master select */
+# define GPDMA_CONTROL_D0                (0 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 0 selected for destination transfer. */
+# define GPDMA_CONTROL_D1                (1 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 1 selected for destination transfer. */
 #define GPDMA_CONTROL_SI                 (1 << 26) /* Bit 26: Source increment */
 #define GPDMA_CONTROL_DI                 (1 << 27) /* Bit 27: Destination increment */
 #define GPDMA_CONTROL_PROT1              (1 << 28) /* Bit 28: Privileged mode */
@@ -45,9 +45,13 @@
 /****************************************************************************************************
 * Pre-processor Definitions
 ****************************************************************************************************/
+
+#define LPC43_SGPIO_SLICES_MASK 0x0000FFFF
+#define LPC43_SGPIO_NUM_SLICES 16
+
 /* Register Offsets *********************************************************************************/

-#define LPC43_SGPIO_OUT_MUXCFG_OFFSET(n)   (0x0000 + ((n) << 2)
+#define LPC43_SGPIO_OUT_MUXCFG_OFFSET(n)   (0x0000 + ((n) << 2))
 #define LPC43_SGPIO_OUT_MUXCFG0_OFFSET     0x0000 /* Pin multiplexer configuration register 0 */
 #define LPC43_SGPIO_OUT_MUXCFG1_OFFSET     0x0004 /* Pin multiplexer configuration register 1 */
 #define LPC43_SGPIO_OUT_MUXCFG2_OFFSET     0x0008 /* Pin multiplexer configuration register 2 */
@@ -65,7 +69,7 @@
 #define LPC43_SGPIO_OUT_MUXCFG14_OFFSET    0x0038 /* Pin multiplexer configuration register 14 */
 #define LPC43_SGPIO_OUT_MUXCFG15_OFFSET    0x003c /* Pin multiplexer configuration register 15 */

-#define LPC43_SGPIO_MUXCFG_OFFSET(n)       (0x0040 + ((n) << 2)
+#define LPC43_SGPIO_MUXCFG_OFFSET(n)       (0x0040 + ((n) << 2))
 #define LPC43_SGPIO_MUXCFG0_OFFSET         0x0040 /* SGPIO multiplexer configuration register 0 */
 #define LPC43_SGPIO_MUXCFG1_OFFSET         0x0044 /* SGPIO multiplexer configuration register 1 */
 #define LPC43_SGPIO_MUXCFG2_OFFSET         0x0048 /* SGPIO multiplexer configuration register 2 */
@@ -83,7 +87,7 @@
 #define LPC43_SGPIO_MUXCFG14_OFFSET        0x0078 /* SGPIO multiplexer configuration register 14 */
 #define LPC43_SGPIO_MUXCFG15_OFFSET        0x007c /* SGPIO multiplexer configuration register 15 */

-#define LPC43_SGPIO_SLICE_MUXCFG_OFFSET(n) (0x0080 + ((n) << 2)
+#define LPC43_SGPIO_SLICE_MUXCFG_OFFSET(n) (0x0080 + ((n) << 2))
 #define LPC43_SGPIO_SLICE_MUXCFG0_OFFSET   0x0080 /* Slice multiplexer configuration register 0 */
 #define LPC43_SGPIO_SLICE_MUXCFG1_OFFSET   0x0084 /* Slice multiplexer configuration register 1 */
 #define LPC43_SGPIO_SLICE_MUXCFG2_OFFSET   0x0088 /* Slice multiplexer configuration register 2 */
@@ -101,7 +105,7 @@
 #define LPC43_SGPIO_SLICE_MUXCFG14_OFFSET  0x00b8 /* Slice multiplexer configuration register 14 */
 #define LPC43_SGPIO_SLICE_MUXCFG15_OFFSET  0x00bc /* Slice multiplexer configuration register 15 */

-#define LPC43_SGPIO_REG_OFFSET(n)          (0x00c0 + ((n) << 2)
+#define LPC43_SGPIO_REG_OFFSET(n)          (0x00c0 + ((n) << 2))
 #define LPC43_SGPIO_REG0_OFFSET            0x00c0 /* Slice data register 0 */
 #define LPC43_SGPIO_REG1_OFFSET            0x00c4 /* Slice data register 1 */
 #define LPC43_SGPIO_REG2_OFFSET            0x00c8 /* Slice data register 2 */
@@ -119,7 +123,7 @@
 #define LPC43_SGPIO_REG14_OFFSET           0x00f8 /* Slice data register 14 */
 #define LPC43_SGPIO_REG15_OFFSET           0x00fc /* Slice data register 15 */

-#define LPC43_SGPIO_REG_SS_OFFSET(n)       (0x0100 + ((n) << 2)
+#define LPC43_SGPIO_REG_SS_OFFSET(n)       (0x0100 + ((n) << 2))
 #define LPC43_SGPIO_REG_SS0_OFFSET         0x0100 /* Slice data shadow register 0 */
 #define LPC43_SGPIO_REG_SS1_OFFSET         0x0104 /* Slice data shadow register 1 */
 #define LPC43_SGPIO_REG_SS2_OFFSET         0x0108 /* Slice data shadow register 2 */
@@ -137,7 +141,7 @@
 #define LPC43_SGPIO_REG_SS14_OFFSET        0x0138 /* Slice data shadow register 14 */
 #define LPC43_SGPIO_REG_SS15_OFFSET        0x013c /* Slice data shadow register 15 */

-#define LPC43_SGPIO_PRESET_OFFSET(n)       (0x0140 + ((n) << 2)
+#define LPC43_SGPIO_PRESET_OFFSET(n)       (0x0140 + ((n) << 2))
 #define LPC43_SGPIO_PRESET0_OFFSET         0x0140 /* COUNT0 reload value */
 #define LPC43_SGPIO_PRESET1_OFFSET         0x0144 /* COUNT1 reload value */
 #define LPC43_SGPIO_PRESET2_OFFSET         0x0148 /* COUNT2 reload value */
@@ -155,7 +159,7 @@
 #define LPC43_SGPIO_PRESET14_OFFSET        0x0178 /* COUNT14 reload value */
 #define LPC43_SGPIO_PRESET15_OFFSET        0x017c /* COUNT15 reload value */

-#define LPC43_SGPIO_COUNT_OFFSET(n)        (0x0180 + ((n) << 2)
+#define LPC43_SGPIO_COUNT_OFFSET(n)        (0x0180 + ((n) << 2))
 #define LPC43_SGPIO_COUNT0_OFFSET          0x0180 /* Down counter 0 */
 #define LPC43_SGPIO_COUNT1_OFFSET          0x0184 /* Down counter 1 */
 #define LPC43_SGPIO_COUNT2_OFFSET          0x0188 /* Down counter 2 */
@@ -173,7 +177,7 @@
 #define LPC43_SGPIO_COUNT14_OFFSET         0x01b8 /* Down counter 14 */
 #define LPC43_SGPIO_COUNT15_OFFSET         0x01bc /* Down counter 15 */

-#define LPC43_SGPIO_POS_OFFSET(n)          (0x01c0 + ((n) << 2)
+#define LPC43_SGPIO_POS_OFFSET(n)          (0x01c0 + ((n) << 2))
 #define LPC43_SGPIO_POS0_OFFSET            0x01c0 /* Position register 0 */
 #define LPC43_SGPIO_POS1_OFFSET            0x01c4 /* Position register 1 */
 #define LPC43_SGPIO_POS2_OFFSET            0x01c8 /* Position register 2 */
@@ -443,7 +447,7 @@
 #define SGPIO_OUT_MUXCFG_OUTCFG_SHIFT      (0)       /* Bits 0-3: P_OUT_CFG Output control SGPIOn */
 #define SGPIO_OUT_MUXCFG_OUTCFG_MASK       (15 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)
 #  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM1   (0 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm1 (1-bit mode) */
-#  define SGPIO_OUT_MUXCFG_OUTCFG_ DOUTM2A (1 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2a (2-bit mode 2a) */
+#  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM2A  (1 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2a (2-bit mode 2a) */
 #  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM2B  (2 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2b (2-bit mode 2b) */
 #  define SGPIO_OUT_MUXCFG_OUTCFG_DOUTM2C  (3 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* dout_doutm2c (2-bit mode 2c) */
 #  define SGPIO_OUT_MUXCFG_OUTCFG_GPIOOUT  (4 << SGPIO_OUT_MUXCFG_OUTCFG_SHIFT)  /* gpio_out (level set by GPIO_OUTREG) */
@@ -557,14 +561,17 @@
 /* GPIO output control register */

 #define SGPIO_GPIO_OUTREG(n)               (1 << (n)) /* Bits 0-15: Bit i sets the output of SGPIO pin i */
+#define SGPIO_GPIO_OUTREG_SHIFT(n)         (n)
                                                      /* Bits 16-31: Reserved */
 /* GPIO output enable register */

 #define SGPIO_GPIO_OENREG(n)               (1 << (n)) /* Bits 0-15: Bit i selects the output enable state of SGPIO pin i */
+#define SGPIO_GPIO_OENREG_SHIFT(n)         (n)
                                                      /* Bits 16-31: Reserved */
 /* Slice count enable register */

 #define SGPIO_CTRL_ENABLE(n)               (1 << (n)) /* Bits 0-15: Bit n controls slice n */
+#define SGPIO_CTRL_ENABLE_SHIFT(n)         (n)
                                                      /* Bits 16-31: Reserved */
 /* Slice count disable register */

@@ -470,7 +470,7 @@ static int adc_interrupt(int irq, void *context, FAR void *arg)
    }
  else
    {
-      if (priv->freq == 0 && priv->m_ch) /* clear burst mode */
+      if (priv->freq == 0 && !priv->m_ch) /* clear burst mode */
        {
          regval = getreg32(LPC43_ADC0_CR);
          regval &= ~ADC_CR_BURST;
@@ -186,7 +186,7 @@
 #ifndef CONFIG_LPC43_BOOT_SRAM

 /* Configuration A */
-/* CONFIG_RAM_START shoudl be set to the base of local SRAM, Bank 0. */
+/* CONFIG_RAM_START should be set to the base of local SRAM, Bank 0. */

 #  if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE
 #    error "CONFIG_RAM_START must be set to the base address of RAM bank 0"
@@ -110,11 +110,10 @@
 #  error "Both CONFIG_LPC43_MII and CONFIG_LPC43_RMII defined"
 #endif

+#ifdef CONFIG_LPC43_AUTONEG
 #  ifndef CONFIG_LPC43_PHYSR
 #    error "CONFIG_LPC43_PHYSR must be defined in the NuttX configuration"
 #  endif
-
-#ifndef CONFIG_LPC43_AUTONEG
 #  ifdef CONFIG_LPC43_PHYSR_ALTCONFIG
 #    ifndef CONFIG_LPC43_PHYSR_ALTMODE
 #      error "CONFIG_LPC43_PHYSR_ALTMODE must be defined in the NuttX configuration"
@@ -3337,21 +3336,22 @@ static inline void lpc43_ethgpioconfig(FAR struct lpc43_ethmac_s *priv)
   * MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
   */

-  lpc43_pin_config(GPIO_ETH_MII_COL);
-  lpc43_pin_config(GPIO_ETH_MII_CRS);
-  lpc43_pin_config(GPIO_ETH_MII_RXD0);
-  lpc43_pin_config(GPIO_ETH_MII_RXD1);
-  lpc43_pin_config(GPIO_ETH_MII_RXD2);
-  lpc43_pin_config(GPIO_ETH_MII_RXD3);
-  lpc43_pin_config(GPIO_ETH_MII_RX_CLK);
-  lpc43_pin_config(GPIO_ETH_MII_RX_DV);
-  lpc43_pin_config(GPIO_ETH_MII_RX_ER);
-  lpc43_pin_config(GPIO_ETH_MII_TXD0);
-  lpc43_pin_config(GPIO_ETH_MII_TXD1);
-  lpc43_pin_config(GPIO_ETH_MII_TXD2);
-  lpc43_pin_config(GPIO_ETH_MII_TXD3);
-  lpc43_pin_config(GPIO_ETH_MII_TX_CLK);
-  lpc43_pin_config(GPIO_ETH_MII_TX_EN);
+  lpc43_pin_config(PINCONF_ENET_MII_COL);
+  lpc43_pin_config(PINCONF_ENET_MII_CRS);
+  lpc43_pin_config(PINCONF_ENET_MII_RXD0);
+  lpc43_pin_config(PINCONF_ENET_MII_RXD1);
+  lpc43_pin_config(PINCONF_ENET_MII_RXD2);
+  lpc43_pin_config(PINCONF_ENET_MII_RXD3);
+  lpc43_pin_config(PINCONF_ENET_MII_RX_CLK);
+  lpc43_pin_config(PINCONF_ENET_MII_RX_DV);
+  lpc43_pin_config(PINCONF_ENET_MII_RX_ER);
+  lpc43_pin_config(PINCONF_ENET_MII_TXD0);
+  lpc43_pin_config(PINCONF_ENET_MII_TXD1);
+  lpc43_pin_config(PINCONF_ENET_MII_TXD2);
+  lpc43_pin_config(PINCONF_ENET_MII_TXD3);
+  lpc43_pin_config(PINCONF_ENET_MII_TX_CLK);
+  lpc43_pin_config(PINCONF_ENET_MII_TX_EN);
+  lpc43_pin_config(PINCONF_ENET_MII_TX_ER);

  /* Set up the RMII interface. */

@@ -463,7 +463,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
    {
      priv           = &g_i2c0dev;
      priv->base     = LPC43_I2C0_BASE;
-      priv->irqid    = LPC43M0_IRQ_I2C0;
+      priv->irqid    = LPC43M4_IRQ_I2C0;
      priv->baseFreq = BOARD_ABP1_FREQUENCY;

      /* Enable, set mode */
@@ -496,7 +496,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
    {
      priv        = &g_i2c1dev;
      priv->base  = LPC43_I2C1_BASE;
-      priv->irqid = LPC43M0_IRQ_I2C1;
+      priv->irqid = LPC43M4_IRQ_I2C1;
      priv->baseFreq = BOARD_ABP3_FREQUENCY;

      /* No need to enable */
@@ -380,6 +380,8 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)

  if (mode != priv->mode)
    {
+      spiinfo("Setting mode to %d.\n", mode);
+
      /* Yes... Set CR0 appropriately */

      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
@@ -442,12 +444,15 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)

  if (nbits != priv->nbits)
    {
+      spiinfo("Setting bits per word to %d.\n", nbits);
+
      /* Yes... Set CR1 appropriately */

      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
      regval &= ~SSP_CR0_DSS_MASK;
      regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT);
-      regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET);
+      ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, regval);
+      spiinfo("SSP Control Register 0 (CR0) after setting DSS: 0x%08X.\n", regval);

      /* Save the selection so the subsequence re-configurations will be faster */

@@ -385,16 +385,6 @@ void up_irqinitialize(void)
      putreg32(0, regaddr);
    }

-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
@@ -362,7 +362,7 @@ exception_common:
 	 *
 	 * Here:
 	 *   r0 = Address of the register save area
-	
+	 *
 	 * NOTE: It is a requirement that up_restorefpu() preserve the value of
 	 * r0!
 	 */
@@ -482,7 +482,7 @@ exception_common:
 	.global	g_intstackbase
 	.align	8
 g_intstackalloc:
-	.skip	(CONFIG_ARCH_INTERRUPTSTACK & ~7)
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
 g_intstackbase:
 	.size	g_intstackalloc, .-g_intstackalloc
 #endif
@@ -431,16 +431,6 @@ void up_irqinitialize(void)
   * access to the AIC.
   */

-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Redirect all interrupts to the AIC if so configured */

  sam_aic_redirection();
@@ -381,16 +381,6 @@ void up_irqinitialize(void)
      putreg32(0, regaddr);
    }

-  /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
-  {
-    size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-    up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
-                   intstack_size);
-  }
-#endif
-
  /* Make sure that we are using the correct vector table.  The default
   * vector address is 0x0000:0000 but if we are executing code that is
   * positioned in SRAM or in external FLASH, then we may need to reset
--- a/Show More
+++ b/Show More