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arch/arm/stm32h5: IWDG remove some ifdefs, extend prescaler.
Remove the feature #ifdef guard since the file is conditionally compiled. Remove the #ifdefs for other stm32 families that came from the common stm32_wdg.h. Add additional extended prescaler values for stm32h5 IWDG. Change the WWDG_CFR_WDGTB shift value to match what it should be on stm32h5. (WWDG not supported on stm32h5 yet.) Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
This commit is contained in:
Liam Howatt
committed by
Alan C. Assis
Alan C. Assis
parent
788d3640eb
commit
b013f074f4
@@ -41,9 +41,7 @@
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#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
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#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
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#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */
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#endif
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#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
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#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
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#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
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@@ -55,9 +53,7 @@
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#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
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#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
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#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
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#if defined(CONFIG_STM32_STM32F30XX)
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# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
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#endif
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#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
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#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
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#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
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@@ -77,15 +73,17 @@
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/* Prescaler register (32-bit) */
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#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
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#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
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# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
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# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
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# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
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# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
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# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
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# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
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#define IWDG_PR_SHIFT (0) /* Bits 3-0: Prescaler divider */
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#define IWDG_PR_MASK (15 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 ( 0 << IWDG_PR_SHIFT) /* 0000: divider /4 */
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# define IWDG_PR_DIV8 ( 1 << IWDG_PR_SHIFT) /* 0001: divider /8 */
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# define IWDG_PR_DIV16 ( 2 << IWDG_PR_SHIFT) /* 0010: divider /16 */
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# define IWDG_PR_DIV32 ( 3 << IWDG_PR_SHIFT) /* 0011: divider /32 */
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# define IWDG_PR_DIV64 ( 4 << IWDG_PR_SHIFT) /* 0100: divider /64 */
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# define IWDG_PR_DIV128 ( 5 << IWDG_PR_SHIFT) /* 0101: divider /128 */
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# define IWDG_PR_DIV256 ( 6 << IWDG_PR_SHIFT) /* 0110: divider /256 */
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# define IWDG_PR_DIV512 ( 7 << IWDG_PR_SHIFT) /* 0111: divider /512 */
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# define IWDG_PR_DIV1024 ( 8 << IWDG_PR_SHIFT) /* 1xxx: divider /1024 */
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/* Reload register (32-bit) */
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@@ -98,17 +96,12 @@
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#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
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#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define IWDG_SR_WVU (1 << 2) /* Bit 2: */
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#endif
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#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */
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/* Window register (32-bit) */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define IWDG_WINR_SHIFT (0)
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# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
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#endif
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#define IWDG_WINR_SHIFT (0)
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#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
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/* Control Register (32-bit) */
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@@ -122,12 +115,16 @@
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#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
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#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
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#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
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#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
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# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
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# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
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# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
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# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
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#define WWDG_CFR_WDGTB_SHIFT (11) /* Bits 13:11 [2:0]: Timer Base */
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#define WWDG_CFR_WDGTB_MASK (7 << WWDG_CFR_WDGTB_SHIFT)
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# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 000: CK Counter Clock (PCLK1 div 4096) div 1 */
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# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 001: CK Counter Clock (PCLK1 div 4096) div 2 */
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# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 010: CK Counter Clock (PCLK1 div 4096) div 4 */
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# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 011: CK Counter Clock (PCLK1 div 4096) div 8 */
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# define WWDG_CFR_PCLK1d16 (4 << WWDG_CFR_WDGTB_SHIFT) /* 100: CK Counter Clock (PCLK1 div 4096) div 16 */
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# define WWDG_CFR_PCLK1d32 (5 << WWDG_CFR_WDGTB_SHIFT) /* 101: CK Counter Clock (PCLK1 div 4096) div 32 */
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# define WWDG_CFR_PCLK1d64 (6 << WWDG_CFR_WDGTB_SHIFT) /* 110: CK Counter Clock (PCLK1 div 4096) div 64 */
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# define WWDG_CFR_PCLK1d128 (7 << WWDG_CFR_WDGTB_SHIFT) /* 111: CK Counter Clock (PCLK1 div 4096) div 128 */
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#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
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@@ -43,8 +43,6 @@
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#include "hardware/stm32_dbgmcu.h"
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#include "stm32_wdg.h"
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#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@@ -53,7 +51,7 @@
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/* The minimum frequency of the IWDG clock is:
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*
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* Fmin = Flsi / 256
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* Fmin = Flsi / 1024
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*
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* So the maximum delay (in milliseconds) is then:
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*
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@@ -62,11 +60,11 @@
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* For example, if Flsi = 30Khz (the nominal, uncalibrated value), then the
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* maximum delay is:
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*
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* Fmin = 117.1875
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* 1000 * 4095 / Fmin = 34,944 MSec
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* Fmin = 29.296875
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* 1000 * 4095 / Fmin = 139,776 MSec
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*/
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#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256)
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#define IWDG_FMIN (STM32_LSI_FREQUENCY / 1024)
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#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN)
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/* Configuration ************************************************************/
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@@ -527,14 +525,16 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower,
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for (prescaler = 0; ; prescaler++)
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{
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/* PR = 0 -> Divider = 4 = 1 << 2
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* PR = 1 -> Divider = 8 = 1 << 3
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* PR = 2 -> Divider = 16 = 1 << 4
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* PR = 3 -> Divider = 32 = 1 << 5
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* PR = 4 -> Divider = 64 = 1 << 6
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* PR = 5 -> Divider = 128 = 1 << 7
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* PR = 6 -> Divider = 256 = 1 << 8
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* PR = n -> Divider = 1 << (n+2)
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/* PR = 0 -> Divider = 4 = 1 << 2
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* PR = 1 -> Divider = 8 = 1 << 3
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* PR = 2 -> Divider = 16 = 1 << 4
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* PR = 3 -> Divider = 32 = 1 << 5
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* PR = 4 -> Divider = 64 = 1 << 6
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* PR = 5 -> Divider = 128 = 1 << 7
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* PR = 6 -> Divider = 256 = 1 << 8
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* PR = 7 -> Divider = 512 = 1 << 9
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* PR = 8 -> Divider = 1024 = 1 << 10
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* PR = n -> Divider = 1 << (n+2)
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*/
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shift = prescaler + 2;
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@@ -558,7 +558,7 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower,
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* settings.
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*/
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if (reload <= IWDG_RLR_MAX || prescaler == 6)
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if (reload <= IWDG_RLR_MAX || prescaler == 8)
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{
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/* Note that we explicitly break out of the loop rather than using
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* the 'for' loop termination logic because we do not want the
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@@ -686,18 +686,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq)
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defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
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defined(CONFIG_STM32_JTAG_SW_ENABLE)
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{
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
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defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX)
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uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
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cr |= DBGMCU_APB1_IWDGSTOP;
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putreg32(cr, STM32_DBGMCU_APB1_FZ);
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#else /* if defined(CONFIG_STM32_STM32F10XX) */
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uint32_t cr = getreg32(STM32_DBGMCU_CR);
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cr |= DBGMCU_CR_IWDGSTOP;
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putreg32(cr, STM32_DBGMCU_CR);
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#endif
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}
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#endif
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}
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#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */
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