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Merged in raiden00/nuttx_h7 (pull request #720)
I2C support for STM32H7 * stm32h7/chip.h: update peripherals * stm32h7x3xx_rcc.h: update definitions * stm32h7x3xx_rcc.c: remove some unused code and configure I2C clocks * stm32h7: add lower half I2C driver (based on F7 I2C driver) * configs/nucleo-h743zi: add LSM303AGR and LSM6DSL configuration * Remove whitespace * sensors/lsm303agr.c, sensors/lsm6dsl.c: add mising include, remove whitespace Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
GregoryN
@@ -92,8 +92,19 @@
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/* Peripherals */
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# define STM32H7_NUSART (4) /* USART1-3, 6 */
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# define STM32H7_NUART (4) /* UART4-5, 7-8 */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
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# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
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# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
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# define STM32H7_NSPI (6) /* (6) SPI1-6 */
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# define STM32H7_NI2S (3) /* (3) I2S1-3 */
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# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
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# define STM32H7_NI2C (4) /* (4) I2C1-4 */
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# define STM32H7_NSAI (4) /* (4) SAI1-4*/
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# define STM32H7_NCAN (2) /* (2) CAN1-2 */
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# define STM32H7_NSDIO (2) /* (2) SDIO */
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#else
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# error STM32 H7 chip Family not identified
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#endif
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@@ -113,3 +113,7 @@ CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += stm32_timerisr.c
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endif
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ifeq ($(CONFIG_STM32H7_I2C),y)
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CHIP_CSRCS += stm32_i2c.c
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endif
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@@ -0,0 +1,54 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32_i2c.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Bob Feretich <bob.feretich@rafresearch.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32H7_STM32H7X3XX)
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# include "chip/stm32h7x3xx_i2c.h"
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#else
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# error "Unsupported STM32 H7 sub family"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H */
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@@ -0,0 +1,263 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32h7x3xx_i2c.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_STM32H7X3XX_I2C_H
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#define __ARCH_ARM_SRC_STM32H7_STM32H7X3XX_I2C_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
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#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
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#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
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#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
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#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
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#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
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#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
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#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
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#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
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#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
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#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
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/* Register Addresses ***************************************************************/
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#if STM32H7_NI2C > 0
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# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
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# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
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# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
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# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
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# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
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# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
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# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
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#endif
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#if STM32H7_NI2C > 1
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# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
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# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
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# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
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# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
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# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
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# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
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# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
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#endif
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#if STM32H7_NI2C > 2
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# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
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# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
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# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
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# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
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# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
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# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
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# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
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#endif
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#if STM32H7_NI2C > 3
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# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
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# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
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# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
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# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
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# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
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# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
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# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Control register 1 */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
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#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
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#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
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#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
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#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
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#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
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#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
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#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
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#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
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#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
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#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
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#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
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#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
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#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
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#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
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#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
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#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
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/* Control register 2 */
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#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
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#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
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#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
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#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
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#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
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#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
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#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
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#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
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#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
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#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
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#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
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#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
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#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
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#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
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#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
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/* Own address register 1 */
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#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
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#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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/* Own address register 2 */
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#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
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#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
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# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
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# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
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# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
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# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
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# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
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# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
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# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
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# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
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#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
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/* Timing register */
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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|
||||
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
|
||||
#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
|
||||
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
|
||||
|
||||
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
|
||||
#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
|
||||
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
|
||||
|
||||
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
|
||||
#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT)
|
||||
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
|
||||
|
||||
/* Timeout register */
|
||||
|
||||
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
|
||||
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
|
||||
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
|
||||
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
|
||||
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
|
||||
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
|
||||
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
|
||||
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
|
||||
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
|
||||
|
||||
|
||||
/* Fields unique to the Interrupt and Status register */
|
||||
|
||||
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
|
||||
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
|
||||
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
|
||||
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
|
||||
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
|
||||
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
|
||||
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
|
||||
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
|
||||
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
|
||||
|
||||
/* Interrupt and Status register and interrupt clear register */
|
||||
/* Common interrupt bits */
|
||||
|
||||
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
|
||||
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
|
||||
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
|
||||
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
|
||||
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
|
||||
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
|
||||
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
|
||||
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
|
||||
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
|
||||
|
||||
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
|
||||
|
||||
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
|
||||
| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
|
||||
|
||||
/* Packet error checking register */
|
||||
|
||||
#define I2C_PECR_MASK (0xff)
|
||||
|
||||
/* Receive data register */
|
||||
|
||||
#define I2C_RXDR_MASK (0xff)
|
||||
|
||||
/* Transmit data register */
|
||||
|
||||
#define I2C_TXDR_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_I2C_H */
|
||||
@@ -67,15 +67,15 @@
|
||||
#define STM32_RCC_PLL2FRACR_OFFSET 0x003c /* */
|
||||
#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 /* */
|
||||
#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 /* */
|
||||
#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* */
|
||||
#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* */
|
||||
#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* */
|
||||
#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0060 /* */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x0064 /* */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0068 /* */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* */
|
||||
#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */
|
||||
#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */
|
||||
#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */
|
||||
#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* Domain 3 Kernel Clock configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0060 /* Clock Source Interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x0064 /* Clock Source Interrupt Flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0068 /* Clock Source Interrupt Clear register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup Domain Control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0074 /* Clock Control and Status register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0080 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x0084 /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x007c /* AHB3 peripheral reset register */
|
||||
@@ -316,19 +316,19 @@
|
||||
/* Bits 0-3: Reserved */
|
||||
#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */
|
||||
#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT)
|
||||
#define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 0xx: */
|
||||
#define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 100: */
|
||||
#define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 101: */
|
||||
#define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 110: */
|
||||
#define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 111: */
|
||||
# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 0xx: */
|
||||
# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 100: */
|
||||
# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 101: */
|
||||
# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 110: */
|
||||
# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 111: */
|
||||
/* Bit 7: Reserved */
|
||||
#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */
|
||||
#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT)
|
||||
#define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 0xx: */
|
||||
#define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 100: */
|
||||
#define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 101: */
|
||||
#define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 110: */
|
||||
#define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 111: */
|
||||
# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 0xx: */
|
||||
# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 100: */
|
||||
# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 101: */
|
||||
# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 110: */
|
||||
# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 111: */
|
||||
/* Bits 11-31: Reserved */
|
||||
|
||||
/* Bit definitions for RCC_D3CFGR */
|
||||
@@ -336,11 +336,11 @@
|
||||
/* Bits 0-3: Reserved */
|
||||
#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */
|
||||
#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT)
|
||||
#define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) /* 0xx: */
|
||||
#define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) /* 100: */
|
||||
#define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) /* 101: */
|
||||
#define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) /* 110: */
|
||||
#define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) /* 111: */
|
||||
# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) /* 0xx: */
|
||||
# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) /* 100: */
|
||||
# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) /* 101: */
|
||||
# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) /* 110: */
|
||||
# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) /* 111: */
|
||||
/* Bits 7-31: Reserved */
|
||||
|
||||
/* Bit definitions for RCC_PLLCKSELR register */
|
||||
@@ -494,7 +494,123 @@
|
||||
#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) /* 0x0000FFF8 */
|
||||
#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK
|
||||
|
||||
/* CSR */
|
||||
|
||||
/* Bit definitions for RCC_D1CCIPR reigster */
|
||||
|
||||
#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */
|
||||
#define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT)
|
||||
# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 00: */
|
||||
# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 01: */
|
||||
# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 10: */
|
||||
# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) /* 11: */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define RCC_D1CCIPR_QSPISEL_SHIFT (0) /* Bits 4-5: */
|
||||
#define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT)
|
||||
# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 00: */
|
||||
# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 01: */
|
||||
# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 10: */
|
||||
# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) /* 11: */
|
||||
/* Bits 6-15: Reserved */
|
||||
#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 15: */
|
||||
#define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT)
|
||||
# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) /* 0: */
|
||||
# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) /* 1: */
|
||||
/* Bits 17-27: Reserved */
|
||||
/* Bits 17-27: Reserved */
|
||||
#define RCC_D1CCIPR_CKPERSEL_SHIFT (0) /* Bits 28-29: */
|
||||
#define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT)
|
||||
# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 00: */
|
||||
# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 01: */
|
||||
# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) /* 10: */
|
||||
/* 11: Reserved */
|
||||
/* Bits 30-31: Reserved */
|
||||
|
||||
/* Bit definitions for RCC_D2CCIP1R reigster */
|
||||
|
||||
#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */
|
||||
#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK)
|
||||
# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 000 */
|
||||
# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 001 */
|
||||
# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 010 */
|
||||
# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 011 */
|
||||
# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) /* 100 */
|
||||
/* Bits 3-5: Reserved */
|
||||
#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */
|
||||
#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 000 */
|
||||
# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 001 */
|
||||
# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 010 */
|
||||
# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 011 */
|
||||
# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) /* 100 */
|
||||
/* Bits 9-11: Reserved */
|
||||
#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */
|
||||
#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 000 */
|
||||
# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 001 */
|
||||
# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 010 */
|
||||
# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 011 */
|
||||
# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) /* 100 */
|
||||
/* Bit 15: Reserved */
|
||||
#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */
|
||||
#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 000 */
|
||||
# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 001 */
|
||||
# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 010 */
|
||||
# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 011 */
|
||||
# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 100 */
|
||||
# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) /* 101 */
|
||||
/* Bit 19: Reserved */
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */
|
||||
#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 00 */
|
||||
# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 01 */
|
||||
# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 10 */
|
||||
# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) /* 11 */
|
||||
/* Bits 22-23: Reserved */
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */
|
||||
#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 0 */
|
||||
# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) /* 1 */
|
||||
/* Bits 25-27: Reserved */
|
||||
#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */
|
||||
#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 00 */
|
||||
# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 01 */
|
||||
# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) /* 10 */
|
||||
/* Bit 30: Reserved */
|
||||
#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */
|
||||
#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT)
|
||||
# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */
|
||||
# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 1 */
|
||||
|
||||
/* TODO: Bit definitions for RCC_D2CCIP2R reigster */
|
||||
|
||||
/* ... */
|
||||
#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */
|
||||
#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
|
||||
/* ... */
|
||||
|
||||
/* TODO: Bit definitions for RCC_D3CCIPR reigster */
|
||||
|
||||
/* ... */
|
||||
#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9 */
|
||||
#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT)
|
||||
# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 00 */
|
||||
# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 01 */
|
||||
# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 10 */
|
||||
# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) /* 11 */
|
||||
/* ... */
|
||||
|
||||
/* TODO: CIER */
|
||||
/* TODO: CIFR */
|
||||
/* TODO: CICR */
|
||||
/* TODO: BDCR */
|
||||
|
||||
/* Bit definitions for RCC_CSR register */
|
||||
|
||||
#define RCC_CSR_LSION_SHIFT (0ul) /* RCC CSR: LSION (Bit 0) */
|
||||
#define RCC_CSR_LSION (0x1ul) /* RCC CSR: LSION (Bitfield-Mask: 0x01) */
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32H7_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32H7_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Peripherals **********************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_i2c.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_lowputc.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_i2c.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32H7_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32H7_I2C_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_i2c.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
|
||||
* seconds per byte value must be provided as well.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32H7_I2C_DYNTIMEO
|
||||
# if CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE < 1
|
||||
# warning "Ignoring CONFIG_STM32H7_I2C_DYNTIMEO because of CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE"
|
||||
# undef CONFIG_STM32H7_I2C_DYNTIMEO
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple I2C interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the stm32_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32H7_I2C_H */
|
||||
@@ -289,15 +289,40 @@ static inline void rcc_enableapb1(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1LENR);
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
regval |= RCC_APB1LENR_I2C4EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1LENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1HENR);
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1HENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_APB1HENR); /* Enable APB1H peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -577,112 +602,20 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32H7_LTDC) || defined(CONFIG_STM32H7_PLLSAI)
|
||||
/* Configure I2C source clock */
|
||||
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIP_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIQ_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIR_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR1);
|
||||
regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVR_MASK
|
||||
| RCC_DCKCFGR1_SAI1SEL_MASK
|
||||
| RCC_DCKCFGR1_SAI2SEL_MASK
|
||||
| RCC_DCKCFGR1_TIMPRESEL);
|
||||
|
||||
regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVR
|
||||
| STM32_RCC_DCKCFGR1_SAI1SRC
|
||||
| STM32_RCC_DCKCFGR1_SAI2SRC
|
||||
| STM32_RCC_DCKCFGR1_TIMPRESRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR1);
|
||||
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLSAI is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
|
||||
{
|
||||
}
|
||||
#if defined(STM32_RCC_D2CCIP2R_I2C123SRC)
|
||||
regval = getreg32(STM32_RCC_D2CCIP2R);
|
||||
regval &= ~RCC_D2CCIP2R_I2C123SEL_MASK;
|
||||
regval |= STM32_RCC_D2CCIP2R_I2C123SRC;
|
||||
putreg32(regval, STM32_RCC_D2CCIP2R);
|
||||
#endif
|
||||
#if defined(CONFIG_STM32H7_LTDC) || defined(CONFIG_STM32H7_PLLI2S)
|
||||
|
||||
/* Configure PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLI2SCFGR);
|
||||
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SP_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
|
||||
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SP
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SQ
|
||||
| STM32_RCC_PLLI2SCFGR_PLLI2SR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
|
||||
| RCC_DCKCFGR2_USART2SEL_MASK
|
||||
| RCC_DCKCFGR2_UART4SEL_MASK
|
||||
| RCC_DCKCFGR2_UART5SEL_MASK
|
||||
| RCC_DCKCFGR2_USART6SEL_MASK
|
||||
| RCC_DCKCFGR2_UART7SEL_MASK
|
||||
| RCC_DCKCFGR2_UART8SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C1SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C2SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C3SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C4SEL_MASK
|
||||
| RCC_DCKCFGR2_LPTIM1SEL_MASK
|
||||
| RCC_DCKCFGR2_CECSEL_MASK
|
||||
| RCC_DCKCFGR2_CK48MSEL_MASK
|
||||
| RCC_DCKCFGR2_SDMMCSEL_MASK);
|
||||
|
||||
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
|
||||
| STM32_RCC_DCKCFGR2_USART2SRC
|
||||
| STM32_RCC_DCKCFGR2_UART4SRC
|
||||
| STM32_RCC_DCKCFGR2_UART5SRC
|
||||
| STM32_RCC_DCKCFGR2_USART6SRC
|
||||
| STM32_RCC_DCKCFGR2_UART7SRC
|
||||
| STM32_RCC_DCKCFGR2_UART8SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C1SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C2SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C3SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C4SRC
|
||||
| STM32_RCC_DCKCFGR2_LPTIM1SRC
|
||||
| STM32_RCC_DCKCFGR2_CECSRC
|
||||
| STM32_RCC_DCKCFGR2_CK48MSRC
|
||||
| STM32_RCC_DCKCFGR2_SDMMCSRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#if defined(STM32_RCC_D3CCIPR_I2C4SRC)
|
||||
regval = getreg32(STM32_RCC_D3CCIPR);
|
||||
regval &= ~RCC_D3CCIPR_I2C4SEL_MASK;
|
||||
regval |= STM32_RCC_D3CCIPR_I2C4SRC;
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
||||
|
||||
@@ -184,6 +184,15 @@
|
||||
#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
|
||||
|
||||
/* I2C123 clock source */
|
||||
|
||||
#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
|
||||
|
||||
/* I2C4 clock source */
|
||||
|
||||
#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
* ------------ ---------- -----------
|
||||
@@ -266,7 +275,7 @@
|
||||
#define NUM_BUTTONS 1
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/* Pin Disambiguation ***************************************************************/
|
||||
/* Alternate function pin selections ************************************************/
|
||||
/* USART3 (Nucleo Virtual Console) */
|
||||
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
@@ -277,6 +286,13 @@
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
|
||||
|
||||
/* I2C1 Use Nucleo I2C pins */
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
|
||||
|
||||
/* */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
@@ -52,6 +52,14 @@ ifeq ($(CONFIG_STM32H7_SPI),y)
|
||||
CSRCS += stm32_spi.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SENSORS_LSM6DSL),y)
|
||||
CSRCS += stm32_lsm6dsl.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SENSORS_LSM303AGR),y)
|
||||
CSRCS += stm32_lsm303agr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinitialize.c
|
||||
endif
|
||||
|
||||
@@ -82,6 +82,12 @@
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
/* X-NUCLEO IKS01A2 */
|
||||
|
||||
#define GPIO_LPS22HB_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_LSM6DSL_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_LSM6DSL_INT2 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN5)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
@@ -128,4 +134,27 @@ void stm32_spidev_initialize(void);
|
||||
int stm32_adc_setup(void);
|
||||
#endif
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_lsm6dsl_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize I2C-based LSM6DSL.
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SENSORS_LSM303AGR
|
||||
int stm32_lsm6dsl_initialize(char *devpath);
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_lsm303agr_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize I2C-based LSM303AGR.
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SENSORS_LSM6DSL
|
||||
int stm32_lsm303agr_initialize(char *devpath);
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */
|
||||
|
||||
@@ -63,23 +63,25 @@
|
||||
* CONFIG_BOARD_INITIALIZE=y :
|
||||
* Called from board_initialize().
|
||||
*
|
||||
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
|
||||
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT:
|
||||
* Called from the NSH library
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bringup(void)
|
||||
{
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
int ret;
|
||||
|
||||
UNUSED(ret);
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
#ifdef CONFIG_STM32_CCM_PROCFS
|
||||
/* Register the CCM procfs entry. This must be done before the procfs is
|
||||
* mounted.
|
||||
*/
|
||||
|
||||
(void)ccm_procfs_register();
|
||||
#endif
|
||||
#endif /* CONFIG_STM32_CCM_PROCFS */
|
||||
|
||||
/* Mount the procfs file system */
|
||||
|
||||
@@ -90,7 +92,7 @@ int stm32_bringup(void)
|
||||
"ERROR: Failed to mount the PROC filesystem: %d (%d)\n",
|
||||
ret, errno);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_FS_PROCFS */
|
||||
|
||||
#ifdef CONFIG_BUTTONS
|
||||
/* Register the BUTTON driver */
|
||||
@@ -100,7 +102,7 @@ int stm32_bringup(void)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_BUTTONS */
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
@@ -110,7 +112,23 @@ int stm32_bringup(void)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_ADC */
|
||||
|
||||
#ifdef CONFIG_SENSORS_LSM6DSL
|
||||
ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0");
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize LSM6DSL driver: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_SENSORS_LSM6DSL */
|
||||
|
||||
#ifdef CONFIG_SENSORS_LSM303AGR
|
||||
ret = stm32_lsm303agr_initialize("/dev/lsm303mag0");
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to initialize LSM303AGR driver: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_SENSORS_LSM303AGR */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
/*****************************************************************************
|
||||
* configs/nucleo-h743zi/src/stm32_lsm303agr.c
|
||||
*
|
||||
* Copyright (C) 2018 Greg Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "stm32.h"
|
||||
#include <nucleo-h743zi.h>
|
||||
#include <nuttx/sensors/lsm303agr.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_STM32H7_I2C1
|
||||
# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled"
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_lsm303agr_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize I2C-based LSM303AGR.
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_lsm303agr_initialize(char *devpath)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret = OK;
|
||||
|
||||
sninfo("INFO: Initializing LMS303AGR sensor over I2C\n");
|
||||
|
||||
#if defined(CONFIG_STM32H7_I2C1)
|
||||
i2c = stm32_i2cbus_initialize(1);
|
||||
if (i2c == NULL)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = lsm303agr_sensor_register("/dev/lsm303agr0", i2c, LSM303AGRMAGNETO_ADDR);
|
||||
if (ret < 0)
|
||||
{
|
||||
snerr("ERROR: Failed to initialize LMS303AGR magneto driver %s\n", devpath);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sninfo("INFO: LMS303AGR sensor has been initialized successfully\n");
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
/*****************************************************************************
|
||||
* configs/nucleo-h743zi/src/stm32_lsm6dsl.c
|
||||
*
|
||||
* Copyright (C) 2018 Greg Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "stm32.h"
|
||||
#include <nucleo-h743zi.h>
|
||||
#include <nuttx/sensors/lsm6dsl.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_STM32H7_I2C1
|
||||
# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled"
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_lsm6dsl_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize I2C-based LSM6DSL.
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_lsm6dsl_initialize(char *devpath)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret = OK;
|
||||
|
||||
sninfo("Initializing LMS6DSL!\n");
|
||||
|
||||
/* Configure the GPIO interrupt */
|
||||
|
||||
stm32_configgpio(GPIO_LPS22HB_INT1);
|
||||
|
||||
#if defined(CONFIG_STM32H7_I2C1)
|
||||
i2c = stm32_i2cbus_initialize(1);
|
||||
if (i2c == NULL)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sninfo("INFO: Initializing LMS6DSL accelero-gyro sensor over I2C%d\n", ret);
|
||||
|
||||
ret = lsm6dsl_sensor_register("/dev/lsm6dsl0", i2c, LSM6DSLACCEL_ADDR1);
|
||||
if (ret < 0)
|
||||
{
|
||||
snerr("ERROR: Failed to initialize LMS6DSL accelero-gyro driver %s\n", devpath);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sninfo("INFO: LMS6DSL sensor has been initialized successfully\n");
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -70,7 +70,7 @@ int stm32l4_lsm303agr_initialize(char *devpath)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret = OK;
|
||||
|
||||
|
||||
sninfo("INFO: Initializing LMS303AGR sensor over I2C\n");
|
||||
|
||||
#if defined(CONFIG_STM32L4_I2C1)
|
||||
@@ -79,7 +79,7 @@ int stm32l4_lsm303agr_initialize(char *devpath)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
||||
ret = lsm303agr_sensor_register("/dev/lsm303mag0", i2c, LSM303AGRMAGNETO_ADDR);
|
||||
if (ret < 0)
|
||||
{
|
||||
|
||||
@@ -70,7 +70,7 @@ int stm32l4_lsm6dsl_initialize(char *devpath)
|
||||
{
|
||||
FAR struct i2c_master_s *i2c;
|
||||
int ret = OK;
|
||||
|
||||
|
||||
sninfo("Initializing LMS6DSL!\n");
|
||||
|
||||
/* Configure the GPIO interrupt */
|
||||
@@ -83,7 +83,7 @@ int stm32l4_lsm6dsl_initialize(char *devpath)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
||||
sninfo("INFO: Initializing LMS6DSL accelero-gyro sensor over I2C%d\n", ret);
|
||||
|
||||
ret = lsm6dsl_sensor_register("/dev/lsm6dsl0", i2c, LSM6DSLACCEL_ADDR1);
|
||||
|
||||
@@ -2,9 +2,9 @@
|
||||
* drivers/sensors/lsm303agr.c
|
||||
*
|
||||
* Copyright (C) 2018 Inc. All rights reserved.
|
||||
* Author: Ben vd Veen <disruptivesolutionsnl@gmail.com>
|
||||
* Author: Ben vd Veen <disruptivesolutionsnl@gmail.com>
|
||||
* Alias: DisruptiveNL
|
||||
*
|
||||
*
|
||||
* Based on:
|
||||
*
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
@@ -57,6 +57,7 @@
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/sensors/lsm303agr.h>
|
||||
#include <nuttx/random.h>
|
||||
#include <nuttx/signal.h>
|
||||
|
||||
#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_LSM303AGR)
|
||||
|
||||
@@ -869,10 +870,10 @@ static int lsm303agr_selftest(FAR struct lsm303agr_dev_s *priv, uint32_t mode)
|
||||
*
|
||||
* Description:
|
||||
* Read the sensor.
|
||||
* A sensor in a steady state on a horizontal surface will
|
||||
* measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
|
||||
* measure 1 g. (page 30 datasheet). The X- and Y-axis have an offset
|
||||
* of 40 mg/LSB
|
||||
* A sensor in a steady state on a horizontal surface will
|
||||
* measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
|
||||
* measure 1 g. (page 30 datasheet). The X- and Y-axis have an offset
|
||||
* of 40 mg/LSB
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@@ -2,9 +2,9 @@
|
||||
* drivers/sensors/lsm6dsl.c
|
||||
*
|
||||
* Copyright (C) 2018 Inc. All rights reserved.
|
||||
* Author: Ben vd Veen <disruptivesolutionsnl@gmail.com>
|
||||
* Author: Ben vd Veen <disruptivesolutionsnl@gmail.com>
|
||||
* Alias: DisruptiveNL
|
||||
*
|
||||
*
|
||||
* Based on:
|
||||
*
|
||||
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
|
||||
@@ -57,6 +57,7 @@
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/sensors/lsm6dsl.h>
|
||||
#include <nuttx/random.h>
|
||||
#include <nuttx/signal.h>
|
||||
|
||||
#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_LSM6DSL)
|
||||
|
||||
@@ -889,10 +890,10 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
|
||||
*
|
||||
* Description:
|
||||
* Read the sensor.
|
||||
* A sensor in a steady state on a horizontal surface will
|
||||
* measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
|
||||
* measure 1 g. (page 30 datasheet). The X- and Y-axis have an offset
|
||||
* of 40 mg/LSB
|
||||
* A sensor in a steady state on a horizontal surface will
|
||||
* measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will
|
||||
* measure 1 g. (page 30 datasheet). The X- and Y-axis have an offset
|
||||
* of 40 mg/LSB
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@@ -1132,7 +1133,7 @@ static ssize_t lsm6dsl_read(FAR struct file *filep,
|
||||
}
|
||||
|
||||
/* The value is negative, so find its absolute value by taking the
|
||||
* two's complement
|
||||
* two's complement
|
||||
*/
|
||||
|
||||
else if (data > 0x8000)
|
||||
|
||||
Reference in New Issue
Block a user