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Basic i.MX1 low-level boot

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1695 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2009-04-10 22:07:20 +00:00
parent 8976d24c60
commit ae853aaa49
17 changed files with 1016 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/common/arm.h
+2 -2
View File
@@ -123,12 +123,12 @@
#define PMD_TYPE_COARSE 0x00000001
#define PMD_TYPE_SECT 0x00000002
#define PMD_TYPE_FINE 0x00000003
/* Bits 3:2: Depends on descriptor */
/* Bits 3:2: Depends on descriptor */
#define PMD_BIT4 0x00000010 /* Bit 4: Must be one */
#define PMD_DOMAIN_MASK 0x000001e0 /* Bits 8:5: Domain control bits */
#define PMD_DOMAIN(x) ((x) << 5)
#define PMD_PROTECTION 0x00000200 /* Bit 9: v5 only */
/* Bits 31:10: Depend on descriptor */
/* Bits 31:10: Depend on descriptor */
/* Level 1 Section Descriptor. Section descriptors allow fast, single
* level mapping between 1Mb address regions.
arch/arm/src/common/up_arch.h
+1 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/common/up_arch.h
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
arch/arm/src/common/up_head.S
+85 -40
View File
@@ -1,7 +1,7 @@
/********************************************************************
* common/up_head.S
/****************************************************************************
* arch/arm/src/common/up_head.S
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -14,7 +14,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
@@ -31,19 +31,19 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************/
****************************************************************************/
/********************************************************************
/****************************************************************************
* Included Files
********************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "up_internal.h"
#include "up_arch.h"
/**************************************************************************
/**********************************************************************************
* Conditional Compilation
**************************************************************************/
**********************************************************************************/
#undef ALIGNMENT_TRAP
#undef CPU_DCACHE_WRITETHROUGH
@@ -51,9 +51,41 @@
#undef CPU_DCACHE_DISABLE
#undef CPU_ICACHE_DISABLE
/********************************************************************
/* There are three operational memory configurations:
*
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case
* the boot logic must:
*
* - Configure SDRAM and,
* - Initialize the .data section in RAM.
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
# define CONFIGURE_SDRAM
/* 2. We boot in FLASH but copy ourselves to DRAM from better performance.
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case
* the boot logic must:
*
* - Configure SDRAM and,
* - Copy ourself to DRAM (after mapping it)
*/
#elif defined(CONFIG_BOOT_COPYTORAM)
# define CONFIG_SDRAM
/* 3. There is bootloader that copies us to DRAM (but probably not to the beginning)
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n). In this case the
* boot logic must:
*
* - Nothing special.
*/
#endif
/****************************************************************************
* Definitions
********************************************************************/
****************************************************************************/
/* The physical address of the beginning of SDRAM is provided by
* CONFIG_DRAM_START. The size of installed SDRAM is provided by
@@ -63,9 +95,9 @@
#define NSDRAM_SECTIONS (CONFIG_DRAM_SIZE >> 20)
/********************************************************************
/****************************************************************************
* Assembly Macros
********************************************************************/
****************************************************************************/
/* Since the page table is closely related to the NuttX base
* address, we can convert the page table base address to the
@@ -88,9 +120,9 @@
.endm
#endif
/********************************************************************
/****************************************************************************
* Name: __start
********************************************************************/
****************************************************************************/
/* We assume the bootloader has already initialized most of the h/w for
* us and that only leaves us having to do some os specific things
@@ -105,9 +137,14 @@ __start:
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0
/* Initialize DRAM using a macro provided by board-specific logic */
#ifdef CONFIG_SDRAM
config_sdram
#endif
/* Clear the 16K level 1 page table */
ldr r4, .LCppgtable /* r4=phys. page table */
ldr r4, .LCppgtable /* r4=phys. page table */
mov r0, r4
mov r1, #0
add r2, r0, #PGTABLE_SIZE
@@ -126,9 +163,9 @@ __start:
*/
mksection r0, r4 /* r0=phys. base section */
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r3, r1, r0 /* r3=flags + base */
str r3, [r4, r0, lsr #18] /* identity mapping */
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r3, r1, r0 /* r3=flags + base */
str r3, [r4, r0, lsr #18] /* identity mapping */
/* Create a "normal" single section mapping for the first
* MB of memory. Now, we have the first 1MB mapping to
@@ -137,20 +174,20 @@ __start:
* moved the physical mapping out of the way.
*/
ldr r2, .LCvpgtable /* r2=virt. page table */
ldr r2, .LCvpgtable /* r2=virt. page table */
mksection r0, r2 /* r0=virt. base section */
str r3, [r4, r0, lsr #18] /* identity mapping */
str r3, [r4, r0, lsr #18] /* identity mapping */
/* The following logic will set up the ARM926 for normal operation */
/* The following logic will set up the ARM920/ARM926 for normal operation */
mov r0, #0
mcr p15, 0, r0, c7, c7 /* Invalidate I,D caches */
mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
mcr p15, 0, r0, c8, c7 /* Invalidate I,D TLBs */
mcr p15, 0, r4, c2, c0 /* Load page table pointer */
#ifdef CPU_DCACHE_WRITETHROUGH
mov r0, #4 /* Disable write-back on caches explicitly */
mov r0, #4 /* Disable write-back on caches explicitly */
mcr p15, 7, r0, c15, c0, 0
#endif
@@ -164,17 +201,25 @@ __start:
mcr p15, 0, r0, c3, c0 /* Load domain access register */
mrc p15, 0, r0, c1, c0 /* Get control register */
/* Clear bits (see start.h) */
/* Clear bits (see arm.h) */
bic r0, r0, #(CR_R|CR_F|CR_Z)
bic r0, r0, #(CR_A|CR_C|CR_W)
bic r0, r0, #(CR_I)
/* Set bits (see start.h) */
/* Set bits (see arm.h) */
orr r0, r0, #(CR_M|CR_P|CR_D)
orr r0, r0, #(CR_S|CR_V)
/* In most architectures, vectors are reloated to 0xffff0000.
* -- but not all
*/
#ifndef CONFIG_ARCH_LOWVECTORS
orr r0, r0, #(CR_S)
#else
orr r0, r0, #(CR_S|CR_V)
#endif
#ifdef CPU_CACHE_ROUND_ROBIN
orr r0, r0, #(CR_RR)
#endif
@@ -197,9 +242,9 @@ __start:
mov pc, lr
/**************************************************************************
/**********************************************************************************
* PC_Relative Data
**************************************************************************/
**********************************************************************************/
/* These addresses are all virtual address */
@@ -211,15 +256,15 @@ __start:
.long MMU_MEMFLAGS
.type .LCppagetable, %object
.LCppgtable:
.long CONFIG_DRAM_START /* Physical start of DRAM */
.long CONFIG_DRAM_START /* Physical start of DRAM */
.type .LCvpagetable, %object
.LCvpgtable:
.long CONFIG_DRAM_VSTART /* Virtual start of DRAM */
.long CONFIG_DRAM_VSTART /* Virtual start of DRAM */
.size _start, .-_start
/**************************************************************************
/**********************************************************************************
* Name: .Lvstart
**************************************************************************/
**********************************************************************************/
/* The following is executed after the MMU has been enabled. This uses
* absolute addresses; this is not position independent.
@@ -231,19 +276,19 @@ __start:
/* Remove the temporary null mapping */
ldr r4, .LCvpgtable /* r4=virtual page table */
ldr r1, .LCppgtable /* r1=phys. page table */
ldr r4, .LCvpgtable /* r4=virtual page table */
ldr r1, .LCppgtable /* r1=phys. page table */
mksection r3, r1 /* r2=phys. base addr */
mov r0, #0 /* flags + base = 0 */
str r0, [r4, r3, lsr #18] /* Undo identity mapping */
mov r0, #0 /* flags + base = 0 */
str r0, [r4, r3, lsr #18] /* Undo identity mapping */
/* Now setup the pagetables for our normal SDRAM mappings
* mapped region. We round NUTTX_START_VADDR down to the
* nearest megabyte boundary.
*/
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r3, r3, r1 /* r3=flags + base */
ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
add r3, r3, r1 /* r3=flags + base */
add r0, r4, #(NUTTX_START_VADDR & 0xff000000) >> 18
bic r2, r3, #0x00f00000
@@ -269,7 +314,7 @@ __start:
mov fp, #0
.Lbssinit:
cmp r0, r1 /* Clear up to _bss_end_ */
cmp r0, r1 /* Clear up to _bss_end_ */
strcc fp, [r0],#4
bcc .Lbssinit
arch/arm/src/common/up_initialize.c
+5 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/common/up_initialize.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -120,6 +120,10 @@ void up_initialize(void)
up_calibratedelay();
/* Add any extra memory fragments to the memory manager */
up_addregion();
/* Initialize the interrupt subsystem */
up_irqinitialize();
arch/arm/src/common/up_internal.h
+8
View File
@@ -145,6 +145,14 @@ extern void up_vectoraddrexcptn(void);
extern void up_vectorirq(void);
extern void up_vectorfiq(void);
/* Defined in up_allocateheap.c */
#if CONFIG_MM_REGIONS > 1
void up_addregion(void);
#else
# define up_addregion()
#endif
/* Defined in up_serial.c */
#if CONFIG_NFILE_DESCRIPTORS > 0
arch/arm/src/common/up_vectors.S
+2 -1
View File
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/common/up_vectors.S
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -39,6 +39,7 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "up_arch.h"
/************************************************************************************
arch/arm/src/imx/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
up_undefinedinsn.c up_usestack.c
CHIP_ASRCS = #imx_lowputc.S imx_restart.S
CHIP_CSRCS = #imx_allocateheap.c imx_boot.c imx_decodeirq.c \
CHIP_CSRCS = imx_boot.c imx_gpio.c imx_allocateheap.c # imx_decodeirq.c \
#imx_irq.c imx_serial.c imx_timerisr.c imx_framebuffer.c
ifeq ($(CONFIG_USBDEV),y)
arch/arm/src/imx/imx_allocateheap.c
+113
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@@ -0,0 +1,113 @@
/****************************************************************************
* arch/arm/src/imx/imx_allocateheap.c
* arch/arm/src/chip/imx_allocateheap.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/mm.h>
#include <nuttx/arch.h>
#include "up_arch.h"
#include "up_internal.h"
/****************************************************************************
* Private Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* The heap may be statically allocated by defining CONFIG_HEAP_BASE and
* CONFIG_HEAP_SIZE. If these are not defined, then this function will be
* called to dynamically set aside the heap region.
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_heapbase;
*heap_size = (IMX_SDRAM_VSECTION + CONFIG_DRAM_SIZE) - g_heapbase;
}
/****************************************************************************
* Name: up_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
/* If a bootloader that copies us to DRAM, but not to the beginning of DRAM,
* then recover that memory by adding another memory region.
*/
#if !defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_COPYTORAM)
# if (CONFIG_DRAM_NUTTXENTRY & 0xffff0000) != CONFIG_DRAM_VSTART
uint32 start = CONFIG_DRAM_VSTART + 0x1000;
uint32 end = (CONFIG_DRAM_NUTTXENTRY & 0xffff0000);
mm_addregion((FAR void*)start, end - start);
# endif
#endif
/* Check for any additional memory regions */
#if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
#endif
}
#endif
arch/arm/src/imx/imx_boot.c
+184
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@@ -0,0 +1,184 @@
/************************************************************************************
* arch/arm/src/imx/imx_boot.c
* arch/arm/src/chip/imx_boot.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "up_internal.h"
#include "up_arch.h"
/************************************************************************************
* Private Types
************************************************************************************/
/************************************************************************************
* Private Types
************************************************************************************/
struct section_mapping_s
{
uint32 physbase; /* Physical address of the region to be mapped */
uint32 virtbase; /* Virtual address of the region to be mapped */
uint32 mmuflags; /* MMU settings for the region (e.g., cache-able) */
uint32 nsections; /* Number of mappings in the region */
};
/************************************************************************************
* Public Variables
************************************************************************************/
extern uint32 _vector_start; /* Beginning of vector block */
extern uint32 _vector_end; /* End+1 of vector block */
/************************************************************************************
* Private Variables
************************************************************************************/
static const struct section_mapping_s section_mapping[] =
{
{ IMX_PERIPHERALS_PSECTION, IMX_PERIPHERALS_VSECTION,
IMX_PERIPHERALS_MMUFLAGS, IMX_PERIPHERALS_NSECTIONS},
{ IMX_FLASH_PSECTION, IMX_FLASH_VSECTION,
IMX_FLASH_MMUFLAGS, IMX_FLASH_NSECTIONS},
};
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: up_setlevel1entry
************************************************************************************/
static inline void up_setlevel1entry(uint32 paddr, uint32 vaddr, uint32 mmuflags)
{
uint32 *pgtable = (uint32*)PGTABLE_VBASE;
uint32 index = vaddr >> 20;
/* Save the page table entry */
pgtable[index] = (paddr | mmuflags);
}
/************************************************************************************
* Name: up_setupmappings
************************************************************************************/
static void up_setupmappings(void)
{
int i, j;
for (i = 0; i < NMAPPINGS; i++)
{
uint32 sect_paddr = section_mapping[i].physbase;
uint32 sect_vaddr = section_mapping[i].virtbase;
uint32 mmuflags = section_mapping[i].mmuflags;
for (j = 0; j < section_mapping[i].nsections; j++)
{
up_setlevel1entry(sect_paddr, sect_vaddr, mmuflags);
sect_paddr += SECTION_SIZE;
sect_vaddr += SECTION_SIZE;
}
}
}
/************************************************************************************
* Name: up_copyvectorblock
************************************************************************************/
static void up_copyvectorblock(void)
{
/* There are three operational memory configurations:
*
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case:
*
* - Our vectors must be located at the beginning of FLASH and will
* also be mapped to address zero (because of the i.MX's "double map image."
* - There is nothing to be done here in this case.
*
* 2. We boot in FLASH but copy ourselves to DRAM from better performance.
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case:
*
* - Our code image is in FLASH and we boot to FLASH initially, then copy
* ourself to DRAM, and
* - DRAM will be mapped to address zero.
* - There is nothing to be done here in this case.
*
* 3. There is bootloader that copies us to DRAM, but probably not to the beginning
* of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* In this case:
*
* - DRAM will be mapped to address zero.
* - Interrupt vectors will be copied to address zero in this function.
*/
#if !defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_COPYTORAM)
uint32 *src = (uint32*)&_vector_start;
uint32 *end = (uint32*)&_vector_end;
uint32 *dest = (uint32*)VECTOR_BASE;
while (src < end)
{
*dest++ = *src++;
}
#endif
}
/************************************************************************************
* Public Functions
************************************************************************************/
void up_boot(void)
{
/* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all
* IO regions (Including the vector region).
*/
up_setupmappings();
/* Setup up vector block. _vector_start and _vector_end are exported from
* up_vector.S
*/
up_copyvectorblock();
}
arch/arm/src/imx/imx_gpio.c
+110
View File
@@ -0,0 +1,110 @@
/****************************************************************************
* arch/arm/src/imx/imx_gpio.c
* arch/arm/src/chip/imx_gpio.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "up_arch.h"
#include "imx_gpio.h"
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Funtions
****************************************************************************/
/****************************************************************************
* Name: imxgpio_configoutput
****************************************************************************/
void imxgpio_configoutput(int port, int bit, int value)
{
imxgpio_configinput(port, bit); /* Same as input except: */
imxgpio_dirout(GPIOA, 2); /* Output */
if (value)
{
imxgpio_setoutput(GPIOA, 2); /* Set output = 1 */
}
else
{
imxgpio_clroutput(GPIOA, 2); /* Set output = 0 */
}
}
/****************************************************************************
* Name: imxgpio_configinput
****************************************************************************/
void imxgpio_configinput(int port, int bit)
{
imxgpio_pullupdisable(GPIOA, 2); /* No pullup */
imxgpio_dirin(GPIOA, 2); /* Input */
imxgpio_gpiofunc(GPIOA, 2); /* Use as GPIO */
imxgpio_primaryperipheralfunc(GPIOA, 2); /* Not necessary */
imxgpio_ocrain(GPIOA, 2); /* Output AIN */
imxgpio_aoutgpio(GPIOA, 2); /* AOUT input is GPIO */
imxgpio_boutgpio(GPIOA, 2); /* BOUT input is GPIO */
}
/****************************************************************************
* Name: imxgpio_configprimary
****************************************************************************/
void imxgpio_configprimary(int port, int bit)
{
imxgpio_configinput(port, bit); /* Same as input except: */
imxgpio_peripheralfunc(GPIOA, 2); /* Use as peripheral */
imxgpio_primaryperipheralfunc(GPIOA, 2); /* Primary function*/
}
arch/arm/src/imx/imx_gpio.h
+376
View File
@@ -1,5 +1,6 @@
/************************************************************************************
* arch/arm/src/imx/imx_gpio.h
* arch/arm/src/chip/imx_gpio.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -39,6 +40,8 @@
/************************************************************************************
* Included Files
************************************************************************************/
#include "up_arch.h" /* getreg32(), putreg32() */
/************************************************************************************
* Definitions
@@ -180,3 +183,376 @@
************************************************************************************/
#endif /* __ARCH_ARM_IMX_GPIO_H */
#ifndef __ASSEMBLY__
/* Handler circular include... This file includes up_arch.h, but this file is
* included by up_arch.h (via chip.h) BEFORE getreg32 is defined.
*/
#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32)
#define __ARCH_ARM_IMX_GPIOHELPERS_H
/* Select whether the pin is an input or output */
static inline void imxgpio_dirout(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_DDIR(port));
regval |= (1 << bit);
putreg32(regval, IMX_GPIO_DDIR(port));
}
static inline void imxgpio_dirin(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_DDIR(port));
regval &= ~(1 << bit);
putreg32(regval, IMX_GPIO_DDIR(port));
}
/* Select input configuration */
static inline void imxgpio_ocrain(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_OCR1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_OCR2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_ocrbin(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_OCR1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_OCR2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (1 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_ocrcin(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_OCR1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_OCR2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (2 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_ocrodrin(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_OCR1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_OCR2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval |= (3 << shift);
putreg32(regval, regaddr);
}
/* Input configuration */
static inline void imxgpio_aoutgpio(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFA1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFA2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_aoutisr(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFA1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFA2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (1 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_aout0(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFA1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFA2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (2 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_aout1(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFA1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFA2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval |= (3 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_boutgpio(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFB1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFB2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_boutisr(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFB1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFB2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (1 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_bout0(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFB1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFB2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval &= ~(3 << shift);
regval |= (2 << shift);
putreg32(regval, regaddr);
}
static inline void imxgpio_bout1(int port, int bit)
{
uint32 regval;
uint32 regaddr;
int shift;
if (bit < 16)
{
regaddr = IMX_GPIO_ICONFB1(port);
shift = (bit << 1);
}
else
{
regaddr = IMX_GPIO_ICONFB2(port);
shift = ((bit - 16) << 1);
}
regval = getreg32(regaddr);
regval |= (3 << shift);
putreg32(regval, regaddr);
}
/* Select whether the pin is used for its GPIO function or for
* its peripheral function. Also select the primary or alternate
* peripheral function.
*/
static inline void imxgpio_gpiofunc(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_GIUS(port));
regval |= (1 << bit);
putreg32(regval, IMX_GPIO_GIUS(port));
}
static inline void imxgpio_peripheralfunc(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_GIUS(port));
regval &= ~(1 << bit);
putreg32(regval, IMX_GPIO_GIUS(port));
}
static inline void imxgpio_altperipheralfunc(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_GPR(port));
regval |= (1 << bit);
putreg32(regval, IMX_GPIO_GPR(port));
}
static inline void imxgpio_primaryperipheralfunc(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_GPR(port));
regval &= ~(1 << bit);
putreg32(regval, IMX_GPIO_GPR(port));
}
/* Enable/disable pullups */
static inline void imxgpio_pullupenable(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_PUEN(port));
regval |= (1 << bit);
putreg32(regval, IMX_GPIO_PUEN(port));
}
static inline void imxgpio_pullupdisable(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_PUEN(port));
regval &= ~(1 << bit);
putreg32(regval, IMX_GPIO_PUEN(port));
}
static inline void imxgpio_setoutput(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_DR(port));
regval |= (1 << bit);
putreg32(regval, IMX_GPIO_DR(port));
}
static inline void imxgpio_clroutput(int port, int bit)
{
uint32 regval = getreg32(IMX_GPIO_DR(port));
regval &= ~(1 << bit);
putreg32(regval, IMX_GPIO_DR(port));
}
/* Useful functions for normal configurations */
extern void imxgpio_configreset(int port, int bit);
extern void imxgpio_configoutput(int port, int bit, int value);
extern void imxgpio_configinput(int port, int bit);
extern void imxgpio_configprimary(int port, int bit);
#endif
#endif /* __ARCH_ARM_IMX_GPIOHELPERS_H */
arch/arm/src/imx/imx_memorymap.h
+69 -21
View File
@@ -74,14 +74,62 @@
/* Virtual Memory Map ***************************************************************/
/* We use a simple identity mapping. The MMU is really only used to control the
* D-cache
/* There are three operational memory configurations:
*
* 1. We execute in place in FLASH (CONFIG_BOOT_RUNFROMFLASH=y). In this case:
*
* - Our vectors must be located at the beginning of FLASH and will
* also be mapped to address zero (because of the i.MX's "double map image."
* - All vector addresses are FLASH absolute addresses,
* - DRAM cannot reside at address zero,
* - Vectors at address zero (CR_V is not set),
* - The boot logic must configure SDRAM and,
* - The .data section in RAM must be initialized.
*
* 2. We boot in FLASH but copy ourselves to DRAM from better performance.
* (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=y). In this case:
*
* - Our code image is in FLASH and we boot to FLASH initially, then copy
* ourself to DRAM,
* - DRAM will be mapped to address zero,
* - The RESET vector is a FLASH absolute address,
* - All other vectors are absulte and reference functions in the final mapped SDRAM address
* - Vectors at address zero (CR_V is not set), and
* - The boot logic must configure SDRAM.
*
* 3. There is bootloader that copies us to DRAM, but probably not to the beginning
* of DRAM (say to 0x0900:0000) (CONFIG_BOOT_RUNFROMFLASH=n && CONFIG_BOOT_COPYTORAM=n).
* In this case:
*
* - DRAM will be mapped to address zero,
* - Interrupt vectors will be copied to address zero,
* - Memory between the end of the vector area (say 0x0800:0400) and the beginning
* of the page table (0x0900:0000) will be given to the memory manager as a second
* memory region,
* - All vectors are absulte and reference functions in the final mapped SDRAM address
* - Vectors at address zero (CR_V is not set), and
* - We must assume that the bootloader has configured SDRAM.
*/
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Use the identity mapping */
# define IMX_SDRAM_VSECTION 0x08000000 /* -(+CONFIG_DRAM_SIZE) */
#else
/* Map SDRAM to address zero */
# define IMX_SDRAM_VSECTION 0x00000000 /* -(+CONFIG_DRAM_SIZE) */
#endif
/* We use a identity mapping for other regions */
#define IMX_PERIPHERALS_VSECTION 0x00200000 /* -0x002fffff 1Mb */
#define IMX_SDRAM_VSECTION 0x08000000 /* -(+CONFIG_DRAM_SIZE) */
#define IMX_FLASH_VSECTION 0x10000000 /* -(+CONFIG_FLASH_SIZE) */
/* In any event, the vector base address is 0x0000:0000 */
#define VECTOR_BASE 0x00000000
/* Peripheral Register Offsets ******************************************************/
#define IMX_AIPI1_OFFSET 0x00000000 /* -0x00000fff AIPI1 4Kb */
@@ -161,7 +209,11 @@
* This offset reserves space for the MMU page cache.
*/
#define NUTTX_START_VADDR (IMX_SDRAM_VSECTION+PGTABLE_SIZE)
#define NUTTX_START_VADDR ((CONFIG_DRAM_NUTTXENTRY & 0xfff00000) | PGTABLE_SIZE)
#if NUTTX_START_VADDR != CONFIG_DRAM_NUTTXENTRY
# error "CONFIG_DRAM_NUTTXENTRY does not have correct offset for page table"
#endif
/* Section MMU Flags */
@@ -174,28 +226,24 @@
* We will reuse this memory for coarse page tables as follows:
*/
#define PGTABLE_BASE_PBASE IMX_SDRAM0_PSECTION
#define PGTABLE_SDRAM_PBASE PGTABLE_BASE_PBASE
#define PGTABLE_COARSE_BASE_PBASE (PGTABLE_BASE_PBASE+0x00000800)
#define PGTABLE_COARSE_END_PBASE (PGTABLE_BASE_PBASE+0x00003000)
#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_BASE_PBASE+0x00003000)
#define PGTABLE_END_PBASE (PGTABLE_BASE_PBASE+0x00004000)
#define PGTABLE_PBASE IMX_SDRAM0_PSECTION
#define PGTABLE_SDRAM_PBASE PGTABLE_PBASE
#define PGTABLE_COARSE_PBASE (PGTABLE_PBASE+0x00000800)
#define PGTABLE_COARSE_PEND (PGTABLE_PBASE+0x00003000)
#define PTTABLE_PERIPHERALS_PBASE (PGTABLE_PBASE+0x00003000)
#define PGTABLE_PEND (PGTABLE_PBASE+0x00004000)
#define PGTABLE_BASE_VBASE IMX_SDRAM_VSECTION
#define PGTABLE_SDRAM_VBASE PGTABLE_BASE_VBASE
#define PGTABLE_COARSE_BASE_VBASE (PGTABLE_BASE_VBASE+0x00000800)
#define PGTABLE_COARSE_END_VBASE (PGTABLE_BASE_VBASE+0x00003000)
#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_BASE_VBASE+0x00003000)
#define PGTABLE_END_VBASE (PGTABLE_BASE_VBASE+0x00004000)
#define PGTABLE_VBASE IMX_SDRAM_VSECTION
#define PGTABLE_SDRAM_VBASE PGTABLE_VBASE
#define PGTABLE_COARSE_VBASE (PGTABLE_VBASE+0x00000800)
#define PGTABLE_COARSE_VEND (PGTABLE_VBASE+0x00003000)
#define PTTABLE_PERIPHERALS_VBASE (PGTABLE_VBASE+0x00003000)
#define PGTABLE_VEND (PGTABLE_VBASE+0x00004000)
#define PGTBALE_COARSE_TABLE_SIZE (4*256)
#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_END_VBASE-PGTABLE_COARSE_BASE_VBASE)
#define PGTABLE_COARSE_ALLOC (PGTABLE_COARSE_VEND-PGTABLE_COARSE_VBASE)
#define PGTABLE_NCOARSE_TABLES (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
/* This is the base address of the interrupt vectors on the ARM926 */
#define VECTOR_BASE IMX_VECTOR_VBASE
/************************************************************************************
* Inline Functions
************************************************************************************/
arch/z16/src/common/up_internal.h
+1 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* common/up_internal.h
*
* Copyright (C) 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
configs/mx1ads/include/board.h
+14
View File
@@ -48,6 +48,20 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* LED definitions ******************************************************************/
/* The MX1ADS has only one usable LED: Port A, bit 2 */
/* ON OFF */
#define LED_STARTED 0 /* OFF OFF */
#define LED_HEAPALLOCATE 1 /* OFF OFF */
#define LED_IRQSENABLED 2 /* OFF OFF */
#define LED_STACKCREATED 3 /* OFF OFF */
#define LED_INIRQ 4 /* ON OFF */
#define LED_SIGNAL 5 /* ON OFF */
#define LED_ASSERTION 6 /* ON OFF */
#define LED_PANIC 7 /* ON OFF */
/************************************************************************************
* Inline Functions
configs/mx1ads/ostest/Make.defs
+1 -1
View File
@@ -57,7 +57,7 @@ endif
ifeq ($(ARCHCCMAJOR),4)
ARCHCPUFLAGS = -mtune=arm9tdmi -march=armv4t -msoft-float -fno-builtin
else
ARCHCPUFLAGS = -mapcs-32 -mtune=arm9tdmi -march=armv5te -msoft-float -fno-builtin
ARCHCPUFLAGS = -mapcs-32 -mtune=arm9tdmi -march=armv4t -msoft-float -fno-builtin
endif
ARCHPICFLAGS = -fpic
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
configs/mx1ads/ostest/defconfig
+6 -3
View File
@@ -50,6 +50,8 @@
# CONFIG_DRAM_SIZE - Describes the installed DRAM.
# CONFIG_DRAM_START - The start address of DRAM (physical)
# CONFIG_DRAM_VSTART - The startaddress of DRAM (virtual)
# CONFIG_ARCH_LOWVECTORS - Leave ARM interrupt vectors at 0x0000:0000
# instead of moving to 0xffff:0000
# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
# stack. If defined, this symbol is the size of the interrupt
# stack in bytes. If not defined, the user task stacks will be
@@ -64,9 +66,10 @@ CONFIG_ARCH_BOARD=mx1ads
CONFIG_ARCH_BOARD_MX1ADS=y
CONFIG_BOARD_LOOPSPERMSEC=16945
CONFIG_DRAM_SIZE=0x01000000
CONFIG_DRAM_START=0x01000000
CONFIG_DRAM_START=0x08000000
CONFIG_DRAM_VSTART=0x00000000
CONFIG_DRAM_NUTTXENTRY=0x01008000
CONFIG_DRAM_NUTTXENTRY=0x01004000
CONFIG_ARCH_LOWVECTORS=y
CONFIG_ARCH_INTERRUPTSTACK=0
CONFIG_ARCH_STACKDUMP=y
@@ -158,7 +161,7 @@ CONFIG_HAVE_LIBM=n
CONFIG_EXAMPLE=ostest
CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_MM_REGIONS=1
CONFIG_MM_REGIONS=2
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_INSTRUMENTATION=n
configs/mx1ads/src/up_leds.c
+38 -3
View File
@@ -54,6 +54,22 @@
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx_ledon
****************************************************************************/
static inline void imx_ledon(void)
{
}
/****************************************************************************
* Name: imx_ledoff
****************************************************************************/
static void imx_ledoff(void)
{
}
/****************************************************************************
* Public Funtions
****************************************************************************/
@@ -65,7 +81,9 @@
#ifdef CONFIG_ARCH_LEDS
void up_ledinit(void)
{
# error "Missing implementation"
/* Configure Port A, Bit 2 as an output, initial value=1 */
imxgpio_configoutput(GPIOA, 2, 1);
}
/****************************************************************************
@@ -74,7 +92,23 @@ void up_ledinit(void)
void up_ledon(int led)
{
# error "Missing implementation"
switch (led)
{
case LED_STARTED:
case LED_HEAPALLOCATE:
case LED_IRQSENABLED:
case LED_STACKCREATED:
imxgpio_setoutput(GPIOA, 2); /* Port A, Bit 2 = 1 */
break;
case LED_INIRQ:
case LED_SIGNAL:
case LED_ASSERTION:
case LED_PANIC:
default:
imxgpio_clroutput(GPIOA, 2); /* Port A, Bit 2 = 0 */
break;
}
}
/****************************************************************************
@@ -83,6 +117,7 @@ void up_ledon(int led)
void up_ledoff(int led)
{
# error "Missing implementation"
imxgpio_clroutput(GPIOA, 2); /* Port A, Bit 2 = 0 */
}
#endif /* CONFIG_ARCH_LEDS */