Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-06 00:14:22 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Correct some typos int he MPADDRCS register address definitions

Browse Source
This commit is contained in:
Gregory Nutt
2013-08-02 12:06:11 -06:00
parent 244e85a4fa
commit adb065593d
6 changed files with 76 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/sama5d3x-ek/README.txt
+59
View File
@@ -843,11 +843,64 @@ Configurations
4. This configuration has support for NSH built-in applications enabled.
However, no built-in applications are selected in the base configuration.
5. SDRAM support can be enabled by adding the following to your NuttX
configuration file:
CONFIG_SAMA5_MPDDRC=y : Enable the DDR controller
CONFIG_SAMA5_DDRCS=y : Tell the system that DRAM is at the DDR CS
CONFIG_SAMA5_DDRCS_SIZE=268435456 : 2Gb DRAM -> 256GB
CONFIG_SAMA5_DDRCS_LPDDR2=y : Its DDR2
CONFIG_SAMA5_MT47H128M16RT=y : This is the type of DDR2
Now that you have SDRAM enabled, what are you going to do with it? One
thing you can is add it to the heap
CONFIG_SAMA5_DDRCS_HEAP=y : Add the SDRAM to the heap
CONFIG_MM_REGIONS=2 : Two memory regions: ISRAM and SDRAM
Another thing you could do is to enable the RAM test built-in
application:
6. You can enable the NuttX RAM test that may be used to verify the
external SDAM. To do this, keep the SDRAM out of the heap so that
it can be tested without crashing programs using the memory:
CONFIG_SAMA5_DDRCS_HEAP=n : Don't add the SDRAM to the heap
CONFIG_MM_REGIONS=1 : One memory regions: ISRAM
In this configuration, the SDRAM is not added to heap and so is not
excessible to the applications. So the RAM test can be freely
executed against the SRAM memory beginning at address 0x2000:0000
(DDR CS):
nsh> ramtest -h
Usage: <noname> [-w|h|b] <hex-address> <decimal-size>
Where:
<hex-address> starting address of the test.
<decimal-size> number of memory locations (in bytes).
-w Sets the width of a memory location to 32-bits.
-h Sets the width of a memory location to 16-bits (default).
-b Sets the width of a memory location to 8-bits.
To test the entire external 256MB SRAM:
nsh> ramtest 20000000 268435456
RAMTest: Marching ones: 60000000 268435456
RAMTest: Marching zeroes: 60000000 268435456
RAMTest: Pattern test: 60000000 268435456 55555555 aaaaaaaa
RAMTest: Pattern test: 60000000 268435456 66666666 99999999
RAMTest: Pattern test: 60000000 268435456 33333333 cccccccc
RAMTest: Address-in-address test: 60000000 268435456
STATUS:
2013-7-19: This configuration (as do the others) run at 396MHz.
The SAMA5D3 can run at 536MHz. I still need to figure out the
PLL settings to get that speed.
If the CPU speed changes, then so must the NOR and SDRAM
initialization!
2013-7-31: I have been unable to execute this configuration from NOR
FLASH by closing the BMS jumper (J9). As far as I can tell, this
jumper does nothing on my board??? I have been using the norboot
@@ -860,6 +913,9 @@ Configurations
That configuration runs out of internal SRAM and, as a result, this
configuration needs to be recalibrated.
2013-8-31: SDRAM configuration and RAM test usage are documented,
but untested.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
@@ -907,6 +963,9 @@ Configurations
The SAMA5D3 can run at 536MHz. I still need to figure out the
PLL settings to get that speed.
If the CPU speed changes, then so must the NOR and SDRAM
initialization!
2013-7-30: I have been unable to execute this configuration from NOR
FLASH by closing the BMS jumper (J9). As far as I can tell, this
jumper does nothing on my board??? I have been using the norboot
configs/sama5d3x-ek/norboot/defconfig
+2 -2
View File
@@ -20,7 +20,7 @@ CONFIG_WINDOWS_CYGWIN=y
#
# Build Configuration
#
CONFIG_APPS_DIR="../apps"
# CONFIG_APPS_DIR="../apps"
# CONFIG_BUILD_2PASS is not set
#
@@ -167,7 +167,6 @@ CONFIG_SAMA5_USART1=y
#
# External Memory Configuration
#
# CONFIG_SAMA5_DDRCS is not set
CONFIG_SAMA5_EBICS0=y
CONFIG_SAMA5_EBICS0_SIZE=134217728
# CONFIG_SAMA5_EBICS0_SRAM is not set
@@ -248,6 +247,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y
# Board-Specific Options
#
CONFIG_SAMA5_NOR_MAIN=y
# CONFIG_SAMA5_NOR_START is not set
#
# RTOS Features
configs/sama5d3x-ek/nsh/defconfig
-1
View File
@@ -167,7 +167,6 @@ CONFIG_SAMA5_USART1=y
#
# External Memory Configuration
#
# CONFIG_SAMA5_DDRCS is not set
CONFIG_SAMA5_EBICS0=y
CONFIG_SAMA5_EBICS0_SIZE=134217728
# CONFIG_SAMA5_EBICS0_SRAM is not set
configs/sama5d3x-ek/ostest/defconfig
-1
View File
@@ -167,7 +167,6 @@ CONFIG_SAMA5_USART1=y
#
# External Memory Configuration
#
# CONFIG_SAMA5_DDRCS is not set
CONFIG_SAMA5_EBICS0=y
CONFIG_SAMA5_EBICS0_SIZE=134217728
# CONFIG_SAMA5_EBICS0_SRAM is not set
configs/sama5d3x-ek/src/sam_sdram.c
+8
View File
@@ -124,6 +124,14 @@ static inline void sam_sdram_delay(unsigned int loops)
* Description:
* Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
*
* Configures DDR2 (MT47H128M16RT 128MB or, optionally, MT47H64M16HR)
*
* Per the SAMA5D3x-EK User guide: "Two SDRAM/DDR2 used as main system memory.
* MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board provides up to 2 Gb on-
* board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates with
* up to 166 MHz."
*
* From the Atmel Code Example:
* MT47H64M16HR : 8 Meg x 16 x 8 banks
* Refresh count: 8K
* Row address: A[12:0] (8K)
configs/sama5d3x-ek/src/sama5d3x-ek.h
+7 -1
View File
@@ -112,8 +112,14 @@
* Name: board_sdram_config
*
* Description:
* Configures DDR2 (MT47H128M16RT 128MB / MT47H64M16HR)
* Configures DDR2 (MT47H128M16RT 128MB or, optionally, MT47H64M16HR)
*
* Per the SAMA5D3x-EK User guide: "Two SDRAM/DDR2 used as main system memory.
* MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board provides up to 2 Gb on-
* board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates with
* up to 166 MHz."
*
* From the Atmel Code Example:
* MT47H64M16HR : 8 Meg x 16 x 8 banks
* Refresh count: 8K
* Row address: A[12:0] (8K)