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arch/arm/src/tiva/hardware: Fix some naming used in comments.

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This commit is contained in:
Gregory Nutt
2019-01-13 10:43:20 -06:00
parent 68584aa6eb
commit ac0a6ebdd9
7 changed files with 82 additions and 83 deletions
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arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
+10 -10
View File
@@ -80,13 +80,13 @@
/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI2_REFSYS_REFSYSCTL0 */
/* TIVA_ADI2_REFSYS_REFSYSCTL0 */
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT (0) /* Bit 0-4 */
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_MASK (15 << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
# define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF(n) ((uint32_t)(n) << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL0 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL0 */
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
@@ -95,7 +95,7 @@
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL1 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL1 */
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
@@ -104,13 +104,13 @@
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL2 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL2 */
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_MASK (7 << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL3 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL3 */
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
@@ -126,7 +126,7 @@
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_MASK (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL4 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL4 */
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN (1 << 0) /* Bit 0 */
#define ADI2_REFSYS_SOCLDOCTL4_BIAS_DIS (1 << 1) /* Bit 1 */
@@ -137,7 +137,7 @@
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_MASK (3 << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL5 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL5 */
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_MASK (7 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
@@ -148,7 +148,7 @@
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON (4 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
#define ADI2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN (1 << 3) /* Bit 3 */
/* ADI2_REFSYS_HPOSCCTL0 */
/* TIVA_ADI2_REFSYS_HPOSCCTL0 */
#define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS (1 << 0) /* Bit 0 */
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ (0)
@@ -172,7 +172,7 @@
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
#define ADI2_REFSYS_HPOSCCTL0_FILTER_EN (1 << 7) /* Bit 7 */
/* ADI2_REFSYS_HPOSCCTL1 */
/* TIVA_ADI2_REFSYS_HPOSCCTL1 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_MASK (15 << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
@@ -180,7 +180,7 @@
#define ADI2_REFSYS_HPOSCCTL1_PWRDET_EN (1 << 4) /* Bit 4 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_DIS (1 << 5) /* Bit 5 */
/* ADI2_REFSYS_HPOSCCTL2 */
/* TIVA_ADI2_REFSYS_HPOSCCTL2 */
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK (15 << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
+11 -11
View File
@@ -82,13 +82,13 @@
/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI3_REFSYS_SPARE0 */
/* TIVA_ADI3_REFSYS_SPARE0 */
#define ADI3_REFSYS_SPARE0_SPARE0_SHIFT (0) /* Bits 0-7: Do not change */
#define ADI3_REFSYS_SPARE0_SPARE0_MASK (0xff << ADI3_REFSYS_SPARE0_SPARE0_SHIFT)
# define ADI3_REFSYS_SPARE0_SPARE0(n) ((uint32_t)(n) << ADI3_REFSYS_SPARE0_SPARE0_SHIFT)
/* ADI3_REFSYS_REFSYSCTL0 */
/* TIVA_ADI3_REFSYS_REFSYSCTL0 */
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT (0) /* Bits 0-7 */
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_MASK (0xff << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
@@ -103,7 +103,7 @@
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP (0x40 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT (0x80 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
/* ADI3_REFSYS_REFSYSCTL1 */
/* TIVA_ADI3_REFSYS_REFSYSCTL1 */
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT (0) /* Bits 0-1 */
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_MASK (3 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
@@ -148,13 +148,13 @@
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 (30 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
/* ADI3_REFSYS_REFSYSCTL2 */
/* TIVA_ADI3_REFSYS_REFSYSCTL2 */
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT (0) /* Bits 0-1 */
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_MASK (3 << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
# define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
/* ADI3_REFSYS_REFSYSCTL3 */
/* TIVA_ADI3_REFSYS_REFSYSCTL3 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT (0) /* Bits 0-5 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK (0x3f << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
@@ -162,7 +162,7 @@
#define ADI3_REFSYS_REFSYSCTL3_VTEMP_EN (1 << 6) /* Bit 6 */
#define ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN (1 << 7) /* Bit 7 */
/* ADI3_REFSYS_DCDCCTL0 */
/* TIVA_ADI3_REFSYS_DCDCCTL0 */
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT (0) /* Bits 0-4: Set the VDDR voltage */
/* Proprietary encoding */
@@ -180,7 +180,7 @@
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MAX (3 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 15mA */
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MIN (4 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 5mA */
/* ADI3_REFSYS_DCDCCTL1 */
/* TIVA_ADI3_REFSYS_DCDCCTL1 */
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT (0) /* Bits 0-4: Set the min VDDR voltage threshold during sleep mode */
/* Proprietary encoding */
@@ -201,7 +201,7 @@
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p6 (2 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.6x */
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEC0p7 (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Decrease GLDO bias by 0.7x */
/* ADI3_REFSYS_DCDCCTL2 */
/* TIVA_ADI3_REFSYS_DCDCCTL2 */
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT (0) /* Bits 0-3: Select signal for test bus, one hot */
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_MASK (15 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
@@ -215,9 +215,9 @@
#define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */
#define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */
/* ADI3_REFSYS_DCDCCTL3 */
/* TIVA_ADI3_REFSYS_DCDCCTL3 */
/* ADI3_REFSYS_DCDCCTL4 */
/* TIVA_ADI3_REFSYS_DCDCCTL4 */
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT (0) /* Bits 0-2 */
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
@@ -229,7 +229,7 @@
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
# define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
/* ADI3_REFSYS_DCDCCTL5 */
/* TIVA_ADI3_REFSYS_DCDCCTL5 */
#define ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT (0) /* Bits 0-2 */
#define ADI3_REFSYS_DCDCCTL5_IPEAK_MASK (7 << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h
+12 -12
View File
@@ -84,7 +84,7 @@
/* AON RTC Bitfield Definitions *************************************************************************************/
/* AON_RTC_CTL */
/* TIVA_AON_RTC_CTL */
#define AON_RTC_CTL_EN (1 << 0) /* Bit 0: Enable RTC counter */
#define AON_RTC_CTL_RTC_UPD_EN (1 << 1) /* Bit 1: Enable 16-KHz RTC_UPD output */
@@ -113,17 +113,17 @@
# define AON_RTC_CTL_COMB_EV_MASK_CH1 (2 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* Use Chan 1 delayed event to combine */
# define AON_RTC_CTL_COMB_EV_MASK_CH2 (4 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* Use Chan 2 delayed event to combine */
/* AON_RTC_EVFLAGS */
/* TIVA_AON_RTC_EVFLAGS */
#define AON_RTC_EVFLAGS_CH0 (1 << 0) /* Bit 0: Channel 0 event flag */
#define AON_RTC_EVFLAGS_CH1 (1 << 8) /* Bit 8: Channel 1 event flag */
#define AON_RTC_EVFLAGS_CH2 (1 << 16) /* Bit 16: Channel 2 event flag */
/* AON_RTC_SEC (32-bit value, units of seconds) */
/* AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */
/* AON_RTC_SUBSECINC (32-bit value) */
/* TIVA_AON_RTC_SEC (32-bit value, units of seconds) */
/* TIVA_AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */
/* TIVA_AON_RTC_SUBSECINC (32-bit value) */
/* AON_RTC_CHCTL */
/* TIVA_AON_RTC_CHCTL */
#define AON_RTC_CHCTL_CH0_EN (1 << 0) /* Bit 0: RTC Channel 0 enable */
#define AON_RTC_CHCTL_CH1_EN (1 << 8) /* Bit 8: RTC Channel 1 enable */
@@ -133,19 +133,19 @@
#define AON_RTC_CHCTL_CH2_EN (1 << 16) /* Bit 16: RTC Channel 2 Enable */
#define AON_RTC_CHCTL_CH2_CONT_EN (1 << 18) /* Bit 18: Enable Channel 2 Continuous Operation */
/* AON_RTC_CH0CMP (32-bit value) */
/* AON_RTC_CH1CMP (32-bit value) */
/* AON_RTC_CH2CMP (32-bit value) */
/* AON_RTC_CH2CMPINC (32-bit value) */
/* TIVA_AON_RTC_CH0CMP (32-bit value) */
/* TIVA_AON_RTC_CH1CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMPINC (32-bit value) */
/* AON_RTC_CH1CAPT */
/* TIVA_AON_RTC_CH1CAPT */
#define AON_RTC_CH1CAPT_SUBSEC_SHIFT (0) /* Value of SUBSEC.VALUE bits 31:16 at capture time */
#define AON_RTC_CH1CAPT_SUBSEC_MASK (0xffff << AON_RTC_CH1CAPT_SUBSEC_SHIFT)
#define AON_RTC_CH1CAPT_SEC_SHIFT (16) /* Bits 16-31: Value of SEC.VALUE bits 15:0 at capture time */
#define AON_RTC_CH1CAPT_SEC_MASK (0xffff << AON_RTC_CH1CAPT_SEC_SHIFT)
/* AON_RTC_SYNC */
/* TIVA_AON_RTC_SYNC */
#define AON_RTC_SYNC_WBUSY (1 << 0) /* Bit 0:
* Read: Outstanding MCU/AON write request
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
+10 -10
View File
@@ -80,13 +80,13 @@
/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI2_REFSYS_REFSYSCTL0 */
/* TIVA_ADI2_REFSYS_REFSYSCTL0 */
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT (0) /* Bit 0-4 */
#define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_MASK (15 << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
# define ADI2_REFSYS_REFSYSCTL0_TRIM_IREF(n) ((uint32_t)(n) << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL0 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL0 */
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT)
@@ -95,7 +95,7 @@
#define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL1 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL1 */
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)
@@ -104,13 +104,13 @@
#define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_MASK (15 << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL2 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL2 */
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_MASK (7 << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL3 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL3 */
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_MASK (7 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_SHIFT)
@@ -126,7 +126,7 @@
#define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_MASK (3 << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL4 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL4 */
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN (1 << 0) /* Bit 0 */
#define ADI2_REFSYS_SOCLDOCTL4_BIAS_DIS (1 << 1) /* Bit 1 */
@@ -137,7 +137,7 @@
#define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_MASK (3 << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
# define ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN(n) ((uint32_t)(n) << ADI2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_SHIFT)
/* ADI2_REFSYS_SOCLDOCTL5 */
/* TIVA_ADI2_REFSYS_SOCLDOCTL5 */
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT (0) /* Bits 0-2 */
#define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_MASK (7 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
@@ -148,7 +148,7 @@
# define ADI2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON (4 << ADI2_REFSYS_SOCLDOCTL5_TESTSEL_SHIFT)
#define ADI2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN (1 << 3) /* Bit 3 */
/* ADI2_REFSYS_HPOSCCTL0 */
/* TIVA_ADI2_REFSYS_HPOSCCTL0 */
#define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS (1 << 0) /* Bit 0 */
# define ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ (0)
@@ -172,7 +172,7 @@
# define ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 (3 << ADI2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_SHIFT)
#define ADI2_REFSYS_HPOSCCTL0_FILTER_EN (1 << 7) /* Bit 7 */
/* ADI2_REFSYS_HPOSCCTL1 */
/* TIVA_ADI2_REFSYS_HPOSCCTL1 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_MASK (15 << ADI2_REFSYS_HPOSCCTL1_BIAS_RES_SET_SHIFT)
@@ -180,7 +180,7 @@
#define ADI2_REFSYS_HPOSCCTL1_PWRDET_EN (1 << 4) /* Bit 4 */
#define ADI2_REFSYS_HPOSCCTL1_BIAS_DIS (1 << 5) /* Bit 5 */
/* ADI2_REFSYS_HPOSCCTL2 */
/* TIVA_ADI2_REFSYS_HPOSCCTL2 */
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT (0) /* Bits 0-3 */
#define ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_MASK (15 << ADI2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_SHIFT)
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h
+13 -13
View File
@@ -88,7 +88,7 @@
/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI3_REFSYS_ATESTCTL1 */
/* TIVA_ADI3_REFSYS_ATESTCTL1 */
#define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT (0) /* Bits 0-2 */
#define ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_MASK (7 << ADI3_REFSYS_ATESTCTL1_ATEST1_CTL_SHIFT)
@@ -104,7 +104,7 @@
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 (1 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT))
# define ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 (2 << ADI3_REFSYS_ATESTCTL1_ATEST0_CTL_SHIFT))
/* ADI3_REFSYS_REFSYSCTL0 */
/* TIVA_ADI3_REFSYS_REFSYSCTL0 */
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT (0) /* Bits 0-7 */
#define ADI3_REFSYS_REFSYSCTL0_TESTCTL_MASK (0xff << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
@@ -119,7 +119,7 @@
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP (0x40 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
# define ADI3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT (0x80 << ADI3_REFSYS_REFSYSCTL0_TESTCTL_SHIFT)
/* ADI3_REFSYS_REFSYSCTL1 */
/* TIVA_ADI3_REFSYS_REFSYSCTL1 */
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT (0) /* Bits 0-1 */
#define ADI3_REFSYS_REFSYSCTL1_TESTCTL_MASK (3 << ADI3_REFSYS_REFSYSCTL1_TESTCTL_SHIFT)
@@ -164,7 +164,7 @@
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 (30 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
# define ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 (31 << ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT)
/* ADI3_REFSYS_REFSYSCTL2 */
/* TIVA_ADI3_REFSYS_REFSYSCTL2 */
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT (0) /* Bits 0-1 */
#define ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_MASK (3 << ADI3_REFSYS_REFSYSCTL2_TRIM_TSENSE_SHIFT)
@@ -174,7 +174,7 @@
#define ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_MASK (15 << ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT)
# define ADI3_REFSYS_REFSYSCTL2_TRIM_VREF(n) ((uint32_t)(n) << ADI3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT)
/* ADI3_REFSYS_REFSYSCTL3 */
/* TIVA_ADI3_REFSYS_REFSYSCTL3 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT (0) /* Bits 0-5 */
#define ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK (0x3f << ADI3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT)
@@ -182,7 +182,7 @@
#define ADI3_REFSYS_REFSYSCTL3_VTEMP_EN (1 << 6) /* Bit 6 */
#define ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN (1 << 7) /* Bit 7 */
/* ADI3_REFSYS_DCDCCTL0 */
/* TIVA_ADI3_REFSYS_DCDCCTL0 */
#define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT (0) /* Bits 0-4: Set the VDDR voltage */
/* Proprietary encoding */
@@ -200,7 +200,7 @@
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MAX (3 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 15mA */
# define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MIN (4 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) /* Max 5mA */
/* ADI3_REFSYS_DCDCCTL1 */
/* TIVA_ADI3_REFSYS_DCDCCTL1 */
#define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT (0) /* Bits 0-4: Set the min VDDR voltage threshold during sleep mode */
/* Proprietary encoding */
@@ -221,7 +221,7 @@
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_INC1p6 (2 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Increase GLDO bias by 1.6x */
# define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_DEC0p7 (3 << ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT) /* Decrease GLDO bias by 0.7x */
/* ADI3_REFSYS_DCDCCTL2 */
/* TIVA_ADI3_REFSYS_DCDCCTL2 */
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT (0) /* Bits 0-3: Select signal for test bus, one hot */
#define ADI3_REFSYS_DCDCCTL2_TESTSEL_MASK (15 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT)
@@ -235,9 +235,9 @@
#define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */
#define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */
/* ADI3_REFSYS_DCDCCTL3 */
/* TIVA_ADI3_REFSYS_DCDCCTL3 */
/* ADI3_REFSYS_DCDCCTL4 */
/* TIVA_ADI3_REFSYS_DCDCCTL4 */
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT (0) /* Bits 0-2 */
#define ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_MASK (7 << ADI3_REFSYS_DCDCCTL4_HIGH_EN_SEL_SHIFT)
@@ -249,7 +249,7 @@
#define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_MASK (3 << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
# define ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM(n) ((uint32_t)(n) << ADI3_REFSYS_DCDCCTL4_DEADTIME_TRIM_SHIFT)
/* ADI3_REFSYS_DCDCCTL5 */
/* TIVA_ADI3_REFSYS_DCDCCTL5 */
#define ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT (0) /* Bits 0-2 */
#define ADI3_REFSYS_DCDCCTL5_IPEAK_MASK (7 << ADI3_REFSYS_DCDCCTL5_IPEAK_SHIFT)
@@ -268,7 +268,7 @@
#define ADI3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP (1 << 5) /* Bit 5: Offset compensation signal */
#define ADI3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN (1 << 6) /* Bit 6: Activate the backup circuit */
/* ADI3_REFSYS_CTL_RECHARGE_CMP0 */
/* TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP0 */
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT (0) /* Bits 0-3: Trim ref level of recharge */
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_MASK (15 << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
@@ -277,7 +277,7 @@
# define ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_100PCT (0 << ADI3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_SHIFT)
#define ADI3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE (1 << 4) /* Bit 4: Enable 32 kHz SCLK_LF to recharge comparator */
/* ADI3_REFSYS_CTL_RECHARGE_CMP1 */
/* TIVA_ADI3_REFSYS_CTL_RECHARGE_CMP1 */
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT (0) /* Bis 0-4: Trim offset of Recharge comparator */
#define ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_MASK (31 << ADI3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_SHIFT)
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_pmctl.h
+12 -13
View File
@@ -84,7 +84,7 @@
/* AON PMCTL Bitfield Definitions ***********************************************************************************/
/* AON_PMCTL_AUXSCECLK */
/* TIVA_AON_PMCTL_AUXSCECLK */
#define AON_PMCTL_AUXSCECLK_SRC (1 << 0) /* Bit 0: Clock source for AUX dmaon in active mode */
# define AON_PMCTL_AUXSCECLK_SCLK_HFDIV2 (0) /* HF Clock divided by 2 (SCLK_HFDIV2) */
@@ -93,7 +93,7 @@
# define AON_PMCTL_AUXSCECLK_PD_NO_CLOCK (0) /* No clock */
# define AON_PMCTL_AUXSCECLK_PD_SCLK_LF AON_PMCTL_AUXSCECLK_PD_SRC /* LF clock (SCLK_LF) */
/* AON_PMCTL_RAMCFG */
/* TIVA_AON_PMCTL_RAMCFG */
#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT (0) /* Bits 0-3: Select banks for retention during MCU
* bus doman power off */
@@ -110,7 +110,7 @@
#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN (1 << 16) /* Bit 16 */
#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF (1 << 17) /* Bit 17 */
/* AON_PMCTL_PWRCTL */
/* TIVA_AON_PMCTL_PWRCTL */
#define AON_PMCTL_PWRCTL_DCDC_EN (1 << 0) /* Bit 0: Select to use DCDC or GLC0 during recharge of VDDR */
# define AON_PMCTL_PWRCTL_DCDC_EN_GLD0 (0) /* Use GLDO for recharge of VDDR */
@@ -122,17 +122,17 @@
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_GLD0 (0) /* Use GLDO for regulation of VDDR in active mode */
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_DCDC AON_PMCTL_PWRCTL_DCDC_ACTIVE /* Use DCDC for regulation of VDDR in active mode */
/* AON_PMCTL_PWRSTAT */
/* TIVA_AON_PMCTL_PWRSTAT */
#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE (1 << 0) /* Bit 0: Indicates Reset Done from AUX */
#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE (1 << 1) /* Bit 1: Indicates Reset Done from AUX Bus */
#define AON_PMCTL_PWRSTAT_JTAG_PD_ON (1 << 2) /* Bit 2: JTAG power state (ON) */
/* AON_PMCTL_SHUTDOWN */
/* TIVA_AON_PMCTL_SHUTDOWN */
#define AON_PMCTL_SHUTDOWN_EN (1 << 0) /* Bit 0: Shutdown control */
/* AON_PMCTL_RECHARGECFG */
/* TIVA_AON_PMCTL_RECHARGECFG */
#define AON_PMCTL_RECHARGECFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_RECHARGECFG_PER_E_MASK (7 << AON_PMCTL_RECHARGECFG_PER_E_SHIFT)
@@ -160,8 +160,7 @@
# define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE (2 << AON_PMCTL_RECHARGECFG_MODE_SHIFT) /* Adaptive timer */
# define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR (3 << AON_PMCTL_RECHARGECFG_MODE_SHIFT) /* External recharge comparator */
/* AON_PMCTL_RECHARGESTAT */
/* TIVA_AON_PMCTL_RECHARGESTAT */
#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_SHIFT (0) /* Bits 0-15: Mzx 32KHz periods between recharge cycles and VDDR
* is still above BDDR_OK threshold. */
@@ -173,7 +172,7 @@
# define AON_PMCTL_RECHARGESTAT_VDDR_SMPL2 (4 << AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT)
# define AON_PMCTL_RECHARGESTAT_VDDR_SMPL3 (8 << AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT)
/* AON_PMCTL_OSCCFG */
/* TIVA_AON_PMCTL_OSCCFG */
#define AON_PMCTL_OSCCFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_OSCCFG_PER_E_MASK (7 << AON_PMCTL_OSCCFG_PER_E_SHIFT)
@@ -182,7 +181,7 @@
#define AON_PMCTL_OSCCFG_PER_M_MASK (31 << AON_PMCTL_OSCCFG_PER_M_SHIFT)
# define AON_PMCTL_OSCCFG_PER_M(n) ((uint32_t)(n) << AON_PMCTL_OSCCFG_PER_M_SHIFT)
/* AON_PMCTL_RESETCTL */
/* TIVA_AON_PMCTL_RESETCTL */
#define AON_PMCTL_RESETCTL_RESET_SRC_SHIFT (1) /* Bits 1-3: Shows the root cause of the last system reset */
#define AON_PMCTL_RESETCTL_RESET_SRC_MASK (7 << AON_PMCTL_RESETCTL_RESET_SRC_SHIFT)
@@ -211,14 +210,14 @@
#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR (1 << 25) /* Bit 25 */
#define AON_PMCTL_RESETCTL_SYSRESET (1 << 31) /* Bit 31: Cold reset */
/* AON_PMCTL_SLEEPCTL */
/* TIVA_AON_PMCTL_SLEEPCTL */
#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS (1 << 0) /* Bit 0: Controls the I/O pad sleep mode */
/* AON_PMCTL_JTAGCFG */
/* TIVA_AON_PMCTL_JTAGCFG */
#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON (1 << 8) /* Bit 8: Controls JTAG Power domain power state */
/* AON_PMCTL_JTAGUSERCODE (32-bit value) */
/* TIVA_AON_PMCTL_JTAGUSERCODE (32-bit value) */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_PMCTL_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_rtc.h
+14 -14
View File
@@ -88,7 +88,7 @@
/* AON RTC Bitfield Definitions *************************************************************************************/
/* AON_RTC_CTL */
/* TIVA_AON_RTC_CTL */
#define AON_RTC_CTL_EN (1 << 0) /* Bit 0: Enable RTC counter */
#define AON_RTC_CTL_RTC_UPD_EN (1 << 1) /* Bit 1: Enable 16-KHz RTC_UPD output */
@@ -117,17 +117,17 @@
# define AON_RTC_CTL_COMB_EV_MASK_CH1 (2 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* Use Chan 1 delayed event to combine */
# define AON_RTC_CTL_COMB_EV_MASK_CH2 (4 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* Use Chan 2 delayed event to combine */
/* AON_RTC_EVFLAGS */
/* TIVA_AON_RTC_EVFLAGS */
#define AON_RTC_EVFLAGS_CH0 (1 << 0) /* Bit 0: Channel 0 event flag */
#define AON_RTC_EVFLAGS_CH1 (1 << 8) /* Bit 8: Channel 1 event flag */
#define AON_RTC_EVFLAGS_CH2 (1 << 16) /* Bit 16: Channel 2 event flag */
/* AON_RTC_SEC (32-bit value, units of seconds) */
/* AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */
/* AON_RTC_SUBSECINC (32-bit value) */
/* TIVA_AON_RTC_SEC (32-bit value, units of seconds) */
/* TIVA_AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */
/* TIVA_AON_RTC_SUBSECINC (32-bit value) */
/* AON_RTC_CHCTL */
/* TIVA_AON_RTC_CHCTL */
#define AON_RTC_CHCTL_CH0_EN (1 << 0) /* Bit 0: RTC Channel 0 enable */
#define AON_RTC_CHCTL_CH1_EN (1 << 8) /* Bit 8: RTC Channel 1 enable */
@@ -137,32 +137,32 @@
#define AON_RTC_CHCTL_CH2_EN (1 << 16) /* Bit 16: RTC Channel 2 Enable */
#define AON_RTC_CHCTL_CH2_CONT_EN (1 << 18) /* Bit 18: Enable Channel 2 Continuous Operation */
/* AON_RTC_CH0CMP (32-bit value) */
/* AON_RTC_CH1CMP (32-bit value) */
/* AON_RTC_CH2CMP (32-bit value) */
/* AON_RTC_CH2CMPINC (32-bit value) */
/* TIVA_AON_RTC_CH0CMP (32-bit value) */
/* TIVA_AON_RTC_CH1CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMPINC (32-bit value) */
/* AON_RTC_CH1CAPT */
/* TIVA_AON_RTC_CH1CAPT */
#define AON_RTC_CH1CAPT_SUBSEC_SHIFT (0) /* Value of SUBSEC.VALUE bits 31:16 at capture time */
#define AON_RTC_CH1CAPT_SUBSEC_MASK (0xffff << AON_RTC_CH1CAPT_SUBSEC_SHIFT)
#define AON_RTC_CH1CAPT_SEC_SHIFT (16) /* Bits 16-31: Value of SEC.VALUE bits 15:0 at capture time */
#define AON_RTC_CH1CAPT_SEC_MASK (0xffff << AON_RTC_CH1CAPT_SEC_SHIFT)
/* AON_RTC_SYNC */
/* TIVA_AON_RTC_SYNC */
#define AON_RTC_SYNC_WBUSY (1 << 0) /* Bit 0:
* Read: Outstanding MCU/AON write request
* Write: Force wait for SCLK_MF edge */
/* AON_RTC_TIME */
/* TIVA_AON_RTC_TIME */
#define AON_RTC_TIME_SUBSEC_H_SHIFT (0) /* Bits 0-15: Upper halfword of SUBSEC register */
#define AON_RTC_TIME_SUBSEC_H_MASK (0xffff << AON_RTC_TIME_SUBSEC_H_SHIFT)
#define AON_RTC_TIME_SEC_L_SHIFT (16) /* Bits 16-31: Lower halfward of SEC register */
#define AON_RTC_TIME_SEC_L_MASK (0xffff << AON_RTC_TIME_SEC_L_SHIFT)
/* AON_RTC_SYNCLF */
/* TIVA_AON_RTC_SYNCLF */
#define AON_RTC_SYNCLF_PHASE (1 << 0) /* Bit 0: SCLK_LF PHASE */
# define AON_RTC_SYNCLF_FALLING (0)