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Kconfig update

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4616 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-04-16 15:45:33 +00:00
parent 640a0718e2
commit abca2fa311
23 changed files with 614 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Kconfig
+4
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@@ -248,6 +248,10 @@ menu "System Type"
source "arch/Kconfig"
endmenu
menu "Board Selection"
source "configs/Kconfig"
endmenu
menu "Kernel Features"
source sched/Kconfig
endmenu
arch/8051/include/irq.h
+1 -1
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@@ -68,7 +68,7 @@
*/
#define IRAM_BASE 0x0000
#ifdef CONFIG_ARCH_8052
#ifdef CONFIG_ARCH_CHIP_8052
# define IRAM_SIZE 0x0100
#else
# define IRAM_SIZE 0x0080
arch/arm/src/arm/up_head.S
+1 -1
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@@ -458,7 +458,7 @@ __start:
.long MMU_L2_PGTABFLAGS /* L2 MMU flags to use */
#endif /* CONFIG_PAGING */
.size _start, .-_start
.size __start, .-__start
/****************************************************************************
* Name: .Lvstart
arch/sh/include/sh1/irq.h
+2 -2
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@@ -120,7 +120,7 @@
/* On-chip modules -- The following may be unique to the 7032 */
#ifdef CONFIG_ARCH_SH7032
#ifdef CONFIG_ARCH_CHIP_SH7032
/* DMAC */
@@ -342,7 +342,7 @@
/* On-chip modules -- The following may be unique to the 7032 */
#ifdef CONFIG_ARCH_SH7032
#ifdef CONFIG_ARCH_CHIP_SH7032
/* DMAC */
arch/sh/src/sh1/chip.h
+1 -1
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@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <stdint.h>
#ifdef CONFIG_ARCH_SH7032
#ifdef CONFIG_ARCH_CHIP_SH7032
# include "sh1_703x.h"
#endif
configs/Kconfig
+545
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File diff suppressed because it is too large Load Diff
configs/README.txt
+8 -9
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@@ -1354,17 +1354,17 @@ configs/compal_e88 and compal_e99
Denis Carikli using the Stefan Richter's Osmocom-bb patches.
configs/demo9s12ne64
Feescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This
Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This
port uses the m9s12x GCC toolchain. STATUS: (Still) under development; it
is code complete but has not yet been verified.
configs/ea3131
Embedded Artists EA3131 Development bard. This board is based on the
Embedded Artists EA3131 Development board. This board is based on the
an NXP LPC3131 MCU. This OS is built with the arm-elf toolchain*.
STATUS: This port is complete and mature.
configs/ea3152
Embedded Artists EA3152 Development bard. This board is based on the
Embedded Artists EA3152 Development board. This board is based on the
an NXP LPC3152 MCU. This OS is built with the arm-elf toolchain*.
STATUS: This port is has not be exercised well, but since it is
a simple derivative of the ea3131, it should be fully functional.
@@ -1468,8 +1468,6 @@ configs/olimex-lpc1766stk
configs/olimex-lpc2378
This port uses the Olimex-lpc2378 board and a GNU arm-elf toolchain* under
Linux or Cygwin. STATUS: ostest and NSH configurations available.
configs/olimex-lpc2378
This port for the NXP LPC2378 was contributed by Rommel Marcelo.
configs/olimex-strp711
@@ -1528,16 +1526,17 @@ configs/skp16c26
uses the GNU m32c toolchain. STATUS: The port is complete but untested
due to issues with compiler internal errors.
configs/stm3210e-evel
configs/stm3210e-eval
STMicro STM3210E-EVAL development board based on the STMicro STM32F103ZET6
microcontroller (ARM Cortex-M3). This port uses the GNU Cortex-M3
toolchain.
configs/stm3220g-eval
STMicro STM3220G-EVAL development board based.
STMicro STM3220G-EVAL development board based on the STMicro STM32F407IG
microcontroller (ARM Cortex-M3).
configs/stm3240g-eval
STMicro STM3210G-EVAL development board based on the STMicro STM32F103ZET6
STMicro STM3240G-EVAL development board based on the STMicro STM32F103ZET6
microcontroller (ARM Cortex-M4 with FPU). This port uses a GNU Cortex-M4
toolchain (such as CodeSourcery).
@@ -1552,7 +1551,7 @@ configs/sure-pic32mx
information about the Sure DB-DP11215 board.
configs/teensy
This is theport of NuttX to the PJRC Teensy++ 2.0 board. This board is
This is the port of NuttX to the PJRC Teensy++ 2.0 board. This board is
developed by http://pjrc.com/teensy/. The Teensy++ 2.0 is based
on an Atmel AT90USB1286 MCU.
configs/mcu123-lpc214x/composite/defconfig
+1 -1
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@@ -62,7 +62,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc214x
CONFIG_ARCH_LPC2148=y
CONFIG_ARCH_CHIP_LPC2148=y
CONFIG_ARCH_BOARD=mcu123-lpc214x
CONFIG_ARCH_BOARD_MCU123=y
CONFIG_BOARD_LOOPSPERMSEC=3270
configs/mcu123-lpc214x/nsh/defconfig
+1 -1
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@@ -62,7 +62,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc214x
CONFIG_ARCH_LPC2148=y
CONFIG_ARCH_CHIP_LPC2148=y
CONFIG_ARCH_BOARD=mcu123-lpc214x
CONFIG_ARCH_BOARD_MCU123=y
CONFIG_BOARD_LOOPSPERMSEC=3270
configs/mcu123-lpc214x/ostest/defconfig
+1 -1
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@@ -62,7 +62,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc214x
CONFIG_ARCH_LPC2148=y
CONFIG_ARCH_CHIP_LPC2148=y
CONFIG_ARCH_BOARD=mcu123-lpc214x
CONFIG_ARCH_BOARD_MCU123=y
CONFIG_BOARD_LOOPSPERMSEC=3270
configs/mcu123-lpc214x/usbserial/defconfig
+1 -1
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@@ -62,7 +62,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc214x
CONFIG_ARCH_LPC2148=y
CONFIG_ARCH_CHIP_LPC2148=y
CONFIG_ARCH_BOARD=mcu123-lpc214x
CONFIG_ARCH_BOARD_MCU123=y
CONFIG_BOARD_LOOPSPERMSEC=3270
configs/mcu123-lpc214x/usbstorage/defconfig
+1 -1
View File
@@ -62,7 +62,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc214x
CONFIG_ARCH_LPC2148=y
CONFIG_ARCH_CHIP_LPC2148=y
CONFIG_ARCH_BOARD=mcu123-lpc214x
CONFIG_ARCH_BOARD_MCU123=y
CONFIG_BOARD_LOOPSPERMSEC=3270
configs/olimex-lpc2378/nsh/defconfig
+2 -1
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@@ -70,8 +70,9 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc2378
CONFIG_ARCH_LPC2378=y
CONFIG_ARCH_CHIP_LPC2378=y
CONFIG_ARCH_BOARD=olimex-lpc2378
CONFIG_ARCH_BOARD_OLIMEXLPC2378=y
CONFIG_ARCH_IRQPRIO=y
CONFIG_BOARD_LOOPSPERMSEC=3270
CONFIG_ARCH_LEDS=y
configs/olimex-lpc2378/ostest/defconfig
+2 -1
View File
@@ -70,8 +70,9 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=lpc2378
CONFIG_ARCH_LPC2378=y
CONFIG_ARCH_CHIP_LPC2378=y
CONFIG_ARCH_BOARD=olimex-lpc2378
CONFIG_ARCH_BOARD_OLIMEXLPC2378=y
CONFIG_ARCH_IRQPRIO=y
CONFIG_BOARD_LOOPSPERMSEC=3270
CONFIG_ARCH_LEDS=y
configs/olimex-strp711/nettest/defconfig
+1 -1
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@@ -69,7 +69,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=str71x
CONFIG_ARCH_STR71X=y
CONFIG_ARCH_CHIP_STR71X=y
CONFIG_ARCH_BOARD=olimex-strp711
CONFIG_ARCH_BOARD_OLIMEX_STRP711=y
CONFIG_ARCH_NOINTC=n
configs/olimex-strp711/nsh/defconfig
+1 -1
View File
@@ -69,7 +69,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=str71x
CONFIG_ARCH_STR71X=y
CONFIG_ARCH_CHIP_STR71X=y
CONFIG_ARCH_BOARD=olimex-strp711
CONFIG_ARCH_BOARD_OLIMEX_STRP711=y
CONFIG_ARCH_NOINTC=n
configs/olimex-strp711/ostest/defconfig
+1 -1
View File
@@ -69,7 +69,7 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM7TDMI=y
CONFIG_ARCH_CHIP=str71x
CONFIG_ARCH_STR71X=y
CONFIG_ARCH_CHIP_STR71X=y
CONFIG_ARCH_BOARD=olimex-strp711
CONFIG_ARCH_BOARD_OLIMEX_STRP711=y
CONFIG_ARCH_NOINTC=n
configs/pjrc-8051/defconfig
+5 -4
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@@ -37,16 +37,17 @@
#
# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
# processor architecture.
# CONFIG_ARCH_8051 - Set if processor is 8051 family
# CONFIG_ARCH_8052 = Set if processor is 8052 family
# CONFIG_ARCH_CHIP_8051 - Set if processor is 8051 family
# CONFIG_ARCH_CHIP_8052 = Set if processor is 8052 family
# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
# the board that supports the particular chip or SoC.
# CONFIG_ARCH_BOARD_name - for use in C code
# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
#
CONFIG_ARCH=8051
CONFIG_ARCH_8051=n
CONFIG_ARCH_8052=y
CONFIG_ARCH_8051=y
CONFIG_ARCH_CHIP_8051=n
CONFIG_ARCH_CHIP_8052=y
CONFIG_ARCH_BOARD=pjrc-8051
CONFIG_ARCH_BOARD_PJRC_87C52=y
configs/stm3220g-eval/include/board.h
+29 -27
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@@ -2,7 +2,7 @@
* configs/stm3220g-eval/include/board.h
* include/arch/board/board.h
*
* Copyright (C) 2012-12 Gregory Nutt. All rights reserved.
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -66,16 +66,16 @@
*
* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
* System Clock source : PLL (HSE)
* SYSCLK(Hz) : 168000000 Determined by PLL configuration
* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
* SYSCLK(Hz) : 120000000 Determined by PLL configuration
* HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE)
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
* HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL)
* PLLM : 25 (STM32_PLLCFG_PLLM)
* PLLN : 336 (STM32_PLLCFG_PLLN)
* PLLN : 240 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
* PLLQ : 7 (STM32_PLLCFG_PPQ)
* PLLQ : 5 (STM32_PLLCFG_PPQ)
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
* Flash Latency(WS) : 5
* Prefetch Buffer : OFF
@@ -102,34 +102,35 @@
*
* PLL source is HSE
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* = (25,000,000 / 25) * 336
* = 336,000,000
* = (25,000,000 / 25) * 240
* = 240,000,000
* SYSCLK = PLL_VCO / PLLP
* = 336,000,000 / 2 = 168,000,000
* = 240,000,000 / 2 = 120,000,000
* USB OTG FS, SDIO and RNG Clock
* = PLL_VCO / PLLQ
* = 240,000,000 / 5 = 48,000,000
* = 48,000,000
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7)
#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(5)
#define STM32_SYSCLK_FREQUENCY 168000000ul
#define STM32_SYSCLK_FREQUENCY 120000000ul
/* AHB clock (HCLK) is SYSCLK (168MHz) */
/* AHB clock (HCLK) is SYSCLK (120MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
/* Timers driven from APB1 will be twice PCLK1 (60Mhz)*/
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
@@ -141,12 +142,12 @@
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB2 will be twice PCLK2 */
/* Timers driven from APB2 will be twice PCLK2 (120Mhz)*/
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
@@ -155,21 +156,21 @@
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1
*/
#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
* in order to avoid RX overrun/TX underrun errors due to delayed responses
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
@@ -177,9 +178,9 @@
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
@@ -264,9 +265,10 @@
* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
*/
#define GPIO_USART3_RX GPIO_USART3_RX_2
#define GPIO_USART3_TX GPIO_USART3_TX_2
#ifdef CONFIG_STM32_USART3
# define GPIO_USART3_RX GPIO_USART3_RX_2
# define GPIO_USART3_TX GPIO_USART3_TX_2
#endif
/* Ethernet:
*
@@ -398,8 +400,8 @@
*
* Mapping to STM32 GPIO pins:
*
* PD0 = FSMC_D2 & CAN1_RX
* PD1 = FSMC_D3 & CAN1_TX
* PD0 = FSMC_D2 & CAN1_RX
* PD1 = FSMC_D3 & CAN1_TX
* PB13 = ULPI_D6 & CAN2_TX
* PB5 = ULPI_D7 & CAN2_RX
*/
@@ -416,7 +418,7 @@
* - PB6 is I2C1_SCL
* - PB9 is I2C1_SDA
*/
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
configs/us7032evb1/README.txt
+1 -1
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@@ -93,7 +93,7 @@ Architecture selection
processor architecture. This should be sh (for arch/sh)
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory.
This should be sh1 (for arch/sh/src/sh1 and arch/sh/include/sh1)
CONFIG_ARCH_SH1 andCONFIG_ARCH_SH7032 - for use in C code. These
CONFIG_ARCH_SH1 and CONFIG_ARCH_CHIP_SH7032 - for use in C code. These
identify the particular chip or SoC that the architecture is
implemented in.
CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
configs/us7032evb1/nsh/defconfig
+2 -2
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@@ -65,9 +65,9 @@
# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
#
CONFIG_ARCH=sh
CONFIG_ARCH_CHIP=sh1
CONFIG_ARCH_SH1=y
CONFIG_ARCH_SH7032=y
CONFIG_ARCH_CHIP=sh1
CONFIG_ARCH_CHIP_SH7032=y
CONFIG_ARCH_BOARD=us7032evb1
CONFIG_ARCH_BOARD_US7032EVB1=y
CONFIG_ENDIAN_BIG=y
configs/us7032evb1/ostest/defconfig
+2 -2
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@@ -65,9 +65,9 @@
# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
#
CONFIG_ARCH=sh
CONFIG_ARCH_CHIP=sh1
CONFIG_ARCH_SH1=y
CONFIG_ARCH_SH7032=y
CONFIG_ARCH_CHIP=sh1
CONFIG_ARCH_CHIP_SH7032=y
CONFIG_ARCH_BOARD=us7032evb1
CONFIG_ARCH_BOARD_US7032EVB1=y
CONFIG_ENDIAN_BIG=y
configs/vsn/nsh/defconfig
+1
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@@ -78,6 +78,7 @@ CONFIG_ARCH_CHIP=stm32
CONFIG_ARCH_CHIP_STM32F103RET6=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD=vsn
CONFIG_ARCH_BOARD_VSN=y
CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_DRAM_SIZE=0x00010000
CONFIG_DRAM_START=0x20000000