mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 01:05:54 +08:00
libc/machine: introduce memchr/memmove/memset/strlen from newlib for armv7-m
N/A Signed-off-by: Huang Qi <huangqi3@xiaomi.com> Change-Id: If901402e3dc4e6776521ac18fcd2c61e06e6493b
This commit is contained in:
Huang Qi
@@ -5,6 +5,15 @@
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if ARCH_ARMV7M
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config ARMV7M_MEMCHR
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bool "Enable optimized memchr() for ARMv7-M"
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default n
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select MACHINE_OPTS_ARMV7M
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select LIBC_ARCH_MEMCHR
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depends on ARCH_TOOLCHAIN_GNU
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---help---
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Enable optimized ARMv7-M specific memchr() library function
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config ARMV7M_MEMCPY
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bool "Enable optimized memcpy() for ARMv7-M"
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default n
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@@ -14,6 +23,24 @@ config ARMV7M_MEMCPY
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---help---
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Enable optimized ARMv7-M specific memcpy() library function
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config ARMV7M_MEMSET
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bool "Enable optimized memset() for ARMv7-M"
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default n
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select MACHINE_OPTS_ARMV7M
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select LIBC_ARCH_MEMSET
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depends on ARCH_TOOLCHAIN_GNU
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---help---
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Enable optimized ARMv7-M specific memset() library function
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config ARMV7M_MEMMOVE
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bool "Enable optimized memmove() for ARMv7-M"
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default n
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select MACHINE_OPTS_ARMV7M
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select LIBC_ARCH_MEMMOVE
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depends on ARCH_TOOLCHAIN_GNU
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---help---
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Enable optimized ARMv7-M specific memmove() library function
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config ARMV7M_STRCMP
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bool "Enable optimized strcmp() for ARMv7-M"
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default n
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@@ -23,6 +50,15 @@ config ARMV7M_STRCMP
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---help---
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Enable optimized ARMv7-M specific strcmp() library function
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config ARMV7M_STRLEN
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bool "Enable optimized strlen() for ARMv7-M"
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default n
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select MACHINE_OPTS_ARMV7M
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select LIBC_ARCH_STRLEN
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depends on ARCH_TOOLCHAIN_GNU
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---help---
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Enable optimized ARMv7-M specific strlen() library function
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config ARMV7M_LIBM
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bool "Architecture specific FPU optimizations"
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default n
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@@ -33,14 +33,30 @@
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#
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############################################################################
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ifeq ($(CONFIG_ARMV7M_MEMCHR),y)
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ASRCS += arch_memchr.S
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endif
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ifeq ($(CONFIG_ARMV7M_MEMCPY),y)
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ASRCS += arch_memcpy.S
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endif
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ifeq ($(CONFIG_ARMV7M_MEMSET),y)
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ASRCS += arch_memset.S
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endif
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ifeq ($(CONFIG_ARMV7M_MEMMOVE),y)
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ASRCS += arch_memmove.S
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endif
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ifeq ($(CONFIG_ARMV7M_STRCMP),y)
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ASRCS += arch_strcmp.S
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endif
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ifeq ($(CONFIG_ARMV7M_STRLEN),y)
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ASRCS += arch_strlen.S
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endif
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ifeq ($(CONFIG_MACHINE_OPTS_ARMV7M),y)
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DEPPATH += --dep-path machine/arm/armv7-m/gnu
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VPATH += :machine/arm/armv7-m/gnu
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@@ -0,0 +1,181 @@
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/*
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* Copyright (c) 2014 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARM_ARCH
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/* ACLE standardises a set of pre-defines that describe the ARM architecture.
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These were mostly implemented in GCC around GCC-4.8; older versions
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have no, or only partial support. To provide a level of backwards
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compatibility we try to work out what the definitions should be, given
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the older pre-defines that GCC did produce. This isn't complete, but
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it should be enough for use by routines that depend on this header. */
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/* No need to handle ARMv8, GCC had ACLE support before that. */
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# ifdef __ARM_ARCH_7__
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/* The common subset of ARMv7 in all profiles. */
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# define __ARM_ARCH 7
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# define __ARM_ARCH_ISA_THUMB 2
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_LDREX 7
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# define __ARM_FEATURE_UNALIGNED
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# endif
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# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
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# define __ARM_ARCH 7
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# define __ARM_ARCH_ISA_THUMB 2
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# define __ARM_ARCH_ISA_ARM
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_SIMD32
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# define __ARM_FEATURE_DSP
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# define __ARM_FEATURE_QBIT
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# define __ARM_FEATURE_SAT
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# define __ARM_FEATURE_LDREX 15
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# define __ARM_FEATURE_UNALIGNED
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# ifdef __ARM_ARCH_7A__
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# define __ARM_ARCH_PROFILE 'A'
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# else
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# define __ARM_ARCH_PROFILE 'R'
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# endif
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# endif
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# ifdef __ARM_ARCH_7EM__
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# define __ARM_ARCH 7
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# define __ARM_ARCH_ISA_THUMB 2
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_SIMD32
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# define __ARM_FEATURE_DSP
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# define __ARM_FEATURE_QBIT
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# define __ARM_FEATURE_SAT
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# define __ARM_FEATURE_LDREX 7
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# define __ARM_FEATURE_UNALIGNED
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# define __ARM_ARCH_PROFILE 'M'
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# endif
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# ifdef __ARM_ARCH_7M__
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# define __ARM_ARCH 7
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# define __ARM_ARCH_ISA_THUMB 2
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_QBIT
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# define __ARM_FEATURE_SAT
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# define __ARM_FEATURE_LDREX 7
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# define __ARM_FEATURE_UNALIGNED
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# define __ARM_ARCH_PROFILE 'M'
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# endif
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# ifdef __ARM_ARCH_6T2__
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# define __ARM_ARCH 6
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# define __ARM_ARCH_ISA_THUMB 2
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# define __ARM_ARCH_ISA_ARM
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_SIMD32
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# define __ARM_FEATURE_DSP
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# define __ARM_FEATURE_QBIT
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# define __ARM_FEATURE_SAT
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# define __ARM_FEATURE_LDREX 4
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# define __ARM_FEATURE_UNALIGNED
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# endif
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# ifdef __ARM_ARCH_6M__
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# define __ARM_ARCH 6
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# define __ARM_ARCH_ISA_THUMB 1
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# define __ARM_ARCH_PROFILE 'M'
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# endif
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# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
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|| defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
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|| defined (__ARM_ARCH_6ZK__)
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# define __ARM_ARCH 6
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# define __ARM_ARCH_ISA_THUMB 1
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# define __ARM_ARCH_ISA_ARM
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_SIMD32
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# define __ARM_FEATURE_DSP
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# define __ARM_FEATURE_QBIT
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# define __ARM_FEATURE_SAT
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# define __ARM_FEATURE_UNALIGNED
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# ifndef __thumb__
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# if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
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# define __ARM_FEATURE_LDREX 15
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# else
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# define __ARM_FEATURE_LDREX 4
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# endif
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# endif
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# endif
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# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
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# define __ARM_ARCH 5
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# define __ARM_ARCH_ISA_ARM
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# ifdef __ARM_ARCH_5TE__
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# define __ARM_ARCH_ISA_THUMB 1
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# endif
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# define __ARM_FEATURE_CLZ
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# define __ARM_FEATURE_DSP
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# endif
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# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
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# define __ARM_ARCH 5
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# define __ARM_ARCH_ISA_ARM
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# ifdef __ARM_ARCH_5TE__
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# define __ARM_ARCH_ISA_THUMB 1
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# endif
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# define __ARM_FEATURE_CLZ
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# endif
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# ifdef __ARM_ARCH_4T__
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# define __ARM_ARCH 4
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# define __ARM_ARCH_ISA_ARM
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# define __ARM_ARCH_ISA_THUMB 1
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# endif
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# ifdef __ARM_ARCH_4__
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# define __ARM_ARCH 4
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# define __ARM_ARCH_ISA_ARM
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# endif
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# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
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# define __ARM_ARCH 3
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# define __ARM_ARCH_ISA_ARM
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# endif
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# ifdef __ARM_ARCH_2__
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# define __ARM_ARCH 2
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# define __ARM_ARCH_ISA_ARM
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# endif
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# ifdef __ARMEB__
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# define __ARM_BIG_ENDIAN
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# endif
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/* If we still don't know what the target architecture is, then we're
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probably not using GCC. */
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# ifndef __ARM_ARCH
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# error Unable to determine architecture version.
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# endif
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#endif /* __ARM_ARCH */
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@@ -0,0 +1,386 @@
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/* Copyright (c) 2010-2011, Linaro Limited
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All rights reserved.
|
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|
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Linaro Limited nor the names of its
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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|
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Written by Dave Gilbert <david.gilbert@linaro.org>
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This memchr routine is optimised on a Cortex-A9 and should work on
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all ARMv7 processors. It has a fast path for short sizes, and has
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an optimised path for large data sets; the worst case is finding the
|
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match early in a large data set. */
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|
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/* Copyright (c) 2015 ARM Ltd.
|
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All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the Linaro nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
@ 2011-02-07 david.gilbert@linaro.org
|
||||
@ Extracted from local git a5b438d861
|
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@ 2011-07-14 david.gilbert@linaro.org
|
||||
@ Import endianness fix from local git ea786f1b
|
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@ 2011-10-11 david.gilbert@linaro.org
|
||||
@ Import from cortex-strings bzr rev 63
|
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@ Flip to ldrd (as suggested by Greta Yorsh)
|
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@ Make conditional on CPU type
|
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@ tidy
|
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|
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@ This code requires armv6t2 or later. Uses Thumb2.
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|
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.syntax unified
|
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|
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#include "acle-compat.h"
|
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|
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@ NOTE: This ifdef MUST match the one in memchr-stub.c
|
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#if defined (__ARM_NEON__) || defined (__ARM_NEON)
|
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#if __ARM_ARCH >= 8 && __ARM_ARCH_PROFILE == 'R'
|
||||
.arch armv8-r
|
||||
#else
|
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.arch armv7-a
|
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#endif
|
||||
.fpu neon
|
||||
|
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|
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/* Arguments */
|
||||
#define srcin r0
|
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#define chrin r1
|
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#define cntin r2
|
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|
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/* Retval */
|
||||
#define result r0 /* Live range does not overlap with srcin */
|
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|
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/* Working registers */
|
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#define src r1 /* Live range does not overlap with chrin */
|
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#define tmp r3
|
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#define synd r0 /* No overlap with srcin or result */
|
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#define soff r12
|
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|
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/* Working NEON registers */
|
||||
#define vrepchr q0
|
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#define vdata0 q1
|
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#define vdata0_0 d2 /* Lower half of vdata0 */
|
||||
#define vdata0_1 d3 /* Upper half of vdata0 */
|
||||
#define vdata1 q2
|
||||
#define vdata1_0 d4 /* Lower half of vhas_chr0 */
|
||||
#define vdata1_1 d5 /* Upper half of vhas_chr0 */
|
||||
#define vrepmask q3
|
||||
#define vrepmask0 d6
|
||||
#define vrepmask1 d7
|
||||
#define vend q4
|
||||
#define vend0 d8
|
||||
#define vend1 d9
|
||||
|
||||
/*
|
||||
* Core algorithm:
|
||||
*
|
||||
* For each 32-byte chunk we calculate a 32-bit syndrome value, with one bit per
|
||||
* byte. Each bit is set if the relevant byte matched the requested character
|
||||
* and cleared otherwise. Since the bits in the syndrome reflect exactly the
|
||||
* order in which things occur in the original string, counting trailing zeros
|
||||
* allows to identify exactly which byte has matched.
|
||||
*/
|
||||
|
||||
.text
|
||||
.thumb_func
|
||||
.align 4
|
||||
.p2align 4,,15
|
||||
.global memchr
|
||||
.type memchr,%function
|
||||
|
||||
memchr:
|
||||
.cfi_sections .debug_frame
|
||||
.cfi_startproc
|
||||
/* Use a simple loop if there are less than 8 bytes to search. */
|
||||
cmp cntin, #7
|
||||
bhi .Llargestr
|
||||
and chrin, chrin, #0xff
|
||||
|
||||
.Lsmallstr:
|
||||
subs cntin, cntin, #1
|
||||
blo .Lnotfound /* Return not found if reached end. */
|
||||
ldrb tmp, [srcin], #1
|
||||
cmp tmp, chrin
|
||||
bne .Lsmallstr /* Loop again if not found. */
|
||||
/* Otherwise fixup address and return. */
|
||||
sub result, result, #1
|
||||
bx lr
|
||||
|
||||
|
||||
.Llargestr:
|
||||
vdup.8 vrepchr, chrin /* Duplicate char across all lanes. */
|
||||
/*
|
||||
* Magic constant 0x8040201008040201 allows us to identify which lane
|
||||
* matches the requested byte.
|
||||
*/
|
||||
movw tmp, #0x0201
|
||||
movt tmp, #0x0804
|
||||
lsl soff, tmp, #4
|
||||
vmov vrepmask0, tmp, soff
|
||||
vmov vrepmask1, tmp, soff
|
||||
/* Work with aligned 32-byte chunks */
|
||||
bic src, srcin, #31
|
||||
ands soff, srcin, #31
|
||||
beq .Lloopintro /* Go straight to main loop if it's aligned. */
|
||||
|
||||
/*
|
||||
* Input string is not 32-byte aligned. We calculate the syndrome
|
||||
* value for the aligned 32 bytes block containing the first bytes
|
||||
* and mask the irrelevant part.
|
||||
*/
|
||||
vld1.8 {vdata0, vdata1}, [src:256]!
|
||||
sub tmp, soff, #32
|
||||
adds cntin, cntin, tmp
|
||||
vceq.i8 vdata0, vdata0, vrepchr
|
||||
vceq.i8 vdata1, vdata1, vrepchr
|
||||
vand vdata0, vdata0, vrepmask
|
||||
vand vdata1, vdata1, vrepmask
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata0_1
|
||||
vpadd.i8 vdata1_0, vdata1_0, vdata1_1
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata1_0
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata0_0
|
||||
vmov synd, vdata0_0[0]
|
||||
|
||||
/* Clear the soff lower bits */
|
||||
lsr synd, synd, soff
|
||||
lsl synd, synd, soff
|
||||
/* The first block can also be the last */
|
||||
bls .Lmasklast
|
||||
/* Have we found something already? */
|
||||
cbnz synd, .Ltail
|
||||
|
||||
|
||||
.Lloopintro:
|
||||
vpush {vend}
|
||||
/* 264/265 correspond to d8/d9 for q4 */
|
||||
.cfi_adjust_cfa_offset 16
|
||||
.cfi_rel_offset 264, 0
|
||||
.cfi_rel_offset 265, 8
|
||||
.p2align 3,,7
|
||||
.Lloop:
|
||||
vld1.8 {vdata0, vdata1}, [src:256]!
|
||||
subs cntin, cntin, #32
|
||||
vceq.i8 vdata0, vdata0, vrepchr
|
||||
vceq.i8 vdata1, vdata1, vrepchr
|
||||
/* If we're out of data we finish regardless of the result. */
|
||||
bls .Lend
|
||||
/* Use a fast check for the termination condition. */
|
||||
vorr vend, vdata0, vdata1
|
||||
vorr vend0, vend0, vend1
|
||||
vmov synd, tmp, vend0
|
||||
orrs synd, synd, tmp
|
||||
/* We're not out of data, loop if we haven't found the character. */
|
||||
beq .Lloop
|
||||
|
||||
.Lend:
|
||||
vpop {vend}
|
||||
.cfi_adjust_cfa_offset -16
|
||||
.cfi_restore 264
|
||||
.cfi_restore 265
|
||||
|
||||
/* Termination condition found, let's calculate the syndrome value. */
|
||||
vand vdata0, vdata0, vrepmask
|
||||
vand vdata1, vdata1, vrepmask
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata0_1
|
||||
vpadd.i8 vdata1_0, vdata1_0, vdata1_1
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata1_0
|
||||
vpadd.i8 vdata0_0, vdata0_0, vdata0_0
|
||||
vmov synd, vdata0_0[0]
|
||||
cbz synd, .Lnotfound
|
||||
bhi .Ltail
|
||||
|
||||
|
||||
.Lmasklast:
|
||||
/* Clear the (-cntin) upper bits to avoid out-of-bounds matches. */
|
||||
neg cntin, cntin
|
||||
lsl synd, synd, cntin
|
||||
lsrs synd, synd, cntin
|
||||
it eq
|
||||
moveq src, #0 /* If no match, set src to 0 so the retval is 0. */
|
||||
|
||||
|
||||
.Ltail:
|
||||
/* Count the trailing zeros using bit reversing */
|
||||
rbit synd, synd
|
||||
/* Compensate the last post-increment */
|
||||
sub src, src, #32
|
||||
/* Count the leading zeros */
|
||||
clz synd, synd
|
||||
/* Compute the potential result and return */
|
||||
add result, src, synd
|
||||
bx lr
|
||||
|
||||
|
||||
.Lnotfound:
|
||||
/* Set result to NULL if not found and return */
|
||||
mov result, #0
|
||||
bx lr
|
||||
|
||||
.cfi_endproc
|
||||
.size memchr, . - memchr
|
||||
|
||||
#elif __ARM_ARCH_ISA_THUMB >= 2 && defined (__ARM_FEATURE_DSP)
|
||||
|
||||
#if __ARM_ARCH_PROFILE == 'M'
|
||||
.arch armv7e-m
|
||||
#else
|
||||
.arch armv6t2
|
||||
#endif
|
||||
|
||||
@ this lets us check a flag in a 00/ff byte easily in either endianness
|
||||
#ifdef __ARMEB__
|
||||
#define CHARTSTMASK(c) 1<<(31-(c*8))
|
||||
#else
|
||||
#define CHARTSTMASK(c) 1<<(c*8)
|
||||
#endif
|
||||
.text
|
||||
.thumb
|
||||
|
||||
@ ---------------------------------------------------------------------------
|
||||
.thumb_func
|
||||
.align 2
|
||||
.p2align 4,,15
|
||||
.global memchr
|
||||
.type memchr,%function
|
||||
memchr:
|
||||
@ r0 = start of memory to scan
|
||||
@ r1 = character to look for
|
||||
@ r2 = length
|
||||
@ returns r0 = pointer to character or NULL if not found
|
||||
and r1,r1,#0xff @ Don't trust the caller to pass a char
|
||||
|
||||
cmp r2,#16 @ If short don't bother with anything clever
|
||||
blt 20f
|
||||
|
||||
tst r0, #7 @ If it's already aligned skip the next bit
|
||||
beq 10f
|
||||
|
||||
@ Work up to an aligned point
|
||||
5:
|
||||
ldrb r3, [r0],#1
|
||||
subs r2, r2, #1
|
||||
cmp r3, r1
|
||||
beq 50f @ If it matches exit found
|
||||
tst r0, #7
|
||||
cbz r2, 40f @ If we run off the end, exit not found
|
||||
bne 5b @ If not aligned yet then do next byte
|
||||
|
||||
10:
|
||||
@ We are aligned, we know we have at least 8 bytes to work with
|
||||
push {r4,r5,r6,r7}
|
||||
orr r1, r1, r1, lsl #8 @ expand the match word across all bytes
|
||||
orr r1, r1, r1, lsl #16
|
||||
bic r4, r2, #7 @ Number of double words to work with * 8
|
||||
mvns r7, #0 @ all F's
|
||||
movs r3, #0
|
||||
|
||||
15:
|
||||
ldrd r5,r6,[r0],#8
|
||||
subs r4, r4, #8
|
||||
eor r5,r5, r1 @ r5,r6 have 00's where bytes match the target
|
||||
eor r6,r6, r1
|
||||
uadd8 r5, r5, r7 @ Par add 0xff - sets GE bits for bytes!=0
|
||||
sel r5, r3, r7 @ bytes are 00 for none-00 bytes,
|
||||
@ or ff for 00 bytes - NOTE INVERSION
|
||||
uadd8 r6, r6, r7 @ Par add 0xff - sets GE bits for bytes!=0
|
||||
sel r6, r5, r7 @ chained....bytes are 00 for none-00 bytes
|
||||
@ or ff for 00 bytes - NOTE INVERSION
|
||||
cbnz r6, 60f
|
||||
bne 15b @ (Flags from the subs above)
|
||||
|
||||
pop {r4,r5,r6,r7}
|
||||
and r1,r1,#0xff @ r1 back to a single character
|
||||
and r2,r2,#7 @ Leave the count remaining as the number
|
||||
@ after the double words have been done
|
||||
|
||||
20:
|
||||
cbz r2, 40f @ 0 length or hit the end already then not found
|
||||
|
||||
21: @ Post aligned section, or just a short call
|
||||
ldrb r3,[r0],#1
|
||||
subs r2,r2,#1
|
||||
eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub
|
||||
cbz r3, 50f
|
||||
bne 21b @ on r2 flags
|
||||
|
||||
40:
|
||||
movs r0,#0 @ not found
|
||||
bx lr
|
||||
|
||||
50:
|
||||
subs r0,r0,#1 @ found
|
||||
bx lr
|
||||
|
||||
60: @ We're here because the fast path found a hit
|
||||
@ now we have to track down exactly which word it was
|
||||
@ r0 points to the start of the double word after the one tested
|
||||
@ r5 has the 00/ff pattern for the first word, r6 has the chained value
|
||||
cmp r5, #0
|
||||
itte eq
|
||||
moveq r5, r6 @ the end is in the 2nd word
|
||||
subeq r0,r0,#3 @ Points to 2nd byte of 2nd word
|
||||
subne r0,r0,#7 @ or 2nd byte of 1st word
|
||||
|
||||
@ r0 currently points to the 2nd byte of the word containing the hit
|
||||
tst r5, # CHARTSTMASK(0) @ 1st character
|
||||
bne 61f
|
||||
adds r0,r0,#1
|
||||
tst r5, # CHARTSTMASK(1) @ 2nd character
|
||||
ittt eq
|
||||
addeq r0,r0,#1
|
||||
tsteq r5, # (3<<15) @ 2nd & 3rd character
|
||||
@ If not the 3rd must be the last one
|
||||
addeq r0,r0,#1
|
||||
|
||||
61:
|
||||
pop {r4,r5,r6,r7}
|
||||
subs r0,r0,#1
|
||||
bx lr
|
||||
#else
|
||||
/* Defined in memchr-stub.c. */
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2015 ARM Ltd
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the company may not be used to endorse or promote
|
||||
* products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
||||
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
.thumb
|
||||
.syntax unified
|
||||
.global memmove
|
||||
.type memmove, %function
|
||||
memmove:
|
||||
cmp r0, r1
|
||||
push {r4}
|
||||
bls 3f
|
||||
adds r3, r1, r2
|
||||
cmp r0, r3
|
||||
bcs 3f
|
||||
adds r1, r0, r2
|
||||
cbz r2, 2f
|
||||
subs r2, r3, r2
|
||||
1:
|
||||
ldrb r4, [r3, #-1]!
|
||||
cmp r2, r3
|
||||
strb r4, [r1, #-1]!
|
||||
bne 1b
|
||||
2:
|
||||
pop {r4}
|
||||
bx lr
|
||||
3:
|
||||
cmp r2, #0
|
||||
beq 2b
|
||||
add r2, r2, r1
|
||||
subs r3, r0, #1
|
||||
4:
|
||||
ldrb r4, [r1], #1
|
||||
cmp r2, r1
|
||||
strb r4, [r3, #1]!
|
||||
bne 4b
|
||||
pop {r4}
|
||||
bx lr
|
||||
.size memmove, . - memmove
|
||||
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* Copyright (c) 2015 ARM Ltd
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the company may not be used to endorse or promote
|
||||
* products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
||||
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
.thumb
|
||||
.syntax unified
|
||||
.global memset
|
||||
.type memset, %function
|
||||
memset:
|
||||
push {r4, r5, r6}
|
||||
lsls r4, r0, #30
|
||||
beq 10f
|
||||
subs r4, r1, #1
|
||||
cmp r1, #0
|
||||
beq 9f
|
||||
uxtb r5, r2
|
||||
mov r3, r0
|
||||
b 2f
|
||||
1:
|
||||
subs r1, r4, #1
|
||||
cbz r4, 9f
|
||||
mov r4, r1
|
||||
2:
|
||||
strb r5, [r3], #1
|
||||
lsls r1, r3, #30
|
||||
bne 1b
|
||||
3:
|
||||
cmp r4, #3
|
||||
bls 7f
|
||||
uxtb r5, r2
|
||||
orr r5, r5, r5, lsl #8
|
||||
cmp r4, #15
|
||||
orr r5, r5, r5, lsl #16
|
||||
bls 5f
|
||||
mov r6, r4
|
||||
add r1, r3, #16
|
||||
4:
|
||||
subs r6, r6, #16
|
||||
cmp r6, #15
|
||||
str r5, [r1, #-16]
|
||||
str r5, [r1, #-12]
|
||||
str r5, [r1, #-8]
|
||||
str r5, [r1, #-4]
|
||||
add r1, r1, #16
|
||||
bhi 4b
|
||||
sub r1, r4, #16
|
||||
bic r1, r1, #15
|
||||
and r4, r4, #15
|
||||
adds r1, r1, #16
|
||||
cmp r4, #3
|
||||
add r3, r3, r1
|
||||
bls 7f
|
||||
5:
|
||||
mov r6, r3
|
||||
mov r1, r4
|
||||
6:
|
||||
subs r1, r1, #4
|
||||
cmp r1, #3
|
||||
str r5, [r6], #4
|
||||
bhi 6b
|
||||
subs r1, r4, #4
|
||||
bic r1, r1, #3
|
||||
adds r1, r1, #4
|
||||
add r3, r3, r1
|
||||
and r4, r4, #3
|
||||
7:
|
||||
cbz r4, 9f
|
||||
uxtb r2, r2
|
||||
add r4, r4, r3
|
||||
8:
|
||||
strb r2, [r3], #1
|
||||
cmp r3, r4
|
||||
bne 8b
|
||||
9:
|
||||
pop {r4, r5, r6}
|
||||
bx lr
|
||||
10:
|
||||
mov r4, r1
|
||||
mov r3, r0
|
||||
b 3b
|
||||
.size memset, . - memset
|
||||
@@ -0,0 +1,179 @@
|
||||
/* Copyright (c) 2010-2011,2013 Linaro Limited
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
* Neither the name of Linaro Limited nor the names of its
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
Assumes:
|
||||
ARMv6T2 or ARMv7E-M, AArch32
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2015 ARM Ltd.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the Linaro nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
|
||||
|
||||
#include "acle-compat.h"
|
||||
|
||||
.macro def_fn f p2align=0
|
||||
.text
|
||||
.p2align \p2align
|
||||
.global \f
|
||||
.type \f, %function
|
||||
\f:
|
||||
.endm
|
||||
#ifdef __ARMEB__
|
||||
#define S2LO lsl
|
||||
#define S2HI lsr
|
||||
#else
|
||||
#define S2LO lsr
|
||||
#define S2HI lsl
|
||||
#endif
|
||||
|
||||
/* This code requires Thumb. */
|
||||
#if __ARM_ARCH_PROFILE == 'M'
|
||||
.arch armv7e-m
|
||||
#else
|
||||
.arch armv6t2
|
||||
#endif
|
||||
.eabi_attribute Tag_ARM_ISA_use, 0
|
||||
.thumb
|
||||
.syntax unified
|
||||
|
||||
/* Parameters and result. */
|
||||
#define srcin r0
|
||||
#define result r0
|
||||
|
||||
/* Internal variables. */
|
||||
#define src r1
|
||||
#define data1a r2
|
||||
#define data1b r3
|
||||
#define const_m1 r12
|
||||
#define const_0 r4
|
||||
#define tmp1 r4 /* Overlaps const_0 */
|
||||
#define tmp2 r5
|
||||
|
||||
def_fn strlen p2align=6
|
||||
pld [srcin, #0]
|
||||
strd r4, r5, [sp, #-8]!
|
||||
bic src, srcin, #7
|
||||
mvn const_m1, #0
|
||||
ands tmp1, srcin, #7 /* (8 - bytes) to alignment. */
|
||||
pld [src, #32]
|
||||
bne.w .Lmisaligned8
|
||||
mov const_0, #0
|
||||
mov result, #-8
|
||||
.Lloop_aligned:
|
||||
/* Bytes 0-7. */
|
||||
ldrd data1a, data1b, [src]
|
||||
pld [src, #64]
|
||||
add result, result, #8
|
||||
.Lstart_realigned:
|
||||
uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
|
||||
sel data1a, const_0, const_m1 /* Select based on GE<0:3>. */
|
||||
uadd8 data1b, data1b, const_m1
|
||||
sel data1b, data1a, const_m1 /* Only used if d1a == 0. */
|
||||
cbnz data1b, .Lnull_found
|
||||
|
||||
/* Bytes 8-15. */
|
||||
ldrd data1a, data1b, [src, #8]
|
||||
uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
|
||||
add result, result, #8
|
||||
sel data1a, const_0, const_m1 /* Select based on GE<0:3>. */
|
||||
uadd8 data1b, data1b, const_m1
|
||||
sel data1b, data1a, const_m1 /* Only used if d1a == 0. */
|
||||
cbnz data1b, .Lnull_found
|
||||
|
||||
/* Bytes 16-23. */
|
||||
ldrd data1a, data1b, [src, #16]
|
||||
uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
|
||||
add result, result, #8
|
||||
sel data1a, const_0, const_m1 /* Select based on GE<0:3>. */
|
||||
uadd8 data1b, data1b, const_m1
|
||||
sel data1b, data1a, const_m1 /* Only used if d1a == 0. */
|
||||
cbnz data1b, .Lnull_found
|
||||
|
||||
/* Bytes 24-31. */
|
||||
ldrd data1a, data1b, [src, #24]
|
||||
add src, src, #32
|
||||
uadd8 data1a, data1a, const_m1 /* Saturating GE<0:3> set. */
|
||||
add result, result, #8
|
||||
sel data1a, const_0, const_m1 /* Select based on GE<0:3>. */
|
||||
uadd8 data1b, data1b, const_m1
|
||||
sel data1b, data1a, const_m1 /* Only used if d1a == 0. */
|
||||
cmp data1b, #0
|
||||
beq .Lloop_aligned
|
||||
|
||||
.Lnull_found:
|
||||
cmp data1a, #0
|
||||
itt eq
|
||||
addeq result, result, #4
|
||||
moveq data1a, data1b
|
||||
#ifndef __ARMEB__
|
||||
rev data1a, data1a
|
||||
#endif
|
||||
clz data1a, data1a
|
||||
ldrd r4, r5, [sp], #8
|
||||
add result, result, data1a, lsr #3 /* Bits -> Bytes. */
|
||||
bx lr
|
||||
|
||||
.Lmisaligned8:
|
||||
ldrd data1a, data1b, [src]
|
||||
and tmp2, tmp1, #3
|
||||
rsb result, tmp1, #0
|
||||
lsl tmp2, tmp2, #3 /* Bytes -> bits. */
|
||||
tst tmp1, #4
|
||||
pld [src, #64]
|
||||
S2HI tmp2, const_m1, tmp2
|
||||
orn data1a, data1a, tmp2
|
||||
itt ne
|
||||
ornne data1b, data1b, tmp2
|
||||
movne data1a, const_m1
|
||||
mov const_0, #0
|
||||
b .Lstart_realigned
|
||||
.size strlen, . - strlen
|
||||
@@ -37,8 +37,8 @@
|
||||
# Add the string C files to the build
|
||||
|
||||
CSRCS += lib_ffs.c lib_ffsl.c lib_ffsll.c lib_fls.c lib_flsl.c
|
||||
CSRCS += lib_flsll.c lib_isbasedigit.c lib_memset.c lib_memchr.c
|
||||
CSRCS += lib_memccpy.c lib_memcmp.c lib_memmove.c lib_memrchr.c
|
||||
CSRCS += lib_flsll.c lib_isbasedigit.c
|
||||
CSRCS += lib_memccpy.c lib_memcmp.c lib_memrchr.c
|
||||
CSRCS += lib_popcount.c lib_popcountl.c lib_popcountll.c
|
||||
CSRCS += lib_skipspace.c lib_stpcpy.c lib_stpncpy.c lib_strcasecmp.c
|
||||
CSRCS += lib_strcat.c lib_strchr.c lib_strcpy.c lib_strcspn.c
|
||||
@@ -51,6 +51,10 @@ CSRCS += lib_anbstr2cstr.c lib_ancstr2bstr.c lib_bmem2cmem.c
|
||||
CSRCS += lib_bstrnlen.c lib_cmem2bmem.c lib_nbstr2cstr.c lib_ncstr2bstr.c
|
||||
CSRCS += lib_index.c lib_rindex.c lib_strlcpy.c
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_MEMCHR),y)
|
||||
CSRCS += lib_memchr.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_MEMCPY),y)
|
||||
ifeq ($(CONFIG_MEMCPY_VIK),y)
|
||||
CSRCS += lib_vikmemcpy.c
|
||||
@@ -59,10 +63,26 @@ CSRCS += lib_memcpy.c
|
||||
endif
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_MEMSET),y)
|
||||
CSRCS += lib_memset.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_MEMMOVE),y)
|
||||
CSRCS += lib_memmove.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_STRCPY),y)
|
||||
CSRCS += lib_strcpy.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_STRCMP),y)
|
||||
CSRCS += lib_strcmp.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_LIBC_ARCH_STRLEN),y)
|
||||
CSRCS += lib_strlen.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIBC_LOCALE),y)
|
||||
CSRCS += lib_strcoll.c lib_strxfrm.c
|
||||
endif
|
||||
|
||||
Reference in New Issue
Block a user