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More trailing whilespace removal

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This commit is contained in:
Gregory Nutt
2014-04-13 16:22:22 -06:00
parent fb4fa33cae
commit ab5b37189b
503 changed files with 1312 additions and 1312 deletions
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configs/16z/README.txt
+1 -1
View File
@@ -126,7 +126,7 @@ Other Versions
If you use any version of ZDS-II other than 5.0.1 or if you install ZDS-II
at any location other than the default location, you will have to modify
two files: (1) configs/16z/*/setenv.sh and (2) configs/16z/*/Make.defs.
two files: (1) configs/16z/*/setenv.sh and (2) configs/16z/*/Make.defs.
Simply edit these two files, changing 5.0.1 to whatever.
Patches
configs/16z/src/Makefile
+1 -1
View File
@@ -49,7 +49,7 @@ endif
INCLUDES = $(ARCHSTDINCLUDES) $(USRINCLUDES)
CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(INCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(EXTRADEFINES)
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = z16f_lowinit.c z16f_leds.c
COBJS = $(CSRCS:.c=$(OBJEXT))
configs/16z/tools/zneo-zdsii-5_0_1-variadic-func-fix.patch
+10 -10
View File
@@ -22,12 +22,12 @@ index ba7dbe7..b9f9991 100644
+ FAR const char *fmt, va_list ap);
+#endif
static FAR char *nsh_consolelinebuffer(FAR struct nsh_vtbl_s *vtbl);
#if CONFIG_NFILE_DESCRIPTORS > 0
@@ -213,6 +219,7 @@ static ssize_t nsh_consolewrite(FAR struct nsh_vtbl_s *vtbl, FAR const void *buf
*
****************************************************************************/
+#if 0
static int nsh_consoleoutput(FAR struct nsh_vtbl_s *vtbl,
FAR const char *fmt, ...)
@@ -35,7 +35,7 @@ index ba7dbe7..b9f9991 100644
@@ -263,6 +270,51 @@ static int nsh_consoleoutput(FAR struct nsh_vtbl_s *vtbl,
#endif
}
+#else
+static int nsh_consolevoutput(FAR struct nsh_vtbl_s *vtbl, FAR const char *fmt, va_list ap)
+{
@@ -95,7 +95,7 @@ index ba7dbe7..b9f9991 100644
+#endif
pstate->cn_vtbl.linebuffer = nsh_consolelinebuffer;
pstate->cn_vtbl.exit = nsh_consoleexit;
@@ -489,3 +545,15 @@ FAR struct console_stdio_s *nsh_newconsole(void)
}
return pstate;
@@ -122,12 +122,12 @@ index c78362f..59bd8d7 100644
#include <stdbool.h>
+#include <stdarg.h>
#include <errno.h>
/****************************************************************************
@@ -62,11 +63,13 @@
#define nsh_undirect(v,s) (v)->undirect(v,s)
#define nsh_exit(v,s) (v)->exit(v,s)
+#if 0
#ifdef CONFIG_CPP_HAVE_VARARGS
# define nsh_output(v, fmt...) (v)->output(v, ##fmt)
@@ -135,9 +135,9 @@ index c78362f..59bd8d7 100644
# define nsh_output vtbl->output
#endif
+#endif
/* Size of info to be saved in call to nsh_redirect */
@@ -107,7 +110,11 @@ struct nsh_vtbl_s
void (*release)(FAR struct nsh_vtbl_s *vtbl);
#endif
@@ -152,8 +152,8 @@ index c78362f..59bd8d7 100644
void (*redirect)(FAR struct nsh_vtbl_s *vtbl, int fd, FAR uint8_t *save);
@@ -159,5 +166,6 @@ struct console_stdio_s
/* Defined in nsh_console.c *************************************************/
FAR struct console_stdio_s *nsh_newconsole(void);
+int nsh_output(FAR struct nsh_vtbl_s *vtbl, FAR const char *fmt, ...);
#endif /* __APPS_NSHLIB_NSH_CONSOLE_H */
configs/amber/README.txt
+13 -13
View File
@@ -120,21 +120,21 @@ Switches and Jumpers
^^^^^^^^^^^^^^^^^^^^
ISP/UART0
JP1 - DTE/DCE selection
JP2 -
JP5 -
JP2 -
JP5 -
J11 - STK500 Enable
ADC
JP8 -
JP9 -
JP8 -
JP9 -
Networking
JP10 -
JP10 -
RS-485
J8 -
J9 -
J10 -
J8 -
J9 -
J10 -
Atmel AVRISP mkII Connection
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -149,7 +149,7 @@ Atmel AVRISP mkII Connection
(ISP10PIN Connector)
------------------- -------------------------
1 2
MOSI o o Vcc - ISP-PDI: PE0/PDI/RX0 via 74HC5053
LED o o GND - ISP-PROG: J11/GND, to 74HC5053 and LED
@@ -241,7 +241,7 @@ Windows Native Toolchains
^^^^^^^^^^^^^^^^^^^^^^^^^
The WinAVR toolchain is a Windows native toolchain. There are several
limitations to using a Windows native toolchain in a Cygwin environment.
limitations to using a Windows native toolchain in a Cygwin environment.
The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
@@ -341,14 +341,14 @@ Build Notes:
the flowing point library, then you may have to build avr-lib from sources.
Below are instructions for building avr-lib from fresh sources:
1. Download the avr-libc package from:
1. Download the avr-libc package from:
http://savannah.nongnu.org/projects/avr-libc/
I am using avr-lib-1.7.1.tar.bz2
2. Upack the tarball and cd into the
2. Upack the tarball and cd into the
tar jxf avr-lib-1.7.1.tar.bz2
cd avr-lib-1.7.1
configs/amber/hello/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = $(ARCHINCLUDES) "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/hello/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem "$(TOPDIR)/include"
ARCHXXINCLUDES = $(ARCHINCLUDES) -isystem "$(TOPDIR)/include/cxx"
configs/amber/src/Makefile
+4 -4
View File
@@ -35,7 +35,7 @@
-include $(TOPDIR)/Make.defs
ASRCS =
ASRCS =
CSRCS = up_boot.c
ifeq ($(CONFIG_ARCH_LEDS),y)
@@ -58,13 +58,13 @@ endif
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}"
else
CFLAGS += -I "$(TOPDIR)/sched"
CFLAGS += -I "$(ARCH_SRCDIR)/chip"
CFLAGS += -I "$(ARCH_SRCDIR)/common"
CFLAGS += -I "$(ARCH_SRCDIR)/common"
CFLAGS += -I "$(ARCH_SRCDIR)/$(ARCH_SUBDIR)"
endif
configs/arduino-due/nsh/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/avr32dev1/README.txt
+8 -8
View File
@@ -155,7 +155,7 @@ IDEs
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project.
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
@@ -185,7 +185,7 @@ AVR32 Bootloader
Boot Sequence
-------------
"An AVR UC3 part having the bootloader programmed resets as any other
part at 80000000h. Bootloader execution begins here. The bootloader
first performs the boot process to know whether it should start the
@@ -193,7 +193,7 @@ AVR32 Bootloader
that the USB DFU ISP should be started, then execution continues in
the bootloader area, i.e. between 80000000h and 80002000h, else
the bootloader launches the application at 80002000h."
Link Address
------------
@@ -234,7 +234,7 @@ AVR32 Bootloader
will need to modify the setenv.sh files.
Notes from "AVR32 UC3 USB DFU Bootloader" (doc7745.pdf)
"To launch BatchISP, open a command prompt. Windows or Cygwin command
prompt can be used provided that the bin folder of the FLIP installation
directory is in the PATH (Windows’ or Cygwin’s) environment variable.
@@ -247,7 +247,7 @@ AVR32 Bootloader
"BatchISP works with an internal ISP buffer per target memory. These ISP
buffers can be filled from several sources. All target operations (program,
verify, read) are performed using these buffers."
The following BatchISP command line will erase FLASH, write the nuttx binary
into FLASH, and reset the AVR32. This command line is available in the
script config/avr32dev1/tools/doisp.sh:
@@ -256,7 +256,7 @@ AVR32 Bootloader
blankcheck loadbuffer nuttx.elf program verify start reset 0
"BatchISP main commands available on AT32UC3xxxxx are:
- ASSERT { PASS | FAIL } changes the displayed results of the following
operations according to the expected behavior.
- ONFAIL { ASK | ABORT | RETRY | IGNORE } changes the interactive behavior
@@ -325,7 +325,7 @@ Make Tip
changes when you run the program. That is because build is still using the
version of the file in the copied directory, not your modified file! To work
around this annoying behavior, do the following when you re-build:
make clean_context all <-- Remove and re-copy all of the directories, then make all
doisp.sh <-- Load the code onto the board.
@@ -401,7 +401,7 @@ AVR32DEV1 Configuration Options
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_AVR32_GPIOIRQ - GPIO interrupt support
CONFIG_AVR32_GPIOIRQSETA - Set of GPIOs on PORTA that support interrupts
CONFIG_AVR32_GPIOIRQSETB - Set of GPIOs on PORTB that support interrupts
configs/avr32dev1/nsh/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/nsh/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/avr32dev1/ostest/Make.defs
+1 -1
View File
@@ -60,7 +60,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/avr32dev1/src/Makefile
+1 -1
View File
@@ -37,7 +37,7 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
CSRCS = up_boot.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += up_leds.c
configs/avr32dev1/src/avr32dev1_internal.h
+3 -3
View File
@@ -53,15 +53,15 @@
#if (CONFIG_AVR32_GPIOIRQSETB & 4) == 1
# define CONFIG_AVR32DEV_BUTTON1_IRQ 1
#endif
#endif
#if (CONFIG_AVR32_GPIOIRQSETB & 8) == 1
# define CONFIG_AVR32DEV_BUTTON2_IRQ 1
#endif
#endif
/* AVRDEV1 GPIO Pin Definitions *****************************************************/
/* LEDs
*
*
* The AVR32DEV1 board has 3 LEDs, two of which can be controlled through GPIO pins.
*
* PIN 13 PA7 LED1
configs/avr32dev1/src/up_buttons.c
+1 -1
View File
@@ -79,7 +79,7 @@
static xcpt_t board_button_irqx(int irq, xcpt_t irqhandler)
{
xcpt_t oldhandler;
/* Attach the handler */
gpio_irqattach(irq, irqhandler, &oldhandler);
configs/c5471evm/doc/test-result.txt
+1 -1
View File
@@ -103,7 +103,7 @@ cond_test: signaler terminated, now cancel the waiter
cond_test: Waiter Signaler
cond_test: Loops 32 32
cond_test: Errors 0 0
cond_test:
cond_test:
0 times, waiter did not have to wait for data
cond_test: 0 times, data was already available when the signaler run
cond_test: 0 times, the waiter was in an unexpected state when the signaler ran
configs/c5471evm/src/Makefile
+1 -1
View File
@@ -37,7 +37,7 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_leds.c
COBJS = $(CSRCS:.c=$(OBJEXT))
configs/cloudctrl/README.txt
+7 -7
View File
@@ -2,7 +2,7 @@ README
======
This README discusses issues unique to NuttX configurations for the CloudController
development board featuring the STMicro STM32F107VCT MCU.
development board featuring the STMicro STM32F107VCT MCU.
Features of the CloudController board include:
@@ -392,7 +392,7 @@ NXFLAT Toolchain
tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can
be downloaded from the NuttX SourceForge download site
(https://sourceforge.net/projects/nuttx/files/).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
@@ -700,14 +700,14 @@ Cloudctrl-specific Configuration Options
STM32 USB OTG FS Host Driver Support
Pre-requisites
CONFIG_USBHOST - Enable USB host support
CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
CONFIG_STM32_SYSCFG - Needed
CONFIG_SCHED_WORKQUEUE - Worker thread support is required
Options:
CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
Default 128 (512 bytes)
CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
@@ -760,7 +760,7 @@ Where <subdir> is one of the following:
ADC1_IN10(PC0) Potentiometer
External signals are also available on CON5 CN14:
ADC_IN8 (PB0) CON5 CN14 Pin2
ADC_IN9 (PB1) CON5 CN14 Pin1
@@ -855,7 +855,7 @@ Where <subdir> is one of the following:
-CONFIG_NX_WRITEONLY=y
+# CONFIG_NX_WRITEONLY is not set
thttpd
------
configs/cloudctrl/include/board.h
+3 -3
View File
@@ -112,7 +112,7 @@
/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
*
* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
*/
#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
@@ -160,7 +160,7 @@
#define BUTTON_KEY2 1
#define BUTTON_KEY3 2
#define NUM_BUTTONS 3
#define BUTTON_USERKEY BUTTON_KEY1 /* Names in schematic */
#define BUTTON_TAMPER BUTTON_KEY2
#define BUTTON_WAKEUP BUTTON_KEY3
@@ -196,7 +196,7 @@
* 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
* 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
*
* The board desdign can support a 50MHz external clock to drive the PHY
* The board desdign can support a 50MHz external clock to drive the PHY
* (U9). However, on my board, U9 is not present.
*
* 67 PA8 MCO DM9161AEP
configs/cloudctrl/nsh/Make.defs
+1 -1
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@@ -54,7 +54,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/cloudctrl/src/Makefile
+1 -1
View File
@@ -38,7 +38,7 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c up_spi.c up_chipid.c
configs/cloudctrl/src/cloudctrl-internal.h
+1 -1
View File
@@ -84,7 +84,7 @@
* 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
* 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP
*
* The board desdign can support a 50MHz external clock to drive the PHY
* The board desdign can support a 50MHz external clock to drive the PHY
* (U9). However, on my board, U9 is not present.
*
* 67 PA8 MCO DM9161AEP
configs/cloudctrl/src/up_buttons.c
+1 -1
View File
@@ -88,7 +88,7 @@ void board_button_initialize(void)
{
int i;
/* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are
/* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are
* configured for some pins but NOT used in this file
*/
configs/cloudctrl/src/up_userleds.c
+2 -2
View File
@@ -76,9 +76,9 @@
****************************************************************************/
/* This array maps an LED number to GPIO pin configuration */
static uint32_t g_ledcfg[BOARD_NLEDS] =
static uint32_t g_ledcfg[BOARD_NLEDS] =
{
GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4
GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4
};
/****************************************************************************
configs/compal_e86/README.txt
+3 -3
View File
@@ -27,11 +27,11 @@ directory at same level as the nuttx project:
`- osmocom-bb
If you attempt to build this configuration without osmocom-bb, and that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
are needed from the osmocom-bb directory.
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
the host system. Sercomm is the transport used by osmocom-bb that runs on top
of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed
the usage of nuttx with sercomm.
configs/compal_e88/README.txt
+3 -3
View File
@@ -27,11 +27,11 @@ directory at same level as the nuttx project:
`- osmocom-bb
If you attempt to build this configuration without osmocom-bb, and that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
are needed from the osmocom-bb directory.
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
the host system. Sercomm is the transport used by osmocom-bb that runs on top
of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed
the usage of nuttx with sercomm.
configs/compal_e99/README.txt
+3 -3
View File
@@ -27,11 +27,11 @@ directory at same level as the nuttx project:
`- osmocom-bb
If you attempt to build this configuration without osmocom-bb, and that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y)
you will get compilation errors in drivers/sercomm due to header files that
are needed from the osmocom-bb directory.
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
By default, NuttX will not use sercomm (HDLC protocol) to communicate with
the host system. Sercomm is the transport used by osmocom-bb that runs on top
of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed
the usage of nuttx with sercomm.
configs/demo9s12ne64/README.txt
+2 -2
View File
@@ -314,12 +314,12 @@ HCS12/DEMO9S12NEC64-specific Configuration Options
the delay actually is 100 seconds.
GPIO Interrupts
CONFIG_GPIO_IRQ - Enable general support for GPIO IRQs
CONFIG_HCS12_PORTG_INTS - Enable PortG IRQs
CONFIG_HCS12_PORTH_INTS - Enable PortH IRQs
CONFIG_HCS12_PORTJ_INTS - Enable PortJ IRQs
HCS12 build options:
CONFIG_HCS12_SERIALMON - Indicates that the target systems uses
configs/demo9s12ne64/ostest/Make.defs
+1 -1
View File
@@ -65,7 +65,7 @@ ifeq ($(WINTOOL),y)
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/$(LDSCRIPT)}"
MAXOPTIMIZATION = -O2
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/demo9s12ne64/src/Makefile
+1 -1
View File
@@ -37,7 +37,7 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c
configs/ea3131/include/board.h
+3 -3
View File
@@ -66,7 +66,7 @@
#define BOARD_HPLL0_SELI 8 /* SELI bandwidth selection */
#define BOARD_HPLL0_SELP 31 /* SELP bandwidth selection */
#define BOARD_HPLL0_MODE 0 /* PLL mode */
#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
/* HPLL1 configuration */
@@ -78,12 +78,12 @@
#define BOARD_HPLL1_SELI 16 /* SELI bandwidth selection */
#define BOARD_HPLL1_SELP 8 /* SELP bandwidth selection */
#define BOARD_HPLL1_MODE 0 /* PLL mode */
#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
/* The following 3 bitsets determine which clocks will be enabled at initialization
* time.
*/
#define BOARD_CLKS_0_31 \
(_RBIT(CLKID_APB0CLK,0)|_RBIT(CLKID_APB1CLK,0)|_RBIT(CLKID_APB2CLK,0)|\
_RBIT(CLKID_APB3CLK,0)|_RBIT(CLKID_APB4CLK,0)|_RBIT(CLKID_AHB2INTCCLK,0)|\
configs/ea3131/include/board_memorymap.h
+1 -1
View File
@@ -58,7 +58,7 @@
* PGTABLE_BASE_VADDR - The mapped address of the page table in ROM, and
* Mappings for each of the PSECTIONS in lpc31_memorymap.h
*/
#ifdef CONFIG_ARCH_ROMPGTABLE
/* The LPC31xx ROM page table uses a 1-1 physical to virtual memory mapping */
configs/ea3131/locked/Makefile
+2 -2
View File
@@ -65,7 +65,7 @@ ifeq ($(WINTOOL),y)
PASS1_LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)$(DELIM)lib"}"
PASS1_LDSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)locked$(DELIM)ld-locked.inc}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
PASS1_LIBPATHS += -L"(TOPDIR)$(DELIM)lib"
PASS1_LDSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)locked$(DELIM)ld-locked.inc
endif
@@ -99,7 +99,7 @@ $(PASS1_LIBBOARD):
locked.r: ld-locked.inc $(PASS1_LIBBOARD)
@echo "LD: locked.r"
@$(LD) -o $@ $(PASS1_LDFLAGS) $(PASS1_LIBPATHS) --start-group $(PASS1_LDLIBS) --end-group $(PASS1_LIBGCC)
@$(LD) -o $@ $(PASS1_LDFLAGS) $(PASS1_LIBPATHS) --start-group $(PASS1_LDLIBS) --end-group $(PASS1_LIBGCC)
@$(NM) $@ > locked.map
@fgrep " U " locked.map | grep -v os_start
@$(CROSSDEV)size $@
configs/ea3131/nsh/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/ea3131/pgnsh/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/pg-ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/ea3131/src/up_fillpage.c
+7 -7
View File
@@ -96,15 +96,15 @@
#if defined(CONFIG_PAGING_M25PX) && defined(CONFIG_PAGING_AT45DB)
# error "Both CONFIG_PAGING_M25PX and CONFIG_PAGING_AT45DB are defined"
# undef CONFIG_PAGING_M25PX
# undef CONFIG_PAGING_M25PX
#endif
#if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_M25PX)
# error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_M25PX are defined"
# undef CONFIG_PAGING_BINPATH
# undef CONFIG_PAGING_BINPATH
#endif
#if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_AT45DB)
# error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_AT45DB are defined"
# undef CONFIG_PAGING_BINPATH
# undef CONFIG_PAGING_BINPATH
#endif
/* Are we accessing the page source data through a file path? */
@@ -260,7 +260,7 @@ static inline void lpc31_initsrc(void)
ret = mmcsd_slotinitialize(CONFIG_EA3131_PAGING_MINOR, sdio);
DEBUGASSERT(ret == OK);
/* Then let's guess and say that there is a card in the slot.
* (We are basically jodido anyway if there is no card in the slot).
*/
@@ -427,7 +427,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
lpc31_initsrc();
/* Create an offset into the binary image that corresponds to the
/* Create an offset into the binary image that corresponds to the
* virtual address. File offset 0 corresponds to PG_LOCKED_VBASE.
*/
@@ -437,7 +437,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
pos = lseek(g_pgsrc.fd, offset, SEEK_SET);
DEBUGASSERT(pos != (off_t)-1);
/* And read the page data from that offset */
nbytes = read(g_pgsrc.fd, vpage, PAGESIZE);
@@ -450,7 +450,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
lpc31_initsrc();
/* Create an offset into the binary image that corresponds to the
/* Create an offset into the binary image that corresponds to the
* virtual address. File offset 0 corresponds to PG_LOCKED_VBASE.
*/
configs/ea3131/src/up_mem.c
+14 -14
View File
@@ -110,7 +110,7 @@
*
* Micron Initialization Sequence from their data sheet for the Micron
* MT48LC32M16A2 32M x 16 SDRAM chip:
*
*
* "SDRAMs must be powered up and initialized in a predefined manner.
* Operational procedures other than those specified may result in
* undefined operation. Once power is applied to VDD and VDDQ
@@ -118,33 +118,33 @@
* a signal cycling within timing constraints specified for the clock
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
*
* "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
* be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.
*
*
* "Once in the idle state, two AUTO REFRESH cycles must be performed. After
* the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
* register programming.
*
*
* "Because the mode register will power up in an unknown state, it should
* be loaded prior to applying any operational command."
*
* The JEDEC recommendation for initializing SDRAM is:
*
*
* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
* Wait 200uS
* PRECHARGE all
* 8 AUTO REFRESH COMMANDS
* LOAD MODE REGISTER
* SDRAM is ready for operation
*
*
* The Micron SDRAM parts will work fine with the JEDEC sequence, but also
* allow for a quicker init sequence of:
*
*
* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
* Wait at least 100uS (during which time start applying and
* continue applying NOP or COMMAND INHIBIT)
@@ -221,7 +221,7 @@ static void lpc31_sdraminitialize(void)
putreg32(NS2HCLKS(EA3131_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK),
LPC31_MPMC_DYNTMRD);
up_udelay(100);
/* Issue continuous NOP commands */
putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP),
@@ -230,7 +230,7 @@ static void lpc31_sdraminitialize(void)
/* Wait ~200us */
up_udelay(200);
/* Issue a "pre-charge all" command */
putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL),
@@ -246,7 +246,7 @@ static void lpc31_sdraminitialize(void)
/* Wait ~250us */
up_udelay(250);
/* Recommended refresh interval for normal operation of the Micron
* MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
* refresh counter interval rate, (subtract one for safety margin).
@@ -267,7 +267,7 @@ static void lpc31_sdraminitialize(void)
*/
tmp = getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
LPC31_MPMC_DYNCONFIG0);
putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK),
@@ -303,7 +303,7 @@ static void lpc31_sdraminitialize(void)
void lpc31_meminitialize(void)
{
/* Configure the LCD pins in external bus interface (EBI/MPMC) memory mode.
*
*
* LCD_CSB -> MPMC_NSTCS_0
* LCD_DB_1 -> MPMC_NSTCS_1
* LCD_DB_0 -> MPMC_CLKOUT
@@ -331,7 +331,7 @@ void lpc31_meminitialize(void)
/* Enable EBI clock */
lpc31_enableclock(CLKID_EBICLK);
/* Enable MPMC controller clocks */
lpc31_enableclock(CLKID_MPMCCFGCLK);
@@ -351,7 +351,7 @@ void lpc31_meminitialize(void)
*/
putreg32(EA3131_MPMC_DELAY, LPC31_SYSCREG_MPMC_DELAYMODES);
/* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board */
lpc31_sdraminitialize();
configs/ea3131/src/up_nsh.c
+1 -1
View File
@@ -153,7 +153,7 @@ int nsh_archinitialize(void)
return ret;
}
message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n");
/* Then let's guess and say that there is a card in the slot. I need to check to
* see if the LPC313X10E-EVAL board supports a GPIO to detect if there is a card in
* the slot.
configs/ea3131/src/up_usbmsc.c
+1 -1
View File
@@ -98,7 +98,7 @@ int usbmsc_archinitialize(void)
}
/* Register a RAMDISK device to manage this RAM image */
ret = ramdisk_register(CONFIG_SYSTEM_USBMSC_DEVMINOR1,
pbuffer,
USBMSC_NSECTORS,
configs/ea3131/tools/crc32.c
+1 -1
View File
@@ -50,7 +50,7 @@
/************************************************************************************************
* Private Data
************************************************************************************************/
static const uint32_t crc32_tab[] =
{
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
configs/ea3131/tools/lpchdr.c
+2 -2
View File
@@ -273,7 +273,7 @@ int main(int argc, char **argv, char **envp)
padlen = g_hdr.imageLength - buf.st_size;
/* Calculate CRCs */
g_hdr.execution_crc32 = infilecrc32(infd, buf.st_size, padlen);
g_hdr.header_crc32 = crc32((const uint8_t*)&g_hdr, HDR_CRC_SIZE);
@@ -294,4 +294,4 @@ int main(int argc, char **argv, char **envp)
return 0;
}
configs/ea3131/tools/lpchdr.h
+1 -1
View File
@@ -69,7 +69,7 @@ struct lpc31_header_s
* 0xB – Do CRC32 check on both header and
* execution part of the image. */
uint32_t imageLength; /* 0x20 Total image length including header rounded
* up to the nearest 512 byte boundary. In C
* up to the nearest 512 byte boundary. In C
* language the field can be computed as:
* imageLength = (Actual length + 511) & ~0x1FF; */
uint32_t releaseID; /* 0x24 Release or version number of the image. Note,
configs/ea3131/usbserial/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/ea3152/README.txt
+3 -3
View File
@@ -92,7 +92,7 @@ GNU Toolchain Options
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
Generic arm-none-eabi GNU Toolchain
-----------------------------------
There are a number of toolchain projects providing support for ARMv4/v5
@@ -219,7 +219,7 @@ Image Format
- mklpc.sh # Make the bootloader binary (nuttx.lpc)
NOTES:
1. setenv.sh just sets up pathes to the toolchain and also to
configs/ea3152/tools where mklpc.sh resides. Use of setenv.sh is optional.
If you don't use setenv.sh, then just set your PATH variable appropriately or
@@ -265,7 +265,7 @@ Using OpenOCD and GDB
I used to start the OpenOCD daemon on my system called oocd.sh. That
script would probably require some modifications to work in another
environment:
- possibly the value of OPENOCD_PATH
- If you are working under Linux you will need to change any
occurances of `cygpath -w blablabla` to just blablabla
configs/ea3152/include/board.h
+3 -3
View File
@@ -66,7 +66,7 @@
#define BOARD_HPLL0_SELI 8 /* SELI bandwidth selection */
#define BOARD_HPLL0_SELP 31 /* SELP bandwidth selection */
#define BOARD_HPLL0_MODE 0 /* PLL mode */
#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
/* HPLL1 configuration */
@@ -78,12 +78,12 @@
#define BOARD_HPLL1_SELI 16 /* SELI bandwidth selection */
#define BOARD_HPLL1_SELP 8 /* SELP bandwidth selection */
#define BOARD_HPLL1_MODE 0 /* PLL mode */
#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
/* The following 3 bitsets determine which clocks will be enabled at initialization
* time.
*/
#define BOARD_CLKS_0_31 \
(_RBIT(CLKID_APB0CLK,0)|_RBIT(CLKID_APB1CLK,0)|_RBIT(CLKID_APB2CLK,0)|\
_RBIT(CLKID_APB3CLK,0)|_RBIT(CLKID_APB4CLK,0)|_RBIT(CLKID_AHB2INTCCLK,0)|\
configs/ea3152/include/board_memorymap.h
+1 -1
View File
@@ -58,7 +58,7 @@
* PGTABLE_BASE_VADDR - The mapped address of the page table in ROM, and
* Mappings for each of the PSECTIONS in lpc31_memorymap.h
*/
#ifdef CONFIG_ARCH_ROMPGTABLE
/* The LPC31xx ROM page table uses a 1-1 physical to virtual memory mapping */
configs/ea3152/ostest/Make.defs
+1 -1
View File
@@ -46,7 +46,7 @@ ifeq ($(WINTOOL),y)
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}"
else
# Linux/Cygwin-native toolchain
# Linux/Cygwin-native toolchain
MKDEP = $(TOPDIR)/tools/mkdeps.sh
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
configs/ea3152/src/Makefile
+1 -1
View File
@@ -37,7 +37,7 @@
CFLAGS += -I$(TOPDIR)/sched
ASRCS =
ASRCS =
AOBJS = $(ASRCS:.S=$(OBJEXT))
CSRCS = up_boot.c up_clkinit.c
configs/ea3152/src/up_fillpage.c
+7 -7
View File
@@ -96,15 +96,15 @@
#if defined(CONFIG_PAGING_M25PX) && defined(CONFIG_PAGING_AT45DB)
# error "Both CONFIG_PAGING_M25PX and CONFIG_PAGING_AT45DB are defined"
# undef CONFIG_PAGING_M25PX
# undef CONFIG_PAGING_M25PX
#endif
#if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_M25PX)
# error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_M25PX are defined"
# undef CONFIG_PAGING_BINPATH
# undef CONFIG_PAGING_BINPATH
#endif
#if defined(CONFIG_PAGING_BINPATH) && defined(CONFIG_PAGING_AT45DB)
# error "Both CONFIG_PAGING_BINPATH and CONFIG_PAGING_AT45DB are defined"
# undef CONFIG_PAGING_BINPATH
# undef CONFIG_PAGING_BINPATH
#endif
/* Are we accessing the page source data through a file path? */
@@ -260,7 +260,7 @@ static inline void lpc31_initsrc(void)
ret = mmcsd_slotinitialize(CONFIG_EA3152_PAGING_MINOR, sdio);
DEBUGASSERT(ret == OK);
/* Then let's guess and say that there is a card in the slot.
* (We are basically jodido anyway if there is no card in the slot).
*/
@@ -427,7 +427,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
lpc31_initsrc();
/* Create an offset into the binary image that corresponds to the
/* Create an offset into the binary image that corresponds to the
* virtual address. File offset 0 corresponds to PG_LOCKED_VBASE.
*/
@@ -437,7 +437,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
pos = lseek(g_pgsrc.fd, offset, SEEK_SET);
DEBUGASSERT(pos != (off_t)-1);
/* And read the page data from that offset */
nbytes = read(g_pgsrc.fd, vpage, PAGESIZE);
@@ -450,7 +450,7 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage)
lpc31_initsrc();
/* Create an offset into the binary image that corresponds to the
/* Create an offset into the binary image that corresponds to the
* virtual address. File offset 0 corresponds to PG_LOCKED_VBASE.
*/
configs/ea3152/src/up_mem.c
+14 -14
View File
@@ -110,7 +110,7 @@
*
* Micron Initialization Sequence from their data sheet for the Micron
* MT48LC32M16A2 32M x 16 SDRAM chip:
*
*
* "SDRAMs must be powered up and initialized in a predefined manner.
* Operational procedures other than those specified may result in
* undefined operation. Once power is applied to VDD and VDDQ
@@ -118,33 +118,33 @@
* a signal cycling within timing constraints specified for the clock
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
*
* "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
* be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.
*
*
* "Once in the idle state, two AUTO REFRESH cycles must be performed. After
* the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
* register programming.
*
*
* "Because the mode register will power up in an unknown state, it should
* be loaded prior to applying any operational command."
*
* The JEDEC recommendation for initializing SDRAM is:
*
*
* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
* Wait 200uS
* PRECHARGE all
* 8 AUTO REFRESH COMMANDS
* LOAD MODE REGISTER
* SDRAM is ready for operation
*
*
* The Micron SDRAM parts will work fine with the JEDEC sequence, but also
* allow for a quicker init sequence of:
*
*
* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
* Wait at least 100uS (during which time start applying and
* continue applying NOP or COMMAND INHIBIT)
@@ -221,7 +221,7 @@ static void lpc31_sdraminitialize(void)
putreg32(NS2HCLKS(EA3152_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK),
LPC31_MPMC_DYNTMRD);
up_udelay(100);
/* Issue continuous NOP commands */
putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP),
@@ -230,7 +230,7 @@ static void lpc31_sdraminitialize(void)
/* Load ~200us delay value to timer1 */
up_udelay(200);
/* Issue a "pre-charge all" command */
putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL),
@@ -246,7 +246,7 @@ static void lpc31_sdraminitialize(void)
/* Load ~250us delay value to timer1 */
up_udelay(250);
/* Recommended refresh interval for normal operation of the Micron
* MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
* refresh counter interval rate, (subtract one for safety margin).
@@ -267,7 +267,7 @@ static void lpc31_sdraminitialize(void)
*/
tmp = getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
LPC31_MPMC_DYNCONFIG0);
putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK),
@@ -303,7 +303,7 @@ static void lpc31_sdraminitialize(void)
void lpc31_meminitialize(void)
{
/* Configure the LCD pins in external bus interface (EBI/MPMC) memory mode.
*
*
* LCD_CSB -> MPMC_NSTCS_0
* LCD_DB_1 -> MPMC_NSTCS_1
* LCD_DB_0 -> MPMC_CLKOUT
@@ -331,7 +331,7 @@ void lpc31_meminitialize(void)
/* Enable EBI clock */
lpc31_enableclock(CLKID_EBICLK);
/* Enable MPMC controller clocks */
lpc31_enableclock(CLKID_MPMCCFGCLK);
@@ -351,7 +351,7 @@ void lpc31_meminitialize(void)
*/
putreg32(EA3152_MPMC_DELAY, LPC31_SYSCREG_MPMC_DELAYMODES);
/* Configure Micron MT48LC32M16A2 SDRAM on the EA3152 board */
lpc31_sdraminitialize();
configs/ea3152/src/up_nsh.c
+1 -1
View File
@@ -153,7 +153,7 @@ int nsh_archinitialize(void)
return ret;
}
message("nsh_archinitialize: Successfully bound SDIO to the MMC/SD driver\n");
/* Then let's guess and say that there is a card in the slot. I need to check to
* see if the LPC313X10E-EVAL board supports a GPIO to detect if there is a card in
* the slot.
configs/ea3152/src/up_usbmsc.c
+1 -1
View File
@@ -98,7 +98,7 @@ int usbmsc_archinitialize(void)
}
/* Register a RAMDISK device to manage this RAM image */
ret = ramdisk_register(CONFIG_SYSTEM_USBMSC_DEVMINOR1,
pbuffer,
USBMSC_NSECTORS,

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