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More naming changes associated with earlier renaming of LP17xx up_spiinitialize; LPC178x SSP support; Open1788 SSP and touchscreen support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5811 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -312,15 +312,15 @@
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#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT)
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#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */
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#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT )
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#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
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#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
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#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT)
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#define IOCON_INV_SHIFT (6) /* Bit 6: Typ D,A,I,W */
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#define IOCON_INV_SHIFT (6) /* Bit 6: Type D,A,I,W */
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#define IOCON_INV_MASK (1 << IOCON_INV_SHIFT)
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#define IOCON_ADMODE_SHIFT (7) /* Bit 7: Type A */
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#define IOCON_ADMODE_MASK (1 << IOCON_ADMODE_SHIFT)
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#define IOCON_FILTER_SHIFT (8) /* Bit 8: Type A */
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#define IOCON_FILTER_MASK (1 << IOCON_FILTER_SHIFT)
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#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W*/
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#define IOCON_SLEW_SHIFT (9) /* Bit 9: Type W */
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#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT)
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#define IOCON_HIDRIVE_SHIFT (9) /* Bit 9: Type I */
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#define IOCON_HIDRIVE_MASK (1 << IOCON_HIDRIVE_SHIFT)
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@@ -193,7 +193,7 @@
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#define GPIO_IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
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#define GPIO_IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
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#define GPIO_IOCON_MASK (0x00FF0000)
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#define GPIO_IOCON_MASK (0x00ff0000)
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# define GPIO_HYSTERESIS (1 << 16) /* Bit 16: HYSTERESIS: 0-Disable, 1-Enabled */
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# define GPIO_INVERT (1 << 17) /* Bit 17: Input: 0-Not Inverted, 1-Inverted */
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# define GPIO_SLEW (1 << 18) /* Bit 18: Rate Control: 0-Standard mode, 1-Fast mode */
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@@ -259,7 +259,7 @@
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#define GPIO_VALUE_ONE GPIO_VALUE
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#define GPIO_VALUE_ZERO (0)
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/* Port number: PPP (0-5) */
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/* Port number: PPP (0-5) */
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#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
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#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
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@@ -272,7 +272,7 @@
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#define GPIO_NPORTS 6
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/* Pin number: NNNNN (0-31) */
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/* Pin number: NNNNN (0-31) */
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#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
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#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
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@@ -58,7 +58,8 @@
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#include "lpc17_gpio.h"
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#include "lpc17_ssp.h"
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#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
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#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) || \
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defined(CONFIG_LPC17_SSP2)
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/****************************************************************************
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* Definitions
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@@ -91,6 +92,7 @@
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#endif
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/* SSP Clocking *************************************************************/
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#if defined(LPC176x)
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/* The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK).
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* SSP_CLOCK may be further divided by 2-254 to get the SSP clock. If we
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* want a usable range of 4KHz to 25MHz for the SSP, then:
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@@ -102,12 +104,22 @@
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* use the CCLK undivided to get the SSP_CLOCK.
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*/
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#if LPC17_CCLK > 100000000
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# error "CCLK <= 100,000,000 assumed"
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#endif
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# if LPC17_CCLK > 100000000
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# error "CCLK <= 100,000,000 assumed"
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# endif
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#define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
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#define SSP_CLOCK LPC17_CCLK
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# define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
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# define SSP_CLOCK LPC17_CCLK
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/* All peripherals are clocked by the same peripheral clock in the LPC178x
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* family.
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*/
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#elif defined(LPC178x)
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# define SSP_CLOCK BOARD_PCLK_FREQUENCY
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#endif
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/****************************************************************************
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* Private Types
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@@ -161,6 +173,9 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void);
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#ifdef CONFIG_LPC17_SSP1
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void);
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#endif
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#ifdef CONFIG_LPC17_SSP2
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void);
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#endif
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/****************************************************************************
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* Private Data
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@@ -234,6 +249,40 @@ static struct lpc17_sspdev_s g_ssp1dev =
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};
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#endif /* CONFIG_LPC17_SSP1 */
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#ifdef CONFIG_LPC17_SSP2
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static const struct spi_ops_s g_spi2ops =
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{
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#ifndef CONFIG_SPI_OWNBUS
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.lock = ssp_lock,
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#endif
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.select = lpc17_ssp2select, /* Provided externally */
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.setfrequency = ssp_setfrequency,
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.setmode = ssp_setmode,
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.setbits = ssp_setbits,
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.status = lpc17_ssp2status, /* Provided externally */
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = lpc17_ssp2cmddata, /* Provided externally */
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#endif
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.send = ssp_send,
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.sndblock = ssp_sndblock,
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.recvblock = ssp_recvblock,
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#ifdef CONFIG_SPI_CALLBACK
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.registercallback = lpc17_ssp2register, /* Provided externally */
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#else
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.registercallback = 0, /* Not implemented */
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#endif
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};
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static struct lpc17_sspdev_s g_ssp2dev =
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{
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.spidev = { &g_spi2ops },
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.sspbase = LPC17_SSP2_BASE,
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#ifdef CONFIG_LPC17_SSP_INTERRUPTS
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.sspirq = LPC17_IRQ_SSP2,
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#endif
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};
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#endif /* CONFIG_LPC17_SSP2 */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@@ -741,10 +790,12 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp0initialize(void)
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/* Configure clocking */
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#ifdef LPC176x
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regval = getreg32(LPC17_SYSCON_PCLKSEL1);
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regval &= ~SYSCON_PCLKSEL1_SSP0_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL1);
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#endif
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/* Enable peripheral clocking to SSP0 */
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@@ -793,10 +844,12 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void)
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/* Configure clocking */
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#ifdef LPC176x
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regval = getreg32(LPC17_SYSCON_PCLKSEL0);
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regval &= ~SYSCON_PCLKSEL0_SSP1_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL0);
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#endif
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/* Enable peripheral clocking to SSP0 and SSP1 */
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@@ -809,6 +862,59 @@ static inline FAR struct lpc17_sspdev_s *lpc17_ssp1initialize(void)
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}
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#endif
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/****************************************************************************
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* Name: lpc17_ssp2initialize
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*
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* Description:
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* Initialize the SSP2
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*
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* Input Parameter:
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* None
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*
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* Returned Value:
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* Valid SPI device structure reference on succcess; a NULL on failure
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*
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****************************************************************************/
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#ifdef CONFIG_LPC17_SSP2
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static inline FAR struct lpc17_sspdev_s *lpc17_ssp2initialize(void)
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{
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irqstate_t flags;
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uint32_t regval;
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/* Configure multiplexed pins as connected on the board. Chip select
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* pins must be configured by board-specific logic. All SSP2 pins have
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* multiple, alternative pin selection. Definitions in the board.h file
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* must be provided to resolve the board-specific pin configuration like:
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*
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* #define GPIO_SSP2_SCK GPIO_SSP2_SCK_1
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*/
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flags = irqsave();
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lpc17_configgpio(GPIO_SSP2_SCK);
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lpc17_configgpio(GPIO_SSP2_MISO);
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lpc17_configgpio(GPIO_SSP2_MOSI);
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/* Configure clocking */
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#ifdef LPC176x
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regval = getreg32(LPC17_SYSCON_PCLKSEL0);
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regval &= ~SYSCON_PCLKSEL0_SSP2_MASK;
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regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP2_SHIFT);
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putreg32(regval, LPC17_SYSCON_PCLKSEL0);
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#endif
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/* Enable peripheral clocking to SSP0 and SSP1 */
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regval = getreg32(LPC17_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCSSP2;
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putreg32(regval, LPC17_SYSCON_PCONP);
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irqrestore(flags);
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return &g_ssp2dev;
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -846,6 +952,11 @@ FAR struct spi_dev_s *lpc17_sspinitialize(int port)
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case 1:
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priv = lpc17_ssp1initialize();
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break;
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#endif
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#ifdef CONFIG_LPC17_SSP2
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case 2:
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priv = lpc17_ssp2initialize();
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break;
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#endif
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default:
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return NULL;
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