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arch/risc-v/src: Fix nxstyle warnings

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No functional changes
This commit is contained in:
Yoshinori Sugino
2020-10-10 16:31:53 +09:00
committed by Abdelatif Guettouche
parent 20f701f2ec
commit aae4e15d9b
24 changed files with 332 additions and 277 deletions
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arch/risc-v/src/fe310/fe310_clockconfig.h
+1 -1
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@@ -65,7 +65,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
EXTERN uint32_t fe310_get_hfclk(void);
arch/risc-v/src/fe310/fe310_lowputc.h
+1 -1
View File
@@ -45,7 +45,7 @@
#include "chip.h"
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
arch/risc-v/src/gap8/gap8.h
+123 -106
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File diff suppressed because it is too large Load Diff
arch/risc-v/src/gap8/gap8_fll.c
+15 -15
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@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/gap8/gap8_fll.c
* GAP8 FLL clock generator
*
@@ -32,30 +32,30 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
* is 1.2V, it's okay to boost up without considering PMU.
************************************************************************************/
/****************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage
* of PMU is 1.2V, it's okay to boost up without considering PMU.
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include "gap8_fll.h"
/************************************************************************************
/****************************************************************************
* Pre-Processor Declarations
************************************************************************************/
****************************************************************************/
/* Log2(FLL_REF_CLK=32768) */
#define LOG2_REFCLK 15
/************************************************************************************
* Public Function
************************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gap8_setfreq
@@ -103,7 +103,7 @@ void gap8_setfreq(uint32_t frequency)
}
while (mult_factor_diff > 0x10);
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0xB) |
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0xb) |
FLL_CTRL_CONF2_DEASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_ASSERT_CYCLES(0x10) |
FLL_CTRL_CONF2_LOCK_TOLERANCE(0x100) |
@@ -124,5 +124,5 @@ uint32_t gap8_getfreq(void)
{
/* FreqOut = Fref * mult/2^(div-1), where div = 1 */
return FLL_REF_CLK * (FLL_CTRL->SOC_FLL_STATUS & 0xFFFF);
return FLL_REF_CLK * (FLL_CTRL->SOC_FLL_STATUS & 0xffff);
}
arch/risc-v/src/gap8/gap8_fll.h
+10 -10
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/gap8/gap8_fll.h
* GAP8 FLL clock generator
*
@@ -32,25 +32,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
* is 1.2V, it's okay to boost up without considering PMU.
************************************************************************************/
/****************************************************************************
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage
* of PMU is 1.2V, it's okay to boost up without considering PMU.
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_GAP8_FLL_H
#define __ARCH_RISC_V_SRC_GAP8_FLL_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include "gap8.h"
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: gap8_setfreq
arch/risc-v/src/gap8/gap8_gpio.c
+22 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/gap8/gap8_gpio.c
* GAP8 FLL clock generator
*
@@ -32,16 +32,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* GAP8 has only 1 port. Each pin could be configured to GPIO or alternative
* functions.
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include "gap8_gpio.h"
/************************************************************************************
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gap8_configpin
*
* Description:
@@ -57,7 +65,7 @@
* OK on success
* ERROR on invalid pin.
*
************************************************************************************/
****************************************************************************/
int gap8_configpin(uint32_t cfgset)
{
@@ -120,7 +128,7 @@ int gap8_configpin(uint32_t cfgset)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: gap8_gpiowrite
*
* Description:
@@ -132,7 +140,7 @@ int gap8_configpin(uint32_t cfgset)
* | --- | GPIOn | --- |
* | --- | 5-bit | --- |
*
************************************************************************************/
****************************************************************************/
void gap8_gpiowrite(uint32_t pinset, bool value)
{
@@ -147,7 +155,7 @@ void gap8_gpiowrite(uint32_t pinset, bool value)
}
}
/************************************************************************************
/****************************************************************************
* Name: gap8_gpioread
*
* Description:
@@ -159,7 +167,7 @@ void gap8_gpiowrite(uint32_t pinset, bool value)
* | --- | GPIOn | --- |
* | --- | 5-bit | --- |
*
************************************************************************************/
****************************************************************************/
bool gap8_gpioread(uint32_t pinset)
{
@@ -167,7 +175,7 @@ bool gap8_gpioread(uint32_t pinset)
return (GPIOA->IN >> gpio_n) & 0x1;
}
/************************************************************************************
/****************************************************************************
* Name: gap8_gpioirqset
*
* Description:
@@ -179,13 +187,14 @@ bool gap8_gpioread(uint32_t pinset)
* | --- | int-typ | --- | GPIOn | --- |
* | --- | 2-bit | --- | 5-bit | --- |
*
************************************************************************************/
****************************************************************************/
void gap8_gpioirqset(uint32_t pinset, bool enable)
{
uint32_t gpio_n = (pinset >> 10) & 0x1f;
uint32_t int_type = (pinset >> 18) * 0x3;
uint32_t tmp, shitfcnt;
uint32_t tmp;
uint32_t shitfcnt;
if (enable)
{
arch/risc-v/src/gap8/gap8_interrupt.c
+15 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/gap8/gap8_interrupt.c
* GAP8 event system
*
@@ -32,18 +32,18 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals have
* unique ID, which are dispatched to the FC or cluster by the SOC event unit, and
* then by the FC event unit or cluster event unit, and finally to FC or cluster.
* Peripherals share the same IRQ entry.
************************************************************************************/
/****************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals
* have unique ID, which are dispatched to the FC or cluster by the SOC
* event unit, and then by the FC event unit or cluster event unit, and
* finally to FC or cluster. Peripherals share the same IRQ entry.
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/irq.h>
#include <nuttx/arch.h>
@@ -58,9 +58,9 @@
volatile uint32_t *g_current_regs;
/************************************************************************************
* Public Function
************************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/* Function exported to the Nuttx kernel */
@@ -100,8 +100,8 @@ void up_irqinitialize(void)
{
/* Deactivate all the soc events */
SOC_EU->FC_MASK_MSB = 0xFFFFFFFF;
SOC_EU->FC_MASK_LSB = 0xFFFFFFFF;
SOC_EU->FC_MASK_MSB = 0xffffffff;
SOC_EU->FC_MASK_LSB = 0xffffffff;
/* enable soc peripheral interrupt */
arch/risc-v/src/gap8/gap8_tim.c
+8 -8
View File
@@ -34,15 +34,15 @@
*
****************************************************************************/
/************************************************************************************
* FC core has a 64-bit basic timer, able to split into 2 32-bit timers, with
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
* use it as system timer.
************************************************************************************/
/****************************************************************************
* FC core has a 64-bit basic timer, able to split into 2 32-bit timers,
* with identicle memory map and 2 IRQ channels, for both FC core and
* cluster. We would use it as system timer.
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
@@ -56,7 +56,7 @@
struct gap8_tim_instance
{
BASIC_TIM_reg_t *reg;
basic_tim_reg_t *reg;
uint32_t core_clock;
};
arch/risc-v/src/gap8/gap8_tim.h
+11 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/gap8/gap8_tim.h
* PIN driver for GAP8
*
@@ -32,26 +32,26 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
* GAP8 features a 64-bit basic timer, able to split into 2 32-bit timers, with
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
* use it as system timer.
************************************************************************************/
/****************************************************************************
* GAP8 features a 64-bit basic timer, able to split into 2 32-bit timers,
* with identicle memory map and 2 IRQ channels, for both FC core and
* cluster. We would use it as system timer.
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_GAP8_TIM_H
#define __ARCH_RISC_V_SRC_GAP8_TIM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include "gap8.h"
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: gap8_timer_initialize
arch/risc-v/src/gap8/gap8_uart.c
+8 -7
View File
@@ -34,7 +34,7 @@
*
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* This UART IP has no flow control. So ioctl is limited.
* Note that here we don't use the uDMA to send multiple bytes, because
* Nuttx serial drivers don't have abstraction for puts().
@@ -157,7 +157,7 @@ static struct gap8_uart_t gap8_uarts[GAP8_NR_UART] =
{
.udma =
{
.regs = (UDMA_reg_t *)UART,
.regs = (udma_reg_t *)UART,
.id = GAP8_UDMA_ID_UART,
.on_tx = uart_tx_isr,
.tx_arg = &g_uart0port,
@@ -197,7 +197,7 @@ static uart_dev_t g_uart0port =
{
.size = CONFIG_UART_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
},
.ops = &g_uart_ops,
.priv = &gap8_uarts[0],
};
@@ -246,7 +246,7 @@ static void uart_rx_isr(void *arg)
static int up_setup(struct uart_dev_s *dev)
{
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
UART_reg_t *uartreg = (UART_reg_t *)the_uart->udma.regs;
uart_reg_t *uartreg = (uart_reg_t *)the_uart->udma.regs;
uint32_t cfgreg = 0;
if (the_uart->is_initialized == 0)
@@ -303,14 +303,15 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* interrupts are not enabled until the txint() and rxint() methods are
* called.
*
****************************************************************************/
@@ -331,7 +332,7 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception
* closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
*
****************************************************************************/
arch/risc-v/src/gap8/gap8_udma.c
+6 -3
View File
@@ -75,7 +75,10 @@
* The peripheral driver instantiate it and register through _init()
*/
static struct gap8_udma_peripheral *_peripherals[GAP8_UDMA_NR_CHANNELS] = { 0 };
static struct gap8_udma_peripheral *_peripherals[GAP8_UDMA_NR_CHANNELS] =
{
0
};
/****************************************************************************
* Private Functions
@@ -294,7 +297,7 @@ int gap8_udma_rx_poll(struct gap8_udma_peripheral *instance)
* Description:
* uDMA ISR
*
***************************************************************************/
****************************************************************************/
int gap8_udma_doirq(int irq, void *context, FAR void *arg)
{
@@ -349,7 +352,7 @@ int gap8_udma_doirq(int irq, void *context, FAR void *arg)
{
/* Rx channel */
if (the_peripheral->rx.block_count > 1)
if (the_peripheral->rx.block_count > 1)
{
the_peripheral->rx.block_count--;
the_peripheral->rx.buff += the_peripheral->rx.block_size;
arch/risc-v/src/gap8/gap8_udma.h
+1 -1
View File
@@ -102,7 +102,7 @@ struct gap8_udma_peripheral
{
/* Public */
UDMA_reg_t *regs; /* Hardware config regs */
udma_reg_t *regs; /* Hardware config regs */
uint32_t id; /* GAP8_UDMA_ID_x */
void (*on_tx)(void *arg); /* tx callback */
void (*on_rx)(void *arg); /* rx callback */
arch/risc-v/src/k210/k210_lowputc.h
+1 -1
View File
@@ -45,7 +45,7 @@
#include "chip.h"
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
arch/risc-v/src/nr5m100/hardware/nr5m1xx_timer.h
+7 -3
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/nr5m100/hardware/nr5_timer.h
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -28,11 +28,15 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "nr5m1xx_memorymap.h"
/* The timers used in the NR5M100 are functionally equivalent to
@@ -122,7 +126,7 @@
#define NR5_TIMER5_TAIV_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************************/
/* Register Bitfield Definitions ********************************************/
/* Control register TACTL Bit definitions */
arch/risc-v/src/nr5m100/nr5_arch.c
+13 -5
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/nr5m100/nr5_arch.c
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -28,15 +28,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <string.h>
#include <nuttx/arch.h>
#include "nr5.h"
/****************************************************************************
* Public Functions
****************************************************************************/
void up_puts(const char *p)
{
while (*p != 0)
up_lowputc(*(p++));
up_lowputc('\n');
while (*p != 0)
up_lowputc(*(p++));
up_lowputc('\n');
}
arch/risc-v/src/nr5m100/nr5_config.h
+2 -1
View File
@@ -53,6 +53,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* UARTs ****************************************************************************/
/* Are any UARTs enabled? */
@@ -91,7 +92,7 @@
************************************************************************************/
/************************************************************************************
* Public Functions
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */
arch/risc-v/src/nr5m100/nr5_custom_ops.h
+6 -6
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/nr5m100/nr5_custom_ops.h
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -28,7 +28,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
@@ -44,17 +44,17 @@
****************************************************************************/
.macro getq rd qs
custom0 \rd,\qs,0,0
custom0 \rd, \qs, 0, 0
.endm
.macro setq qd rs
custom0 \qd,\rs,0,1
custom0 \qd, \rs, 0, 1
.endm
.macro lsbenc rd rs
custom0 \rd,\rs,0,2
custom0 \rd, \rs, 0, 2
.endm
.macro timer rd rs
custom0 \rd,\rs,0,5
custom0 \rd, \rs, 0, 5
.endm
arch/risc-v/src/nr5m100/nr5_init.c
+1 -1
View File
@@ -70,5 +70,5 @@ void __nr5_init(void)
/* Shouldn't get here */
for (;;);
for (; ; );
}
arch/risc-v/src/nr5m100/nr5_irq.c
+26 -26
View File
@@ -76,27 +76,27 @@ volatile uint32_t *g_current_regs;
void epic_dump(void)
{
uint32_t reg;
char str[40];
uint32_t reg;
char str[40];
__asm__ volatile("csrr %0, 0x7e0" : "=r"(reg));
sprintf(str, "IRQMASK = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e4" : "=r"(reg));
sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e1" : "=r"(reg));
sprintf(str, "PRI1 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e2" : "=r"(reg));
sprintf(str, "PRI2 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e3" : "=r"(reg));
sprintf(str, "PRI3 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e5" : "=r"(reg));
sprintf(str, "SYSTICK = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e0" : "=r"(reg));
sprintf(str, "IRQMASK = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e4" : "=r"(reg));
sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e1" : "=r"(reg));
sprintf(str, "PRI1 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e2" : "=r"(reg));
sprintf(str, "PRI2 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e3" : "=r"(reg));
sprintf(str, "PRI3 = 0x%08X\r", (int) reg);
up_puts(str);
__asm__ volatile("csrr %0, 0x7e5" : "=r"(reg));
sprintf(str, "SYSTICK = 0x%08X\r", (int) reg);
up_puts(str);
}
/****************************************************************************
@@ -151,11 +151,11 @@ void up_irqinitialize(void)
/* Colorize the interrupt stack for debug purposes */
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
intstack_size);
}
{
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase -
intstack_size), intstack_size);
}
#endif
/* Set the location of the vector table */
@@ -168,7 +168,7 @@ void up_irqinitialize(void)
csrw %1, 0(zero) \
csrw %2, 0(zero) " ::
"i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG),
"i"(NR5_EPIC_PRI3_REG) );
"i"(NR5_EPIC_PRI3_REG));
#endif
/* Initialize the IRQ stack to Pri level 5 with interrupts disabled */
arch/risc-v/src/nr5m100/nr5_lowputc.h
+2 -1
View File
@@ -53,7 +53,8 @@
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
extern "C"
{
#else
#define EXTERN extern
#endif
arch/risc-v/src/nr5m100/nr5_memorymap.h
+7 -3
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/nr5m100/nr5_memorymap.h
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -28,12 +28,16 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
#define _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
//#include <stdint.h>
/****************************************************************************
* Included Files
****************************************************************************/
/* #include <stdint.h> */
#ifdef CONFIG_NR5_NR5MXXX
#include "hardware/nr5m1xx_memorymap.h"
arch/risc-v/src/nr5m100/nr5_timer.h
+17 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/risc-v/src/nr5m100/nr5_timer.h
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
@@ -33,24 +33,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
#define __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/nr5m1xx_timer.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Helpers **************************************************************************/
****************************************************************************/
/* Helpers ******************************************************************/
#define NR5_TIMER_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define NR5_TIMER_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
@@ -61,9 +62,9 @@
#define NR5_TIMER_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define NR5_TIMER_ACKINT(d,s) ((d)->ops->ackint(d,s))
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -95,7 +96,6 @@ typedef enum
NR5_TIM_MODE_CK_MED = 0x0010,
NR5_TIM_MODE_CK_SYS = 0x0020,
NR5_TIM_MODE_CK_EXT = 0x0030,
} nr5_timer_mode_t;
/* Timer Operations */
@@ -112,7 +112,8 @@ struct nr5_timer_ops_s
/* Timer Interrupt Operations */
int (*setisr)(FAR struct nr5_timer_dev_s *dev, xcpt_t handler, void *arg, int source);
int (*setisr)(FAR struct nr5_timer_dev_s *dev, xcpt_t handler, void *arg,
int source);
void (*enableint)(FAR struct nr5_timer_dev_s *dev, int source);
void (*disableint)(FAR struct nr5_timer_dev_s *dev, int source);
void (*ackint)(FAR struct nr5_timer_dev_s *dev, int source);
@@ -125,9 +126,9 @@ struct nr5_timer_dev_s
struct nr5_timer_ops_s *ops;
};
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Power-up timer and get its structure */
@@ -145,7 +146,8 @@ int nr5_timer_deinit(FAR struct nr5_timer_dev_s *dev);
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* devpath - The full path to the timer device. This should be of the form
* /dev/timer0
* timer - the timer number.
*
* Returned Value:
arch/risc-v/src/nr5m100/nr5_uart.c
+23 -22
View File
@@ -62,13 +62,13 @@ struct nr5_uart_buffer_s
struct nr5_uart_regs_s
{
uint32_t* pbaud; /* Data status port */
uint32_t* pstat; /* Data status port */
uint8_t* ptx; /* Data TX port */
uint8_t* prx; /* Data RX port */
uint32_t* pintctrl; /* Interrupt enable control */
int rxirq; /* IRQ number */
int txirq; /* IRQ number */
uint32_t *pbaud; /* Data status port */
uint32_t *pstat; /* Data status port */
uint8_t *ptx; /* Data TX port */
uint8_t *prx; /* Data RX port */
uint32_t *pintctrl; /* Interrupt enable control */
int rxirq; /* IRQ number */
int txirq; /* IRQ number */
};
struct nr5_uart_s
@@ -183,8 +183,9 @@ void nr5_uart_init(int uart)
{
/* Attach the ISR and enable the IRQ with the EPIC */
//irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL);
//up_enable_irq(dev->regs->rxirq);
/* irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL); */
/* up_enable_irq(dev->regs->rxirq); */
/* Set the baud rate */
@@ -195,7 +196,7 @@ void nr5_uart_init(int uart)
/* Now enable the RX IRQ in the UART peripheral */
//*dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ;
/* *dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ; */
}
}
@@ -208,11 +209,11 @@ uint8_t nr5_uart_get_rx()
up_disableints();
if (g_nr5_uart1.rxbuf->head != g_nr5_uart1.rxbuf->tail)
{
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
rxdata = pBuf->buffer[pBuf->tail++];
if (pBuf->tail == pBuf->size)
pBuf->tail = 0;
rxdata = pbuf->buffer[pbuf->tail++];
if (pbuf->tail == pbuf->size)
pbuf->tail = 0;
}
up_enableints();
@@ -223,11 +224,11 @@ uint8_t nr5_uart_get_rx()
int nr5_uart_test_rx_avail()
{
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
int avail;
up_disableints();
avail= !(pBuf->head == pBuf->tail);
avail = !(pbuf->head == pbuf->tail);
up_enableints();
/* If no RX data available then halt the processor until an interrupt */
@@ -244,19 +245,19 @@ int nr5_uart_test_rx_avail()
int nr5_uart_test_tx_empty()
{
return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
}
/* Routine to send TX byte to console UART. */
void nr5_uart_put_tx(uint8_t ch)
{
/* Wait for TX to be empty */
/* Wait for TX to be empty */
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
;
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
;
/* Write to TX */
/* Write to TX */
*g_nr5_uart1.regs->ptx = ch;
*g_nr5_uart1.regs->ptx = ch;
}
arch/risc-v/src/nr5m100/nr5_uart.h
+6 -2
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/riscv/src/nr5/nr5_uart.h
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -28,11 +28,15 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef _ARCH_RISCV_SRC_NR5_NR5_UART_H
#define _ARCH_RISCV_SRC_NR5_NR5_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifdef CONFIG_NR5_NR5M1XX