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SAMA5D23 boards: When running out of SDRAM, need to query the PMC to determine operating frequency
This commit is contained in:
Gregory Nutt
@@ -7068,4 +7068,8 @@
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* arch/arm/src/sama5/sam_pmc.c and .h: Add functions to calculate
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PLLACK, PCK, and MCK frequencies given the main clock frequency
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(2014-3-29).
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* configs/sama5d*/include/board.h, board_sdram.h, and other files:
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When booting from SDRAM, we need to query the PMC registers (using
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the functions in sam_pmc.c) to determine the MCK, PCK, etc. We assume
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that the MCK input clock is well known main crystal oscillator
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frequency (2014-3-29).
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@@ -56,6 +56,11 @@
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* Pre-processor Definitions
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****************************************************************************/
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#undef NEED_PLLSETUP
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#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
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# define NEED_PLLSETUP 1
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@@ -80,6 +85,7 @@
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static void sam_pmcwait(uint32_t bit)
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{
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/* There is no timeout on this wait. Why not? Because the symptoms there
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@@ -90,15 +96,17 @@ static void sam_pmcwait(uint32_t bit)
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while ((getreg32(SAM_PMC_SR) & bit) == 0);
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}
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#endif
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/****************************************************************************
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* Name: sam_enablemosc
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*
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* Description:
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* Enable the main osciallator
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* Enable the main oscillator
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_enablemosc(void)
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{
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uint32_t regval;
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@@ -141,6 +149,7 @@ static inline void sam_enablemosc(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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}
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#endif
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/****************************************************************************
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* Name: sam_selectmosc
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@@ -152,6 +161,7 @@ static inline void sam_enablemosc(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_selectmosc(void)
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{
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uint32_t regval;
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@@ -167,6 +177,7 @@ static inline void sam_selectmosc(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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#endif
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/****************************************************************************
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* Name: sam_pllasetup
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@@ -178,6 +189,7 @@ static inline void sam_selectmosc(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_pllasetup(void)
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{
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uint32_t regval;
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@@ -197,6 +209,7 @@ static inline void sam_pllasetup(void)
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sam_pmcwait(PMC_INT_LOCKA);
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}
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#endif
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/****************************************************************************
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* Name: sam_plladivider
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@@ -206,6 +219,7 @@ static inline void sam_pllasetup(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_plladivider(void)
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{
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uint32_t regval;
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@@ -246,6 +260,7 @@ static inline void sam_plladivider(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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#endif
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/****************************************************************************
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* Name: sam_mckprescaler
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@@ -255,6 +270,7 @@ static inline void sam_plladivider(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_mckprescaler(void)
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{
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uint32_t regval;
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@@ -270,6 +286,7 @@ static inline void sam_mckprescaler(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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#endif
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/****************************************************************************
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* Name: sam_mckdivider
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@@ -280,6 +297,7 @@ static inline void sam_mckprescaler(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_mckdivider(void)
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{
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uint32_t regval;
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@@ -295,6 +313,7 @@ static inline void sam_mckdivider(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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#endif
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/****************************************************************************
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* Name: sam_selectplla
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@@ -304,6 +323,7 @@ static inline void sam_mckdivider(void)
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*
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****************************************************************************/
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#if defined(NEED_PLLSETUP)
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static inline void sam_selectplla(void)
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{
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uint32_t regval;
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@@ -319,6 +339,7 @@ static inline void sam_selectplla(void)
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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#endif
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/****************************************************************************
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* Name: sam_usbclockconfig
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@@ -569,8 +590,8 @@ void sam_clockconfig(void)
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#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
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if (config)
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#endif /* CONFIG_SAMA5_BOOT_CS0FLASH */
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#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
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{
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#if defined(NEED_PLLSETUP)
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/* Enable main oscillator (if it has not already been selected) */
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sam_enablemosc();
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@@ -601,10 +622,10 @@ void sam_clockconfig(void)
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/* Finally, elect the PLLA output as the input clock for PCK and MCK. */
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sam_selectplla();
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#endif /* NEED_PLLSETUP */
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/* Setup USB clocking */
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sam_usbclockconfig();
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}
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#endif /* CONFIG_SAMA5_BOOT_ISRAM || CONFIG_SAMA5_BOOT_CS0FLASH */
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}
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+339
-238
File diff suppressed because it is too large
Load Diff
@@ -65,7 +65,7 @@ extern "C"
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* Name: sam_pllack_frequency
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*
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* Description:
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* Given the Main Clock frequency that provides the input to PLLA, return
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* Given the Main Clock frequency that provides the input to PLLA, return
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* the frequency of the PPA output clock, PLLACK
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*
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* Assumptions:
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@@ -76,11 +76,26 @@ extern "C"
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uint32_t sam_pllack_frequency(uint32_t mainclk);
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/****************************************************************************
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* Name: sam_plladiv2_frequency
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*
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* Description:
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* The PLLACK input to most clocking may or may not be divided by two.
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* This function will return the possibly divided PLLACK clock input
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* frequency.
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*
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* Assumptions:
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* See sam_pllack_frequency.
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*
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****************************************************************************/
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uint32_t sam_plladiv2_frequency(uint32_t mainclk);
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/****************************************************************************
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* Name: sam_pck_frequency
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*
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* Description:
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* Given the Main Clock frequency that provides the input to PLLA, return
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* Given the Main Clock frequency that provides the input to PLLA, return
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* the frequency of the processor clock (PCK).
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*
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* Assumptions:
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@@ -95,7 +110,7 @@ uint32_t sam_pck_frequency(uint32_t mainclk);
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* Name: sam_mck_frequency
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*
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* Description:
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* Given the Main Clock frequency that provides the input to PLLA, return
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* Given the Main Clock frequency that provides the input to PLLA, return
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* the frequency of the PPA output clock, PLLACK
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*
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* Assumptions:
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@@ -106,6 +121,30 @@ uint32_t sam_pck_frequency(uint32_t mainclk);
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uint32_t sam_mck_frequency(uint32_t mainclk);
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/************************************************************************************
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* Name: sam_hsmci_clkdiv
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*
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* Description:
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
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* MCI_SPEED = MCK / (CLKFULLDIV + 2)
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* CLKFULLDIV = MCK / MCI_SPEED - 2
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*
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* CLKDIV = CLKFULLDIV >> 1
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* CLOCKODD = CLKFULLDIV & 1
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*
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* Where CLKDIV has a range of 0-255.
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*
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* TODO: This belongs elsewhere
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*
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************************************************************************************/
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#ifdef CONFIG_ARCH_HAVE_SDIO
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uint32_t sam_hsmci_clkdiv(uint32_t target);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@@ -70,14 +70,6 @@
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#define PIT_PIV ((PIT_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
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/* The size of the reload field is 20 bits. Verify that the reload value
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* will fit in the reload register.
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*/
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#if PIT_PIV > PIT_MR_PIV_MASK
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# error PIT_PIV exceeds the maximum value
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@@ -149,7 +141,10 @@ void up_timerinit(void)
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* interrupts from the PIT.
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*/
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regval = PIT_PIV | PIT_MR_PITEN | PIT_MR_PITIEN;
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regval = PIT_PIV;
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DEBUGASSERT(regval <= PIT_MR_PIV_MASK);
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regval |= (PIT_MR_PITEN | PIT_MR_PITIEN);
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putreg32(regval, SAM_PIT_MR);
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/* And enable the timer interrupt */
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@@ -51,7 +51,19 @@
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* definitions will configure operational clocking.
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*/
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#if 1 /* #if !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
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#if defined(CONFIG_SAMA5_BOOT_SDRAM)
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/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader.
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* That bootloader had to have already configured the PLL and SDRAM for proper
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* operation.
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*
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* In this case, we don not reconfigure the clocking. Rather, we need to query
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* the register settings to determine the clock frequencies. We can only assume that
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* the Main clock source in the on-board 12MHz crystal.
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*/
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# include <arch/board/board_sdram.h>
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#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
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/* This is the configuration provided in the Atmel example code. This setup results
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* in a CPU clock of 396MHz.
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*
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@@ -157,7 +157,7 @@
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* Resulting frequencies */
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@@ -115,7 +115,7 @@
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* Resulting frequencies */
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@@ -0,0 +1,167 @@
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/************************************************************************************
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* configs/sama5d3-xplained/include/board_sdram.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H
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#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "sam_pmc.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. When
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* booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That
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* bootloader had to have already configured the PLL and SDRAM for proper operation.
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*
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* In this case, we don not reconfigure the clocking. Rather, we need to query
|
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* the register settings to determine the clock frequencies. We can only assume that
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* the Main clock source in the on-board 12MHz crystal.
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*/
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (sam_pllack_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_PLLADIV2_FREQUENCY (sam_plladiv2_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
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* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
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* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
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* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
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* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
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*
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* For High-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
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* selected.
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* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
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* driver is initialized.
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*/
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# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
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# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
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# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
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#endif
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/* ADC Configuration
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*
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* ADCClock = MCK / ((PRESCAL+1) * 2)
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* PRESCAL = (MCK / (2 * ADCClock) - 1)
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*/
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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#define BOARD_ADCCLK_FREQUENCY \
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((BOARD_PLLADIV2_FREQUENCY / (2 *BOARD_PLLADIV2_FREQUENCY)) - 1)
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
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* MCI_SPEED = MCK / (CLKFULLDIV + 2)
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* CLKFULLDIV = MCK / MCI_SPEED - 2
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*
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* CLKDIV = CLKFULLDIV >> 1
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* CLOCKODD = CLKFULLDIV & 1
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*
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* Where CLKDIV has a range of 0-255.
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*/
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|
||||
/* Initial clock: 400 KHz (target) */
|
||||
|
||||
#define HSMCI_INIT_CLKDIV sam_hsmci_clkdiv(400000)
|
||||
|
||||
/* MMC transfer clock: 20 MHz (target) */
|
||||
|
||||
#define HSMCI_MMCXFR_CLKDIV sam_hsmci_clkdiv(20000000)
|
||||
|
||||
/* SD transfer clock: 25 MHz (target) */
|
||||
|
||||
#define HSMCI_SDXFR_CLKDIV sam_hsmci_clkdiv(25000000)
|
||||
|
||||
#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H */
|
||||
@@ -51,7 +51,19 @@
|
||||
* definitions will configure operational clocking.
|
||||
*/
|
||||
|
||||
#if 1 /* #if !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
|
||||
#if defined(CONFIG_SAMA5_BOOT_SDRAM)
|
||||
/* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader.
|
||||
* That bootloader had to have already configured the PLL and SDRAM for proper
|
||||
* operation.
|
||||
*
|
||||
* In this case, we don not reconfigure the clocking. Rather, we need to query
|
||||
* the register settings to determine the clock frequencies. We can only assume that
|
||||
* the Main clock source in the on-board 12MHz crystal.
|
||||
*/
|
||||
|
||||
# include <arch/board/board_sdram.h>
|
||||
|
||||
#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */
|
||||
/* This is the configuration provided in the Atmel example code. This setup results
|
||||
* in a CPU clock of 396MHz.
|
||||
*
|
||||
|
||||
@@ -157,7 +157,7 @@
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
|
||||
@@ -115,7 +115,7 @@
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
|
||||
@@ -0,0 +1,167 @@
|
||||
/************************************************************************************
|
||||
* configs/sama5d3x-ek/include/board_sdram.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_SDRAM_H
|
||||
#define __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_SDRAM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Clocking *************************************************************************/
|
||||
/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. When
|
||||
* booting from SDRAM, NuttX is loaded in SDRAM by an intermediate bootloader. That
|
||||
* bootloader had to have already configured the PLL and SDRAM for proper operation.
|
||||
*
|
||||
* In this case, we don not reconfigure the clocking. Rather, we need to query
|
||||
* the register settings to determine the clock frequencies. We can only assume that
|
||||
* the Main clock source in the on-board 12MHz crystal.
|
||||
*/
|
||||
|
||||
#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
|
||||
#define BOARD_PLLA_FREQUENCY (sam_pllack_frequency(BOARD_MAINOSC_FREQUENCY))
|
||||
#define BOARD_PLLADIV2_FREQUENCY (sam_plladiv2_frequency(BOARD_MAINOSC_FREQUENCY))
|
||||
#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
|
||||
#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
|
||||
|
||||
#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
|
||||
defined(CONFIG_SAMA5_UDPHS)
|
||||
|
||||
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
|
||||
* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
|
||||
* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
|
||||
* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
|
||||
* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
|
||||
*
|
||||
* For High-speed operations, the user has to perform the following:
|
||||
*
|
||||
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
|
||||
* PMC_PCER register.
|
||||
* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
|
||||
* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
|
||||
* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
|
||||
* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
|
||||
* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
|
||||
* register.
|
||||
* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
|
||||
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
|
||||
* selected.
|
||||
* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
|
||||
*
|
||||
* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
|
||||
* driver is initialized.
|
||||
*/
|
||||
|
||||
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
|
||||
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
|
||||
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
|
||||
#endif
|
||||
|
||||
/* ADC Configuration
|
||||
*
|
||||
* ADCClock = MCK / ((PRESCAL+1) * 2)
|
||||
* PRESCAL = (MCK / (2 * ADCClock) - 1)
|
||||
*/
|
||||
|
||||
#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
|
||||
#define BOARD_ADCCLK_FREQUENCY \
|
||||
((BOARD_PLLADIV2_FREQUENCY / (2 *BOARD_PLLADIV2_FREQUENCY)) - 1)
|
||||
|
||||
#define BOARD_ADC_PRESCAL (7)
|
||||
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
|
||||
#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
|
||||
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
|
||||
|
||||
/* HSMCI clocking
|
||||
*
|
||||
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
||||
* divided by (2*(CLKDIV) + CLOCKODD + 2).
|
||||
*
|
||||
* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
|
||||
* MCI_SPEED = MCK / (CLKFULLDIV + 2)
|
||||
* CLKFULLDIV = MCK / MCI_SPEED - 2
|
||||
*
|
||||
* CLKDIV = CLKFULLDIV >> 1
|
||||
* CLOCKODD = CLKFULLDIV & 1
|
||||
*
|
||||
* Where CLKDIV has a range of 0-255.
|
||||
*/
|
||||
|
||||
/* Initial clock: 400 KHz (target) */
|
||||
|
||||
#define HSMCI_INIT_CLKDIV sam_hsmci_clkdiv(400000)
|
||||
|
||||
/* MMC transfer clock: 20 MHz (target) */
|
||||
|
||||
#define HSMCI_MMCXFR_CLKDIV sam_hsmci_clkdiv(20000000)
|
||||
|
||||
/* SD transfer clock: 25 MHz (target) */
|
||||
|
||||
#define HSMCI_SDXFR_CLKDIV sam_hsmci_clkdiv(25000000)
|
||||
|
||||
#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_SDRAM_H */
|
||||
Reference in New Issue
Block a user