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arch/arm/src/stm32f0l0g0/stm32*_pwr.c: Add some files missing in a previouis commit.
This commit is contained in:
Gregory Nutt
@@ -0,0 +1,406 @@
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/************************************************************************************
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* arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "up_arch.h"
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#include "stm32_pwr.h"
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#if defined(CONFIG_STM32F0L0G0_PWR)
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* Parts only support a single Wake-up pin do not include the numeric suffix
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* in the naming.
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*/
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#ifndef PWR_CSR_EWUP1
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# define PWR_CSR_EWUP1 PWR_CSR_EWUP
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#endif
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/************************************************************************************
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* Private Data
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************************************************************************************/
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static uint16_t g_bkp_writable_counter = 0;
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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static inline uint32_t stm32_pwr_getreg32(uint8_t offset)
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{
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return getreg32(STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value)
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{
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putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
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uint32_t setbits)
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{
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modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_pwr_initbkp
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*
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* Description:
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* Insures the referenced count access to the backup domain (RTC registers,
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* RTC backup data registers and backup SRAM is consistent with the HW state
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* without relying on a variable.
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*
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* NOTE: This function should only be called by SoC Start up code.
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*
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* Input Parameters:
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* writable - True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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void stm32_pwr_initbkp(bool writable)
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{
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uint16_t regval;
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/* Make the HW not writable */
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regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
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regval &= ~PWR_CR_DBP;
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stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
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/* Make the reference count agree */
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g_bkp_writable_counter = 0;
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stm32_pwr_enablebkp(writable);
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}
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/************************************************************************************
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* Name: stm32_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* NOTE: Reference counting is used in order to supported nested calls to this
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* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
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* be followed by a matching call to stm32_pwr_enablebkp(false).
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*
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* Input Parameters:
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* writable - True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebkp(bool writable)
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{
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irqstate_t flags;
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uint16_t regval;
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bool waswritable;
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bool wait = false;
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flags = enter_critical_section();
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/* Get the current state of the STM32 PWR control register */
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regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
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waswritable = ((regval & PWR_CR_DBP) != 0);
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if (writable)
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{
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DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
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g_bkp_writable_counter++;
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}
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else if (g_bkp_writable_counter > 0)
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{
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g_bkp_writable_counter--;
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}
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/* Enable or disable the ability to write */
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if (waswritable && g_bkp_writable_counter == 0)
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{
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/* Disable backup domain access */
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regval &= ~PWR_CR_DBP;
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stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
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}
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else if (!waswritable && g_bkp_writable_counter > 0)
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{
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/* Enable backup domain access */
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regval |= PWR_CR_DBP;
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stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
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wait = true;
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}
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leave_critical_section(flags);
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if (wait)
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{
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/* Enable does not happen right away */
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up_udelay(4);
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}
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}
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/************************************************************************************
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* Name: stm32_pwr_enablewkup
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*
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* Description:
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* Enables the WKUP pin.
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*
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* Input Parameters:
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* wupin - Selects the WKUP pin to enable/disable
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* wupon - state to set it to
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*
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* Returned Value:
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* Zero (OK) is returned on success; A negated errno value is returned on any
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* failure. The only cause of failure is if the selected MCU does not support
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* the requested wakeup pin.
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*
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************************************************************************************/
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int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon)
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{
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uint16_t pinmask;
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/* Select the PWR_CSR bit associated with the requested wakeup pin */
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switch (wupin)
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{
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case PWR_WUPIN_1: /* Wake-up pin 1 (all parts) */
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pinmask = PWR_CSR_EWUP1;
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break;
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#ifdef HAVE_PWR_WKUP2
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case PWR_WUPIN_2: /* Wake-up pin 2 */
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pinmask = PWR_CSR_EWUP2;
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break;
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#endif
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#ifdef HAVE_PWR_WKUP3
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case PWR_WUPIN_3: /* Wake-up pin 3 */
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pinmask = PWR_CSR_EWUP3;
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break;
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#endif
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default:
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return -EINVAL;
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}
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/* Set/clear the the wakeup pin enable bit in the CSR. This must be done
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* within a critical section because the CSR is shared with other functions
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* that may be running concurrently on another thread.
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*/
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if (wupon)
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{
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/* Enable the wakeup pin by setting the bit in the CSR. */
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stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask);
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}
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else
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{
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/* Disable the wakeup pin by clearing the bit in the CSR. */
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stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0);
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}
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return OK;
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}
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/************************************************************************************
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* Name: stm32_pwr_getsbf
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*
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* Description:
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* Return the standby flag.
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*
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************************************************************************************/
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bool stm32_pwr_getsbf(void)
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{
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return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_SBF) != 0;
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}
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/************************************************************************************
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* Name: stm32_pwr_getwuf
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*
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* Description:
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* Return the wakeup flag.
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*
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************************************************************************************/
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bool stm32_pwr_getwuf(void)
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{
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return (stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_WUF) != 0;
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}
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/************************************************************************************
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* Name: stm32_pwr_setvos
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*
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* Description:
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* Set voltage scaling for EnergyLite devices.
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*
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* Input Parameters:
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* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* At present, this function is called only from initialization logic. If used
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* for any other purpose that protection to assure that its operation is atomic
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* will be required.
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*
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************************************************************************************/
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#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
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void stm32_pwr_setvos(uint16_t vos)
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{
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uint16_t regval;
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/* The following sequence is required to program the voltage regulator ranges:
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* 1. Check VDD to identify which ranges are allowed...
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* 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
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* 3. Configure the voltage scaling range by setting the VOS bits in the PWR_CR
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* register.
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* 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
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*/
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while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0)
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{
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}
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regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
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regval &= ~PWR_CR_VOS_MASK;
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regval |= (vos & PWR_CR_VOS_MASK);
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stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
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while ((stm32_pwr_getreg32(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0)
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{
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}
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}
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/************************************************************************************
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* Name: stm32_pwr_setpvd
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*
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* Description:
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* Sets power voltage detector
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*
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* Input Parameters:
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* pls - PVD level
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* At present, this function is called only from initialization logic. If used
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* for any other purpose that protection to assure that its operation is atomic
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* will be required.
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*
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************************************************************************************/
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void stm32_pwr_setpvd(uint16_t pls)
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{
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uint16_t regval;
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/* Set PLS */
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regval = stm32_pwr_getreg32(STM32_PWR_CR_OFFSET);
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regval &= ~PWR_CR_PLS_MASK;
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regval |= (pls & PWR_CR_PLS_MASK);
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/* Write value to register */
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stm32_pwr_putreg32(STM32_PWR_CR_OFFSET, regval);
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}
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/************************************************************************************
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* Name: stm32_pwr_enablepvd
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*
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* Description:
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* Enable the Programmable Voltage Detector
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*
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************************************************************************************/
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void stm32_pwr_enablepvd(void)
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{
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/* Enable PVD by setting the PVDE bit in PWR_CR register. */
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stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, 0, PWR_CR_PVDE);
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}
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/************************************************************************************
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* Name: stm32_pwr_disablepvd
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*
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* Description:
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* Disable the Programmable Voltage Detector
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*
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************************************************************************************/
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void stm32_pwr_disablepvd(void)
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{
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/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
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stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
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}
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#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
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#endif /* CONFIG_STM32F0L0G0_PWR */
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@@ -0,0 +1,112 @@
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/****************************************************************************
|
||||
* arch/arm/src/stm32f0l0g0/stm32g0_pwr.c
|
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*
|
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Daniel Pereira Volpato <dpo@certi.org.br>
|
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*
|
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* Based on: arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
#if defined(CONFIG_STM32F0L0G0_PWR)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t stm32_pwr_getreg32(uint8_t offset)
|
||||
{
|
||||
return getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_putreg32(uint8_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_pwr_setvos(uint16_t vos)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* The following sequence is required to program the voltage regulator
|
||||
* ranges:
|
||||
* 1. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2).
|
||||
* 2. Configure the voltage scaling range by setting the VOS bits in the
|
||||
* PWR_CR1 register.
|
||||
* 3. Wait until VOSF flag is cleared in Power Status register 2 (PWR_SR2).
|
||||
*
|
||||
* No checking is performed to ensure the VOS value to be set is within the
|
||||
* valid range.
|
||||
*/
|
||||
|
||||
while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = stm32_pwr_getreg32(STM32_PWR_CR1_OFFSET);
|
||||
regval &= ~PWR_CR1_VOS_MASK;
|
||||
regval |= (vos & PWR_CR1_VOS_MASK);
|
||||
stm32_pwr_putreg32(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
while ((stm32_pwr_getreg32(STM32_PWR_SR2_OFFSET) & PWR_SR2_VOSF) != 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/* TODO Other stm32_pwr_* functions need to be implemented */
|
||||
|
||||
#endif /* CONFIG_STM32F0L0G0_PWR */
|
||||
Reference in New Issue
Block a user